Hafnia and alumina stacks as UTBOXs in silicon-on insulator

Journal Pre-proofs Hafnia and alumina stacks as UTBOXs in silicon-on insulator V.P. Popov, V.A. Antonov, A.K. Gutakovskiy, I.E. Tyschenko, V.I. Vdovin, A.V. Miakonkikh, K.V. Rudenko PII: DOI: Reference:

S0038-1101(19)30737-3 https://doi.org/10.1016/j.sse.2019.107734 SSE 107734

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Solid-State Electronics

Please cite this article as: Popov, V.P., Antonov, V.A., Gutakovskiy, A.K., Tyschenko, I.E., Vdovin, V.I., Miakonkikh, A.V., Rudenko, K.V., Hafnia and alumina stacks as UTBOXs in silicon-on insulator, Solid-State Electronics (2019), doi: https://doi.org/10.1016/j.sse.2019.107734

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Hafnia and alumina stacks as UTBOXs in silicon-on insulator V.P. Popov a, V.A. Antonov a, A.K. Gutakovskiy a, b, I.E. Tyschenko a, V.I. Vdovin a, A.V. Miakonkikh c, K.V. Rudenko c

Vladimir Popov a Laboratory of Silicon Material Science Rzhanov Institute of Semiconductor Physics SB RAS Novosibirsk, Russia [email protected] • Corresponding author. Valentin Antonov a Laboratory of Silicon Material Science a

Rzhanov Institute of Semiconductor Physics SB RAS

Novosibirsk, Russia [email protected] Anton Gutakovskiy a Laboratory of Nanodiagnostics and Nanolithography a

Rzhanov Institute of Semiconductor Physics SB RAS

b

Novosibirsk State University, Russia

Novosibirsk, Russia [email protected] Vladimir Vdovin a Laboratory of Nanodiagnostics and Nanolithography a

Rzhanov Institute of Semiconductor Physics SB RAS

Novosibirsk, Russia [email protected] Ida Tyschenko a Laboratory of Nanodiagnostics and Nanolithography a

Rzhanov Institute of Semiconductor Physics SB RAS

Novosibirsk, Russia [email protected]

Andrey Miakonkikh c Laboratory of Microstructuring and Submicron Devices c

Valiev Institute of Physics and Technology

RAS, Moscow, Russia [email protected] Konstantin Rudenko c Laboratory of Microstructuring and Submicron Devices c

Valiev Institute of Physics and Technology

RAS, Moscow, Russia [email protected]

Abstract— PEALD-grown hafnia and alumina buried oxide (BOX) stacks in silicon-on-insulator (SOI) structures were produced and characterized by XTEM and pseudo-MOSFET techniques. The ferroelectric phases of hafnia were observed by XTEM and SAED. It was shown that the minimal interface states density (IFS) < 1012cm-2 and the maximal one with a memory window MW ~ 1 V could be obtained by the right choice of high-k dielectric layer sequence in BOX stack and thermal processing.

1. Introduction The ultrathin body and buried (UTBB) oxide in SOI structures with an equivalent oxide thickness (EOT) below 10 nm are promising for two-gate field effect transistors (2G FD SOI FETs) operating in the symmetric or asymmetric mode and low voltage embedded non-volatile memory (e-NVM). The silicon dioxide thickness value with an EOT below 10 nm leads to manifold defects in the SOI layer after a high temperature treatment due to an oversaturation of BOX by hydrogen atoms and their accumulation in the gas blisters at Si/SiO2 interfaces [1]. To avoid this obstacle, the utilizing of thicker high-k dielectric alumina instead of silica was proposed for UTBB SOI [2]. The minimal EOT = 7.9 nm for a stack with alumina was obtained due to relatively thick SiO2 capping layers deposited to reach a low IFS density in the mid 1011 eV−1.cm−2 range. Moreover, high negative effective interface charge density 3x1012 cm−2 was saved even after the annealing at 1200oC. There is a well-known approach to reducing the inherent charge in the high-k stack by using a dipole interface between different dielectrics [3]. But we could not find any data about the high-k stack behavior, in the case of using it as the BOX in SOI structures at a high temperature treatment, in the literature. Moreover, our previous investigation of the hafnia interlayer between silicon and sapphire shows a partial compensation of the large positive charge in the silicon-on-sapphire (SOS) heterostructure [4]. A large hysteresis was observed in the I-V characteristics of drain current – gate voltage IDS(VG) curves for SOS pseudo-MOSFETs. Two orthorhombic, noncentrosymmetric space groups Pca21 and Pmn21 were considered as the sources of ferroelectricity (FE) in HfO2 [5, 6]. The Pca21 phase was identified in an electron diffraction study as the most likely source of ferroelectricity [7], but the Pmn21 phase is often cancelled as such source, despite the observed hysteresis with the Al doping [8]. The observations of Pmn21 phases have been reported recently [4, 9]. The aim of our study was investigating the structural and electric properties of SOI structures with different stacks including hafnia and alumina as BOX dielectrics grown by the plasma-enhanced atomic layer deposition (PEALD) method. Different thicknesses and layouts were investigated in our

experiments, but the total BOX stack thickness did not exceed 30 nm or the BOX EOT was below 5 nm.

2. Experimental The transfer of the only (100) silicon layer (n-type, 10-20 Ohmcm and electron density n = (35)х1014 cm-3) on Si substrates covered by high-k dielectric stacks was carried out by implanted hydrogen according to the patented technology [10]. The hafnia and alumina layers (PEALD HfO2 or Al2O3) with thicknesses from 1ML to 20 nm were grown at 300оС on Si wafers from TEMAH and TMA precursors using oxygen plasma, respectively. Immediately before the bonding, the wafer pairs of high-k covered Si-wafer and hydrogen-implanted Si-wafer were subjected to a treatment in O+ or N+ plasma, and the resulting SOI structures with a transferred Si layer (0.5 µm) were annealed in the Ar atmosphere in the temperature range of 800-1100 оС for 1 hour (Fig. 1).

Fig. 1. 4” SOI wafers with three different high-k UTBOX stacks (from left to right): Al2O3 20 nm; Al2O3 10 nm / HfO2 10 nm; HfO2 6 nm / Al2O3 8 nm / HfO2 6 nm. The different SOI-wafers colors in the images are due to the differences in the optical properties of BOX-stacks. The UTBOX layer composition and structural properties were determined by the transmission electron microscopy cross-section (X-TEM) with selective area electron diffraction (SAED), including the 0.06 nm high-resolution (HRTEM) mode, and the energy dispersion analysis X-ray (EDAX), using FEI Titan 80-300 and JEM2000FX scanning transmission electron microscopes, respectively (Fig. 2, 3). The electric properties of SOI structures were determined from the drain-gate characteristics of pseudo-MOSFETs, with the tungsten needle tip radius of 20 µm and the pressing force of 60 g used as drain-source contacts, and Si substrates as a gate electrode. The C-V and I-V measurements with the tungsten needle tip radius of 60 µm were used after the SOI layer chemical etching to characterize the breakdown voltage and leakage currents in the BOX dielectric stacks and Si substrates (Fig. 4, 5).

3. Results and Discussion Comparison of HRTEM and SAED data The structural properties and composition of SOI and BOX layers were determined using electron microscopy (Fig. 2, 3). The transferred Si-layers in SOI wafers after annealing at temperatures above 1000 оС have almost no defects and do not differ in their structure essentially from the similar SOI wafers with the silica BOX. The originally amorphous/nanocrystalline PEALD HfO2 and Al2O3 layers are recrystallized in clearly observed multi-crystalline layers above 800 and 1000 оС, respectively. The cross-section HRTEM image of BOX HfO2 10 nm / Al2O3 10 nm layers is shown in Figure 2a. The result of annealing is also the formation of intermediate layers between silicon and PEALD oxides, which contain, according to EDAX, mainly silicon and oxygen. Figure 2d shows the results of hafnia bicrystal simulation using orthorhombic HfO2 phase Pmn21 with two different HfO2 orientations relative to the (100) Si substrate [001]  [1-10] and [3-11]  [1-10], respectively. Figures 2 and 3 represent also the results of the Fast Fourier Transform Image (FFT) analysis and plane spots simulation in the program CaRIne Crystallography (v. 3.1) for two different SOI cross-sectional HRTEM images with the three different crystallites of the same HfO2 orthorhombic phase Pmn21 and elemental cell parameters: a = 3.41 Å, b = 5.18 Å, c = 3.83 Å, β = 90°, γ = 84.3° similar to [6]. We observed previously the Pmn21 phase for silicon-on-sapphire (SOS) with a hafnia interlayer [4], but the followed analysis of this sample showed the presence of the orthorhombic Pca21 phase in other points, too, corresponding to the strong orientation of Pca21 phase [100] axis parallel to the [-110] axis of (100) Si layer in the SOS structure. The SOI wafer (from Fig.1, 2) with a PEALD Al2O3/HfO2 stack also shows the large crystallites with the orthorhombic Pmn21 phase of HfO2. In the SOI structure we observed for two crystallites a strong orientation of the Pmn21 phase [001] axis of hafnia parallel to the [1-10] axis of (001) Si layers, but differently turned around this axis (Fig. 2, 3). There are also, on the FFT maps in Fig.2a, 3a, 3b, the “forbidden” spots from the (010) plane family due to its small misalignment. The Al2O3 layer in the stack is nanocrystalline and had not any influence on the preferred hafnia orientation in SOI structures even after the annealing at 1100oC during 1 hour (Fig. 2a). It means that the preferential orientation of hafnia crystallites is determined by the heteroepitaxial solid state recrystallization from the silicon layer and substrate in SOI structures.

Pr

Fig. 2. a) HRTEM cross-section image of the SOI wafer with the BOX PEALD HfO2 10 nm / Al2O3 10 nm layers deposited on the Si substrate before bonding and annealed at 1100oC for 1 hour. In the inserts are the enlarged images of two hafnia crystallite structures divided by a white dashed line with proper Fast Fourier Transform (FFT) maps under the nanocrystalline /amorphous Al2O3 thin layer and (100) Si layer with the thickness of 500 nm; b) - FFT experimental image from the HRTEM cross-section micro-image of the SOI wafer (from Fig. 2a) with two HfO2 Pmn21 crystallites and the Si substrate; c) - calculated corresponding three reciprocal-oriented lattices for Si and HfO2 lattices with green, red, and blue circles, respectively; d) - hafnia reciprocal-oriented lattice for the mutual axis orientation [001]  [110] of silicon; and e) – fthe same for the [3-11]  [1-10] axis. Color circles for two reciprocal HfO2 lattices are at the coincided latice planes for hafnia and silicon.

Pr

Fig. 3. a) FFT map from the HRTEM cross-section image of the SOI wafer (another point) with HfO2 Pmn21 plane spots turned around the [001] axis relative to the one in Fig.2b, silicon substrate plane spots and the “amorphous-like” halo from nanocrystalline alumina; b) the corresponding two reciprocal-oriented lattice spots of hafnia and silicon with red and green circles, respectively, for the mutual axis orientation [001]  [1-10] (see main text for white arrow). A possible reason of the differences between SOS and SOI hafnia is the large stress in the HfO2 interlayer in the SOS heterostructure, where, according to Raman scattering, the Si layer is under the biaxial compressive stress as high as 1 GPa [11]. No essential stresses in Si layers were measured by Raman spectroscopy in SOI wafers [12]. Other mechanisms can be responsible for the Pmn21 phase stabilization including interface dipoles, charges or interface structures. Considering two different SOS and SOI heterostructures we should conclude that stresses and interface lattice structures of silicon and sapphire are among the major reasons for the hafnia properties in the SOS, while only the Si lattice interfaces are the phase-stabilizing factor in the SOI structure. It means that the chemical roles of the same interface elements for both SOS and SOI stacks are negligible in the phase stabilization. Really, the occurrence of the hafnia reciprocal lattice spots on the blue straight lines between the main silicon reciprocal lattice spots indicates the existence of the hafnia lattice turn angles relative to the Si lattice, when more than one interplanar spaces between direct lattices coincide (Fig. 3). One tilted plane correlates with Si planes for the SOS structure, while another HfO2 plane is tilted relative to the sapphire planes [4]. It provides a minimal density of broken bonds and minimal stresses at both interfaces.

CV properties of BOX SOI structures after annealing Metall-Oxide-Semiconductor (MOS) structures were used to characterize BOX high-k dielectric stacks. Silicon layers were paterned by chemical etching after annealing of SOI waferses. The typical values of effective dielectric constant ε for HfO2/Al2O3 stacks were ε = 15 - 23 for the 1 kHz frequency and slowly decreased with increasing the annealing temperature T  900oC or part of the Al2O3 thickness in the stack even after the RTA temperatures T  800oC. Carrier-transport and charges in pseudo-MOSFETs The transport properties measurement was carried out using the Y-function of the pseudo-MOS field effect transistors (FET) with a field gate from the substrates [4]. The effective positive charge Qox at the interface of Si layer and high-k BOX was large enough almost for all measured structures leading to a negative shift of the curves relative to Vsubstrate = VG = 0 V (Fig. 4a). More symmetric characteristics of SOI pseudo-MOSFETs were observed only for the SOI structures with a HfO2 BOX thickness tHfO2 < 30 nm after the annealing at T < 800oC (Fig. 4b). But the incomplete removal of defects is expressed, in this case, in lower electron mobility μе= βе2/ (fG COX VDS) ~75 cm2/(Vs), where βе is the slope of Y-function, fG = 0.75 is the geometric coefficient, COX and VDS are the BOX capacitance and drain voltage, respectively. Increasing the annealing temperature for SOI wafers also leads to the increase in asymmetry due to the effective positive charge at the Si/BOX interface and to lower electron mobility μе= ~50 cm2/(Vs). The IDS(VG) characteristics for both SOI and SOS pseudo-MOS FETs with high-k stack interlayers after the annealing at 1000oC are shown in Fig. 5. High drain currents (~1 A) are observed even at Vsubstrate =VG =0 V due to a positive charge in the BOX and the defects in the BOX dielectric stack. The currents are increased rapidly at VG < -2 V or VG > 0.5 V. This asymmetry is another evidence of the BOX charge. Immediately, after the Si layer transfer and annealing at 450oC 1h, those currents were less than 100 nA and decreased to 0.1-0.01 nA after annealing at 600-800oC. The nonmonotonic behavior is the result of annealing the point defects and the grain boundaries formation with the increased electric conductivity due to the high-k oxide recrystallization starting at 800oC. The most intriguing difference between SOS and SOI pseudo-FeFETs is a large hysteresis for the first type of heterostructures [4]. We suggested that in-plane compressive stress is a major reason for this. But according to mutual researches, tensile stresses provide the highest polarization for the Hf0.5Zr0.5O2 (HZO) solid solution (see review [13]).

Fig. 4. Y-functions for pseudo-MOS transistors with a 20 nm thick HfO2 interlayer for the SOS after the annealing at 1100°С (a), and SOI after the annealing at 800°С (b) during 1 hour. The bonding interface is shown for comparison in the insets by solid red lines. Only one report, where RTA at 700oC was used for the HZO/GaN heterostructure, gives an exact evidence for the compressive stress enhancement of the ferroelectricity in HZO due to a large lattice mismatch [14]. In our case the strong ferroelectricity was observed by us in the pure hafnia interlayer for SOS, and the weaker one-in the Al2O3/HfO2 stack for SOI structures, where only O or Si, or Al impurity atoms could diffuse through interface boundaries during high temperature treatments in SOI and SOS heterostructures. No evidences were obtained by EDS measurements about the occurrence of Hf or Al atoms in the SiOx interlayers grown between silicon and the highk dielectric. But in order to avoid this interdiffusion, we also used rapid thermal annealing (RTA) during 30 s at the same temperature interval, and also to prevent an excess of SiOx interlayer growth. No large negative shifts for the IDS(VG) characteristics were observed for such annealing up to 950oC (Fig. 6). Moreover, the BOX charge sign strongly depends on the stack combinations, layer thicknesses and orders showing the usual charge signs and interface dipole orientations, according to the reported data in the literature (see [3]). Pure negative and small positive charges were observed by the pseudo-MOSFETs IDS(VG) measurements for only HfO2 BOX layer and the HfO2 BOX layer doped by the insertion of 1ML of Al2O3 between 10ML of HfO2 during the PEALD growth with an additional pure 2 nm Al2O3 layer in order to suppress the oxygen loss in the SiOx interlayer formation [15] (Fig. 6). The bonding interface was between the Si layer and high-k BOX in all cases. The leakage current was the lowest for a thicker Al2O3 layer, but, in all cases, they started rapidly being increased at +2 V in the dependence on the stack order, or at 2 V for the symmetrical HfO2/Al2O3/HfO2 stack (not shown here). The interface state densities Dit(n.p) were determined from the IDS(VG) curves and Y-functions

according to the formula (1) from our previous report [4]. They were below 1012cm-2V-1, when the hafnia layer in the stacks was at the interface with the silicon layers. The hysteresis for pseudoMOSFETs with the pure HfO2 BOX in Fig. 6a-c is closed when the sweeping rate exceeds 50 V/s and can be introduced by the charge trapping from the Si substrate on the centers inside hafnia.

Fig. 5. a), b), d) - IDS(VG) characteristics of the SOI pseudo-MOS transistors with HfO2/Al2O3 stacks (in the inserts) with the thickness of 20 nm after the furnace annealing at 1000°С for 1 hour. IDS(VG) SOS pseudo-MOSFET graphs with the x-axis and memory window (MW) in kV is shown for comparison in c) after the furnace annealing at 1100°С for 1 hour from [4]. A relatively small FE clockwise or counter-clockwise hysteresis was observed for pure HfO2 for both electrons and holes, and only the counter-clockwise hysteresis for the HfO2/Al2O3 stacked high-k BOX after the RTA at 950oC, even for Vsubstrate > 2 V or E > (1-2)106 V/cm (Fig.6). It can be increased by changing pure HfO2 layers for a highly reliable ferroelectric Hf1-xZrxO2 (HZO) film at x ~ 0.25 [16], or for Hf0.5Zr0.5O2 with the embedded Al2O3 monolayer doping technique to suppress the Zr diffusion, similar to the IEDM-2018 report [17]. But another reason seems more likely. The polarisation direction lies for the HZO along [110] axis [18, 19].

Fig. 6. IDS(VG) characteristics of SOI pseudo-MOSFETs after the RTA annealing at 950°С 30 s: with the HfO2 BOX thickness of 20 nm only (a); with the HfO2:Al2O3 (10:1) superlattice BOX thickness of 20 nm and additional 2 nm Al2O3 layer (b); with 12 nm HfO2 and 8 nm Al2O3 thickness of the BOX stack (c); with 10 nm Al2O3 and 10 nm HfO2 thickness of the BOX stack, respectively (d). But this direction for all studied here crystallites in the high-k SOI BOX with hafnia or hafniaalumina stacks lies practically parallel to the (001) surface plane of Si lattice with the deviation angles 5o or -20o (see the white arrows in Fig. 2 and 3). If the polarization angles for HZO and our high-k hafnia based BOX Pmn21 crystallites coincide, the FE hysteresis will be small.

4. Conclusions

The results obtained by structural and electrical measurements show the promising properties of high-k UTBOX SOI structures for their further applications in both energy effective 2G FD SOI FETs and VLSI circuits, as well as in ferroelectric FETs for embedded nonvolatile memories and

neuron networks. It was shown that FE phases in SOS structures are stabilized by the biaxial compressive stress, while for SOI structures Si-interface boundaries are responsible for the large grains of FE phase stabilization for SOI structures. The qualitative models are proposed to explain the observed orientations of large FE grains of hafnia in the BOX and the weak polarization in the transversal electric field. The high temperature furnace annealing at T  900oC leads to the formation of SiOx interlayers between silicon and high-k stacks. These interlayers introduce a high effective positive charge determining the negative flatbands and threshold shifts in both SOS and SOI pseudo-MOSFETs. The suggested use of RTA provides removing these shifts, but limits the whole thermal budget during the further thermal procedures. A relatively small FE hysteresis for a pure HfO2 or HfO2/Al2O3 stacked high-k BOX can be increased by changing HfO2 layers for a highly reliable ferroelectric Hf0.5Zr0.5O2 (HZO) film with the SrTiO3 interlayers to provide large polarization Pr perpendicular to the layers [19]. Parallel polarization can be in demand for high-k UTBB SOI double gate FETs without FE hysteresis.

Highlights – In SOI pseudo-MOSFETs with 20 nm hafnia alumina interlayers show normal gatedrain characteristics after an RTA  950oC with the charge-carrier mobilities below the same in a thick silica BOX.

A highly stable ferroelectric hysteresis was observed in the case of SOI pseudo-MOSFETs with high oxygen vacancy concentrations in the UTBOX HfO2/Al2O3 stack after a furnace annealing  900oC due to the formation of the SiOx interlayers between silicon and high-k stacks.

The formation of a HfO2 film, having ferroelectric phase OII (Pmn21), is stabilized by a compressive stress in the case of SOI pseudo-MOSFETs. Keywords – hafnia and alumina high-k BOX, ferroelectric phase, SOI pseudo-MOSFETs, interface states, interface polarization.

Acknowledgements All authors and co-authors declare no competing financial interest.

The authors thank M.A. Ilnitsky and A.A. Gismatulin from ISP SB RAS for their help in electrophysical measurements. Funding: This work was partially funded by RFBR grants no.1842-540008 and no.19-03031, RSCF grant no. 19-72-30023, and by the Ministry of Science and Higher Education of Russia, programs no. 0306-2019-0005, and no. 0066-2019-0004.

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