HBT IC manufacturability and reliability

~

Pergamon

Solid-State Electronics Vol. 41, No. 10, pp. 1591-1598,1997 © 1997Published by ElsevierScienceLtd. All rights reserved Printed in Great Britain PII: S0038-1101(97)00111-1 0038-1101/97 $17.00+ 0.00

HBT IC M A N U F A C T U R A B I L I T Y A N D RELIABILITY MADJID HAFIZI Hughes Research Lab, 3011 Malibu Canyon Rd, Malibu, CA, 90265, U.S.A. (Received 11 October 1996)

Abstract--HBT based integrated circuits have reached LSI levels of integration complexity with both GaAs- and InP-based technologies. A wide range of application areas are suitable for HBT integrated circuits ranging in frequencies from below 1 GHz to above 40 GHz. In this article we will present manufacturability and reliability of these technologies with particular emphasis on InP-based HBT IC's. Technology requirements for different application areas are presented with specific integrated circuit examples. Key HBT reliability issues are also presented including discrete devices and IC reliability. © 1997 Elsevier Science Ltd

1. INTRODUCTION HBT has emerged as a key enabling technology for wireless communications, high data rate fiber-optic communication, and data conversion. For wireless applications, there is presently much interest for HBT circuits of low to medium complexity in the 0.8 to 2.5 GHz frequency range. The HBT power amplifiers[l] are particularly attractive in this application area for their high efficiency, high power density, high linearity and low intermodulation distortion characteristics. The HBT power amplifiers are particularly important for code-division-multiple-access (CDMA) transmission systems[2]. Other attractive features of HBT IC's for the wireless market include single supply operation, availability of on-chip passive components, low phase noise and gain-bandwidth product. Commercial products are now available for the wireless market. The key requirements of this application area are high volume production and very low-cost chip sets. Analog-to-digital conversion is another key application area for HBT IC's which requires LSI levels of circuit complexity. Sampling rates of up to 8 giga-sample-per-second (GSPS) were reported using both the GaAs and InP-based technologies[3-5]. High-speed HBT-based ADC's are particularly in demand for direct sampling receivers in satellite and radar applications. Muti-gigasample per second ADC's greatly simplify receiver architectures by digitizing the analog signal closer to the sensor, thus reducing or eliminating the need for analog downconversion stages. For ADC's operating at greater than 4 GSPS, the speed of the device technology is a limiting factor[6]. This limit is related to the regeneration time constant of comparator(s) in the ADC architecture. The comparator performance can be directly related to the RF performance of the technology used to fabricate the ADC. To achieve

sample rates of 10 GSPS and greater, a device technology with 200GHz RF performance is required. Another limitation of ADC's is the power dissipation which increases with higher ADC performance. To meet these requirements and fully utilize the potential of HBT technology, ultra-highspeed performance is required with devices scaled to submicron dimensions. InP-based HBT technology is particularly attractive for low-power, high-speed IC's because it has a turn-on characteristic comparable or lower than that of silicon bipolar transistors. For high data rate optical communication applications, there was significant progress in development of circuits for up to 40 Gbit/s as well as monolithic optoelectronic integrated circuits[7-10]. Typical circuits include multiplexer/demultiplexers, clock and data recovery circuits, frequency dividers and receiver circuits. For long wavelength communications (1.3-1.55/~m wavelength) the InP-based HBT technology is particularly attractive for monolithic integration of p-i-n photodetectors and transimpedance amplifiers[9]. The InP HBT technology is also attractive for ultrafast circuits required for high data rate communications. The circuits involved in this application area are medium complexity with only minimal extra processing required for monolithic integration of p-i-n photodiodes. Impressive device performance was also reported for both GaAs- and InP-based HBT technologies. InP-based HBT's have exhibited[11] fT of 228 GHz and fmax of 227 GHz. Significant progress was also made in establishing the long-term reliability of HBT's as the technology is maturing into the manufacturing phase[12-15]. Mixed-mode, multiple device integration are also emerging technologies which add functionality to HBT integrated circuits. Monolithic integration of HBT and RTD can potentially reduce the circuit complexity by taking advantage of the negative

1591

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Madjid Hafizi

resistance feature of the RTD to perform latching functions, thus reducing device count in complex circuits. Integration of HBT and HEMT is attractive for receiver applications where the low noise amplifier function is best suited for the HEMT technology, while HBT can provide down conversion, gain, and ADC functions. At Hughes, we have concentrated on InP-based HBT's for a number of different integrated circuit applications[16-17]. Our versatile, multi-function IC process is used for development of A/D converters, optoelectronic circuits, high-data rate communication circuits, and internal ASIC applications. We also have multiple efforts in monolithic integration of HEMT/HBT, RTD/HBT, and P I N photo-detector/ HBT for multi-function, mixed-signal IC applications. Our baseline IC process offers 2 x 2 lLm2 emitter transistors with fT and fmax of 80--100 GHz. With an epitaxial profile optimized for speed, we can achieve 170 G H z f r with good uniformity across a 3 inch wafer. Our process is based on stepper lithography on 3 inch substrate and in addition to HBT, it offers TaN thin-film resistors, MIM capacitors and two levels of metal interconnect. Base-collector junction P I N photo-detectors are available with some additional process steps. Coplanar integration of HEMT or RTD is also possible with patterning of the substrate prior to MBE growth and some additional process steps. Recently we have concentrated on improving the yield and uniformity of our baseline IC process and are now able to yield circuits with a complexity of over 1000 transistors. To improve the IC yield and uniformity we are applying semiconductor manufacturing techniques such as Statistical Process Control (SPC). Design of Experiments (DOE), and Pareto Analysis. We have included an extensive set of process control monitors (PCM) on each mask set (approx. 20% of our stepper reticule). The PCM include a wide range of test structures designed for automated wafer testing. We use these test structures to monitor HBT device parameters, device yield, metalization and via yields, and contact and sheet resistances. Simultaneously, we are developing a next generation, manufacturable IC process based on scaling of device lateral dimensions and vertical epitaxial layer thicknesses. This effort also includes scaling of interconnect metalization pitch and via dimensions. We have demonstrated[18] a scaler transistor technology with emitter dimensions as small as 0.3 #m 2 and fr, f~ax of greater than 120 GHz. In this new process we rely heavily on dry etching techniques for defining mesas and forming dielectric sidewalls. The ultimate usefulness of HBT technology for system applications is dependent on its reliability performance. We have undertaken[12] an extensive and systematic study of reliability of InP-based device and IC technology including physics and device failure and reliability statistics. With over 12000

hours of accelerated lifetest on discrete devices, we are able to project mean-time-to-failures of 107 hours at 125°C junction temperatures. We are presently pursuing IC reliability qualifications for satellite payloads and for airborne applications. We have performed accelerated lifetests on digital circuits stressed at a constant d.c. bias at elevated temperatures. The high-frequency performance of these circuits were monitored at room temperature. The high-frequency performance of these circuits were monitored at room temperature. Based on these lifetests, we have developed IC design and transistor operating limits to improve long-term circuit stability. In this article we will present The InP-based HBT process at Hughes and the manufacturing techniques being applied to monitor and improve yield. This is followed by a discussion of our next generation HBT technology with submicron dimensions. Next, some representative integrated circuits are presented with performance results. Finally, the reliability aspects of the technology are covered for both discrete transistors and integrated circuits. 2. FABRICATION

Single heterojunction bipolar transistors with AllnAs emitter and GalnAs base and collector are grown by our conventional solid-source MBE machine. The key features of our graded junction MBE profile are a GalnAs base with thickness of approximately 60 nm doped at 2.5 x 1019cm -3 with Be and a GalnAs collector with thickness of 700 nm doped at 5 x 10~5cm -3 with Si. The A l l n A s emitter is 120 nm thick and doped at 8 x 1017cm -3 with Si. The base-emitter junction is compositionally graded over a distance of 30 nm. This epitaxial structure results in a transistor with a f r and fmax of around 80 GHz and a d.c. current gain of greater than 40. With the compositionally graded emitter-base junction, the transistor exhibits a turn-on voltage, VBE, less than that of the silicon bipolar transistors with nearly ideal base and collector current characteristics. Our HBT IC process uses a triple-mesa approach to access the base and collector and to isolate the device. Non-alloyed Ti/Pt/Au are used for the emitter and base ohmic contacts and AuGe/Ni/Au for the collector contacts. Subsequently, thin-film resistors (TFR) and metal-insulator-metal (MIM) capacitors are fabricated on the substrate. The mesa structure resulting from the device fabrication is planarized by polyimide which is then etched back by reactive ion etching (RIE) to expose the emitter tops. Via holes are subsequently etched in the polyimide using RIE to reach the base and collector and the resistor and capacitor terminals. The second level of metalization is patterned over the polyimide for interconnection. The schematic cross-section of a planarized HBT with passive components and interconnects is shown in Fig. 1.

HBT IC Manufacturability and reliability Via

mide 2nd Level Poly: I Metal !

ThinFilm Resistor/

~

1 0 k c /_ Dielectric Epi Resistor Metal

lStLevel Metal

BonLg Pad

Fig. 1. Schematic cross-section of a planarized HBT with passive components and interconnects. To increase the fT of the transistor, we reduce the collector thickness, while for improving the d.c. current gain reducing the base thickness is effective[17]. Figure 2 shows the contour maps offT for two different epitaxial structures. One incorporates a collector thickness of 700 nm and a base of 60 nm, the other one features a collector of 250 nm and a base of 25 nm (doped with Be at 6 x 1019cm-3). The d.c. current gain for the profile with thinner base was 75 at arc = 5 x 104 A cm -2. 3. MANUFACTURABILITY To evaluate and improve the yield of the IC process we employ classical Pareto analysis techniques. To identify the major causes of yield loss we performed detail inspection of a particular circuit across the wafer and identified all major contributors to loss of functionality. Some examples are deformity in the emitters, surface particles, MBE defects, polyimide defects, and so forth. Pareto analysis reveals the most critical cause of yield loss in the IC process. To improve yield and manufacturability, tradeoffs must be considered between circuit corn-

1593

plexity, transistor count, die size, feature sizes, layout and design rules, and cycle time. It is, therefore, essential to understand the process capability, the control over the process, and the equipment. The best approach to continuously assess this is through the use of statistical process control (SPC). SPC requires inputs from critical on-line processes, electrical measurements of process control monitors (PCM) placed on every wafer, and finally charting of parametric outputs in the form of control charts, wafer maps, trend charts, and so forth. The online processes that we monitor include metal thicknesses (emitter, base, collector, and interconnect metals), dielectric thicknesses and index of refraction. For thin-film resistors we monitor the etch rate, sheet resistance, and thickness. For photolithography we monitor resist thicknesses. Control charts generated from this data reveal which processes are under control and which need improvement. In addition to on-line process monitoring, electrical characterization is performed on individual test transistors and on test structures to measure sheet resistances, contact resistances, via chains, contact chains, metal-metal separations, and so forth. From the measured transistor data we can extract key HBT device parameters[19] such as turn-on voltage, d.c. current gain, offset voltage, Early voltage, and all the Gummel-Poon model parameters used in SPICE circuit models. A contour map of turn-on voltage of HBT's on a 2-inch wafer is shown in Fig. 3 as an example. Finally, to improve process control and to perform critical process development, we employ design of experiment (DOE) techniques. DOE is crucial, particularly in III-V processing because the sample

fT (GHz) 1

< = 60

I

<=70

%~

< = 80

~

<=90

1

<=100

1

< = 110

1

< = 120

1

< = 130

1

< = 140

1

< = 150

1

< = 160

1

<=170

Fig. 2. Contour maps offT for two different epitaxial structures. (a) Baseline HBT profile with 60 nm base and 700 nm collector. (b) Profile optimized for high fl and current gain with 25 nm base and 250 nm collector thicknesses.

Madjid Hafizi

1594

53-

:

-. • -

.x:

52~s~izi~i~" iilii ~ii::::i:::.:.ii?ili;},~i . . . . . ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

51

rr

"!i::

:::~.~::: :

:!; !!ii

50

49-

~i}~'~-~*~4 ,,,,,,,,

48-

47

I

47

48

I

I

49

50

~ ,

.....

,,,,

I

51

I

52

C Vbe@500 i<=

0.600 <= 0.620 I<= 0.640

ggmtm

- , - - < = 0.610 I<= 0.630 I> 0.640

Fig. 3. Contour map of turn-on voltage, VBE, of HBT's of a 2-inch wafer, measured at collector current density of 500 A cm -2. sizes are often small and experiments are time consuming and expensive. 4. NEXT

GENERATION

IC

TECHNOLOGY

To fully utilize the potential of the compound semiconductor HBT technology in circuit applications, it is essential to scale the transistor to submicron dimensions. HBT peak R F performance generally occurs at current densities of 105 A cm -: or higher. Unless the device dimensions are scaled down, LSI circuits will suffer from high power dissipation, Thermal management problems, performance instability and reliability problems. To achieve proper scaling of bipolar transistors and minimize parasitics, all lateral dimensions need to be scaled down. This requires the use of self-alignment techniques to ensure that the parasitic elements remain low. With the use of stepper projection lithography, we were able to achieve emitter geometries as small as 0.3 pm 2 with great uniformity and yield using this novel processing approach. A schematic cross sectional view of the fully self-aligned fabrication sequence is shown in Fig. 4. The fine emitter geometrics were patterned into a thin layer of photoresist (about 0.3 #m thick) using

a 1 x stepper. The emitter pattern was then transferred into a thin layer of dielectric (about 0.2/~m thick) using SF6/N2 plasma in a reactive ion etch (RIE) system. The nitride pattern (dummy emitter) was used as a mask to etch the Gain/As emitter cap using a CHn/H2/Ar plasma by RIE. Similarly, the base was patterned into a dielectric film (Fig. 4(b)), then emitter, base, and collector were dry etched as shown in Fig. 4(c). Next, PECVD silicon dioxide was deposited and etched in SF6/N2 plasma at low pressure and high bias voltage to leave a uniform sidewall of SiO2 which is approximately 0.2/~m thick at the base of the mesa. After the sidewall formation, a light wet chemical etching was performed to remove a GalnAs thickness of approximately 0.1 #m. This citric-based etch removes the emitter and causes an undercut of the SiO2 sidewall as shown in Fig. 4(d). At the same time, the wet etching removes from the sub-collector and leaves an undercut of the collector sidewall as well. The overhang caused by the undercut of the sidewall facilitates fully self-aligned metalization of emitter, base, and collector contacts in a single evaporation step. The metal on the base and subcollector break at the sidewall overhang and results in a separation of approximately 0.1 #m from the mesa edges. The fully

HBT IC Manufacturability and reliability self-aligned ohmic metal is shown in the SEM image of Fig. 5. In this figure, the two silicon dioxide sidewalls are also visible. Next, the HBT mesa structure was planarized by polyimide and etched back by RIE to expose the emitter tops. After the planarization, via holes were etched into the polyimide to reach the base and collector contacts (Fig. 4(f)). The R F performance of 0.3/~m2-emitter HBT is shown in Fig. 6. We are currently processing a wide range of circuits using this technology including 3- and 4-bit flash ADC's, dividers, amplifiers, and clock/data recovery circuits.

viders[20] to data conversion circuits such as ADC's[3] and digital to analog converters (DAC). As an example, a 3-bit ADC is described briefly. The die photo of the fabricated A D C is shown in Fig. 7. The chip contains 900 transistors with a die size of 2.2 × 2.7 mm and a total power dissipation of 3.5 W. The ADC is based on the classical parallel or flash architecture consisting of 8 comparator cells and a resistor reference ladder, followed by a decoding logic and output drivers. Each comparator cell is made up of two comparators in a master/slave configuration and is preceded by a preamplifier. Transistors with an emitter geometry of 2 × 3 #m 2 were mostly used in this circuit and the design is kept differential throughout for best common-mode and power supply rejection. Measurements on this chip were performed using a membrane probe at a full-scale input range of 600mV p-p. Table 1

5. INTEGRATED CIRCUITS

We have demonstrated a number of different InP-based HBT IC's with complexities of over a 1000 transistors. These IC's range from frequency di-

PECVD S~N4 " - ' ~ ~

GalnAs

Emitter Base

n p+

AllnAs GalnAs

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Fig. 4. Schematic cross sectional view of the fully self-aligned fabrication sequence.

1596

Madjid Hafizi

B .11

1 :~.lil~, 5 ; c I t ~ A t i ~ tic, l

C

Fig. 5. SEM micrograph of the fully self-aligned ohmic metal in the scaled HBT process. summarizes the test results. The Nyquist operation was confirmed up to 8 GHz sampling rate with a signal to noise ratio (SNR) of 16.1 dB. The SNR and the effective number of bits (ENOB) are related as: SNR = 6.02 ENOB + 1.76. The ADC operated at up to 5 GHz with input frequency equal to the sampling rate, while at low frequencies it could be clocked at up to 12.7 GHz with 2.7 effective number of bits. A redesigned version of this chip and a 4 bit version is currently in fabrication using our new scaled process. The new designs incorporated devices with an emitter area of 0.6 am'-, which is nearly a factor of 10 smaller than the original design. We expect this version, with scaled transistors, to operate at conversion rates of up to 20 GSPS. We have also demonstrated a number of monolithic OEIC single and multi-channel receivers. Each channel of such a receiver includes a p-i-n photodiode, a transimpedance amplifier and an

150 . . . . . . . . . .

I

output buffer. Each channel has demonstrated greater than 18 GHz bandwidth with optical input of 1.55 #m[17]. In the area of mixed-mode IC's, we are presently fabricating a channelized receiver consisting of HEMT low-noise amplifier (LNA), HBT down converter, automatic gain-control amplifier (AGC), and ADC function, all monolithically integrated. 6. RELIABILITY Reliability of both GaAs and InP based HBT's was extensively reported in recent years. Table 2

150

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50 J

O fT []

0

Jl

0.1

,

i

,

i

i

,

fmax 0

Ill

t

Collector Current (mA) Fig. 6. RF performance of 0.3 pmZ-emitter HBT fabricated using the fully self-aligned process.

Fig. 7. Die photo of the fabricated 3-bit flash architecture ADC.

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HBT IC Manufacturability and reliability Table 1. Measured performance of the 3-bit ADC Input signal freq.

Sample rate (GHz)

4 GHz 5 GHz < 100 MHz

8 5 12.7

SNR (dB)

ENOB (bits)

16.1 16.2 18.1

2.4 2.4 2.7

0.54 BiasStressat 215 *C Ambient 0.52

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,--,

>

/.~

I

~

•

3-PeriodS.L.

•

6-PeriodS.L.

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o

summarizes the results of HBT lifetests for both discrete devices and circuits. In general, beryllium doped HBT's show a degradation in the d.c. current gain and increase in the device turn-on voltage which is strongly bias dependent[25]. When devices are stored at elevated temperature unbiased, they exhibit no change. This is believed to be caused by diffusion of interstitial Be from the base into the emitter when the activation efficiency of Be drops for doping levels above l019 cm -3. Electron-hole pair recombination can also lead to generation of interstitial Be. Three types of solutions exist for this problem. One is to limit the base Be doping to about 1019cm -3 and operate the transistors at a low current density (generally at or below 104 A cm-2). This is sufficient for most of the wireless applications of the technology which presently require circuits operating below 2.5 GHz. Another solution which was adopted by many in the industry is to use carbon-doped MOCVD material instead. Carbon has higher solubility than Be and occupies As substitutes which is more stable after growth. However, carbon-doped transistors have also exhibited severe degradations in d.c. current gain (increase in the base current). To remedy this, "ledge" passivation for reduction of surface recombination was proposed. In-doping of the base to relieve strain was also suggested. Finally, the third solution for us was the use of a chirped superlattice (which is inherently somewhat strained) at the base-emitter junction. This superlattice (SL) both acts as base--emitter heterojunction grading and is also extremely effective in blocking diffusion of Be into the emitter. The role of the SL in trapping of impurities and nonradiative recombination centers was reported extensively[26-28]. SL's were also used as buffer layers in MESFET's to fetter impurities and defects[29]. Two possible mechanisms were proposed[26] for the impurity trapping mechanism of

0.48

0.46

0.44

i

i

i

i

50

100

150

200

Fig. 8. Effect of number of periods in the B-E junction superlattice on the stability of the VBEwhen the Be-doped HBTs are placed under bias and temperature stress.

SL's. First, trapping at the interfaces caused by different impurity solubility in the two SL materials. Second, a strain induced impurity fettering caused by misfit strain between the SL constituents. In our devices if the superlattice is removed, the field-aided Be diffusion from the base occurs under applied bias and temperature stress. Further, the number of periods in the superlattice are very important. We effectively reduced the periods of the SL by extending the base doping towards the emitter. The instability in the VBE is obvious from Fig. 8 for a 3-period SL. Following the success of our work on discrete device reliability, we have initiated an IC lifetest program to assess the reliability of our InP-based HBT IC's. We started with a divide-by-four, static frequency divider as a representative of many of our digital circuits. The divider consists of two D-type flip-flops, a clock driver, an output buffer, and a bias generator and was designed to operate at around 10 GHz clock frequency. We have developed a low-cost packaging technique which allows us to stress the divider circuits by applying bias to them at elevated temperatures. We can also monitor the power supply voltage, Vee, and the supply current, lee under lifetest. The packaging scheme allows us to perform R F measurement of the dividers at room

Table 2. Reported lifetest data on HBT devices and circuits Technology AllnAs/GalnAs AIGaAs/GaAs AIGaAs/GaAs (Log amplifier) AIGaAs/GaAs AIGaAs/GaAs (Power cell) AIGaAs/GaAs (Strain relaxed base) AIGaAs/GaAs InGaP/GaAs

SSE

4|/10--H

Emitter (#m)

Bias stress Vce(V)/Jc(A/cm2)

Growth technique

Ea (eV)

MTTF@ 125 C(h)

Ref.

2 × 3 2 x 3 3 x 10 Circuit

1/70 3/25 3/6.7 V~ = 5, V~ = - 5 V P4c = 0.9 W 6/9.6 Vc = 10, Ib = 9.9 mA Pin = 24.1 dBm 2/10 2/50 2.5/60 2.5/60

MBE MBE MBE MBE

1.92 1.94 1.77 1.4

1.2 5.7 18 1.1

[12] [12] [21] [24]

MOCVD MOCVD

1.1 0.42

MOCVD

0.48 0.48 0.6 2.0

2.5 x 25 1.2 W Cell 4 x 4 4 x 4 2 x 10 2 x 10

250

Stress Time (hr)

MOCVD MOCVD

x x x ×

107 106 l0 s 107

5 x 106 2020, 1340@ 218, 245 C < q2.8 x 106 < ql.l x 105 ~ 104 > 106@200 C

[14] [23] [15] [15] [22] [22]

Madjid Hafizi

1598

temperature. We then characterize the R F performance of the divider periodically and record such parameters as the output amplitude, rise/fall times, maximum operating frequency, and so forth. The dividers can be placed back for further bias/temperature stress. This work is ongoing.

4. 5. 6. 7.

7. CONCLUSIONS H B T based integrated circuits have a wide range of applications in frequencies from < 1 G H z to > 40 GHz. In the area of wireless communications, several H B T IC products are now in production. There is tremendous potential for HBTs in the area of data conversion ( A D C and D A C ) and related components. In particular, InP-based HBTs with inherently superior performances are well suited for the ultra high speed end of the spectrum such as direct sampling receivers. There is more technology development needed in this area both in terms of advanced processes and scaled technologies and in terms of device and circuit reliability. High data rate optical communication with rates of up to 40 Gbit s -~ is another application for H B T technology. Many circuits have demonstrated the potential of the H B T in this area and the required integration levels are within reach at the present time.

8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21.

Acknowledgements--The MBE growth for this work was done by H. C. Sun and T. Liu of Hughes Research Laboratory. I am thankful to W. Stanchina thank J. Jensen, R. Walden, and K. Elliott for helpful discussions and comments. I would like to acknowledge contributions of A. Schmitz to the manufacturability section. I would like to acknowledge M. Montes, Y. Brown, R. Martinez, A. Arthur, and F. Williams for their assistance.

22. 23. 24. 25. 26.

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1. Walters P., et al., Tech. Digest ofGaAs IC Symp., 1995, pp. 67-70. 2. Neal J. D., HBT technology adds power to CDMA chip set. Technical Article, RF Micro Devices, Greensboro,

27. 28. 29.

NC. 3. Baringer C., et al., Proc. Indium Phosphide and Rel Mat. Conf., 1996, pp. 64--67. Tran L., et al., Tech. Dig. GaAs IC Syrup., 1993, pp. 159-162. Nary K. R. et al., Tech. Dig. GaAs IC Symp., 1995, pp. 303-306. Walden R. H., Tech. Dig. GaAs IC Symp., 1994, pp. 217-219. Matsuoka Y., et al., Tech. Dig. GaAs IC Symp., 1994, pp. 185-188. Otsuji T., et al., Tech Digest o f Mic. Millimeter Wave Mon. Cir. Symp., 1995, pp. 11-14. Walden R. H., et al., Digest L E O S Summer Top. Meet., 1995, pp. 48-49. Chandrasehkar S., et al., IEEE Photonics Tech. Lett., 1991, September, pp. 823-825. Yamahata S., et al., Tech. Dig. GaAs IC Symp., 1995, pp. 163-165. Hafizi M., et al., IEEE Trans Microwave Theory Tech., Dec, 1995, pp. 3048-3054. Yamada F. M., et al., Tech. Dig. GaAs IC Symp., 1994, pp. 271-274. Henderson T., et al., I E D M Tech. Dig., 1994, pp. 187-190. Sugahara H., et al., Tech. Dig. GaAs IC Symp., 1993, 115-118. Hafizi M., Compound Semiconductor 1995, Ins. Phys. Conf. Series. No 145, lOP 1996, pp. 631-636. Stanchina W. E., et al., Tech Diget o f GaAs IC Symp., 1995, pp. 31-34. Hafizi M., et al., 53rd Device Research Conf., June 1995. Hafizi M., Crowell C. R. and Grupen M. E., IEEE Trans. Electron Devices, 1990, 37, pp. 2121-2129. Hafizi M., et al., IEEE Electron Device Lett., 1992, 13, pp. 612-614. Yamada F. M., et al., IEEE M T T - S Digest, 1992, pp. 739-742. Takahashi T., et al., I E D M Tec. Digest., 1994, pp. 191-194. Henderson T. S., et al., Dig. GaAs IC Syrup., 1995, pp. 151-154. Yamada F. M., et al., Dig. GaAs IC Symp., 1994, pp. 271-274. Hafizi M., et al., Tech. Dig. GaAs IC Symp., 1990, pp. 329-332. Petroff P. M., et al., Appl. Phys. Lett., 1982, 44, pp. 217-219. Iwata H., et al., Appl. Phys. Lett., 1989, 54, pp. 2427-2428. Tournie E., et al., J. Appl. Phys., 1991, 70, pp. 7362-7369. Liu W. C. et al., J V S T B. , 1989, 7, pp. 589-592.