- Email: [email protected]
charge (IBIC) through insulating oxides
NIM B Beam Interactions with Materials & Atoms
Nuclear Instruments and Methods in Physics Research B 249 (2006) 204–208 www.elsevier.com/locate/nimb
Heavy ion beam induced current/charge (IBIC) through insulating oxides q Gyorgy Vizkelethy *, David K. Brice, Barney L. Doyle Sandia National Laboratories, P.O. Box 5800, MS 1056, Albuquerque, NM 87185, USA Available online 12 May 2006
Abstract Model experiments were performed on MOS (metal-oxide semiconductor) capacitors to study ion beam induced charge generation in silicon-on-insulator (SOI) devices. Surprisingly large induced charge was found and a lateral non-uniformity of the induced charge was discovered across the top electrode of the capacitor. In this paper we will give a simple model for the charge induction in MOS structures and an explanation of the lateral changes in the amount of induced charge. 2006 Elsevier B.V. All rights reserved.
1. Introduction Traditionally SOI devices were considered more radiation hardened than the ones manufactured by bulk technology. The charge collection volume was assumed to be much smaller in the SOI because it was believed that charge is induced only by the carriers created in the top silicon layer and not by the carriers created below the buried oxide (BOX). In the past the single event upset (SEU) tests seemed to support this assumption. Most recently, new SEU tests on modern SOI static random access memories (SRAMs with BOX thicknesses less than 200 nm) showed unexpectedly high SEU cross-sections [1]. The measured SEU cross-section (8 lm2/bit) was much closer to the combined gate-drain area (6.1 lm2/bit) than to the expected gate-only area (0.6 lm2/bit). SEU imaging performed using a nuclear microprobe [1] proved that the combined drain– gate area is sensitive to SEUs. IBIC measurements showed that the amount of induced charge is much larger than the charge deposited into the top silicon layer above the BOX.
q Sandia is a multi-program laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy’s National Nuclear Security Administration under Contract DEAC04-94AL85000. * Corresponding author. Tel.: +1 505 284 3120; fax: +1 505 844 7775. E-mail address: [email protected] (G. Vizkelethy).
0168-583X/$ - see front matter 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.nimb.2006.03.115
This was a clear indication that the charge induction occurs not only when the carriers move in the top silicon layer but also when they move below the BOX. It was speculated that the enhanced charge induction was due to a conducting channel formed in the BOX along the ion track [1]. To further study the charge induction on SOI devices, IBIC experiments were done on MOS capacitors [2,3]. These experiments showed that the induced charge is close to the sum of the total charge deposited into the top silicon layer and below the BOX and this enhanced charge induction occurs only when the MOS capacitor is in depletion or inversion mode. Further studies combined with TCAD calculations were done recently [4]. Using the well-known Gunn theorem we developed a model [5] to describe the charge induction through insulating oxides and we will give a brief summary in this paper. The detailed study of the MOS capacitors gave some surprising results; namely, the lateral distribution of the induced charge across the top contact was highly non-uniform at low biases while it was quite uniform at higher biases. In this paper we will give a qualitative explanation and present experimental proofs for the model. 2. Experimental Thermal oxide capacitors were manufactured on various substrates (n, p, n+, p+) with thicknesses of 50, 100 and
G. Vizkelethy et al. / Nucl. Instr. and Meth. in Phys. Res. B 249 (2006) 204–208
3. Results
50 -40 V
45 40
Induced charge fraction [%]
200 nm. The polysilicon gate was silicided (Ti) and Al was deposited on the back. The areas of the contacts varied between 0.0012 and 0.11 mm2 and were either square or circular. The IBIC experiments were performed using the Sandia National Laboratories nuclear microprobe. In most experiments 35 MeV Cl ions were focused into a spot about 1 lm2 size and electrostatically scanned along a line or over a square. The typical scan size was around 100 · 100 lm2. The IBIC signal was recorded using Tektronix digital oscilloscopes or a multi-channel analyzer (MCA). For more detailed experimental description see [2].
205
35
-20 V
30 -8V
25 20
-4 V
15 10
0V 5
The IBIC experiments showed that significant charge induction occurs only if the MOS capacitor is in depletion or inversion, i.e. positive top electrode potential for p-type substrate and negative top electrode potential for n-type substrate [2]. The fraction of maximum induced charge for lightly doped (1015 atom/cm3) substrates varied between 20% and 80% depending on the oxide thickness and, as we later discovered, on the position of the ion hit on the capacitor. The amount of induced charge drastically decreased with increasing substrate doping; it became less than 7% for the highly doped (1019 atoms/cm3) ones. Typical bias and oxide thickness dependence of the amount of induced charge is shown in Fig. 1. The induced charge initially increases with increasing bias, then it saturates. Thinner BOX showed larger amount of induced charge than the thicker ones. Fig. 2 [6] shows the induced charge as the function of the distance from the center of the top electrode of the MOS capacitor. The amount of induced charge is the highest at the edge of the electrode, stays constants for about 100 lm, then quickly drops to a level that remains constant to the center of the electrode. Moving away from the edge of the electrodes we found the amount of collected charge 70
Induced charge fraction [%]
60 50
0 0
200
400
600
800
Distance from left edge [μm] Fig. 2. Charge collection efficiency profile for a 200 nm oxide capacitor on lightly doped substrate. The vertical lines mark the edges of the capacitor.
dropping to zero almost exponentially. As the bias increases, the amount of induced charge increases in both the edge and the central regions but the width of the high charge collection edge region (‘‘rabbit ears’’) remains constant. At high enough voltages the difference between the two regions disappears and the charge induction profile becomes flat across the electrode as it was expected. Experiments on MOS capacitors with different BOX thicknesses and different electrode sizes showed that the width of the high charge collection efficiency edge region depends on the thickness of the BOX but not on the electrode size or on the applied bias. Two-dimensional IBIC scans are shown in Fig. 3(a) and (b) at 2 and 40 V. The difference in the amount of induced charge in the edge and central regions indicated an inhomogeneity across the electrode. Secondary ion mass spectroscopy (SIMS) and elastic recoil detection (ERD) measurements were done to determine the concentration distribution of the various elements, mainly to see if there was an inhomogeneous distribution of hydrogen at the oxide–substrate interface. The results of both measurements showed no significant variation of any of the elements or the oxide and silicide layer thicknesses across the electrode.
40
4. Discussion 30 20
According to the Gunn theorem [7], charge is induced when a carrier moves in the electric field generated by the applied bias to the electrodes of a system. More precisely, if a q charge is moving in a system with a number of electrodes, the current induced in the ith electrode is
50 nm oxide 100 nm oxide
10
200 nm oxide 0 0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
Bias voltage [V] Fig. 1. Induced charge fraction as the function of the oxide thickness and applied bias for n-type lightly doped (1015 atom/cm3) substrate.
I i ¼ qv
oE ; oV i
ð1:1Þ
oE where v is the velocity of the charge and oV is the differeni tial of the electric field with respect to the voltage on the ith
206
G. Vizkelethy et al. / Nucl. Instr. and Meth. in Phys. Res. B 249 (2006) 204–208
Fig. 3. IBIC images of a 100 nm oxide capacitor on lightly doped p-type substrate at 2 V (a) and 40 V (b) bias voltages. The thick white line marks the edge of the capacitor.
qi ¼
k=eSi q k=eSi þ xox =eox d
ð1:2Þ
with k ¼ hxi þ Q
ohxi ; oQ
in [5]. The contribution of the charge created in the fieldfree region can be estimated by adding a diffusion term as was shown by Breese [8] R k=eSi ldiff p 1 e ldiff ; ð1:4Þ qi qd k=eSi þ xox =eox Rp where ldiff is the diffusion length of the minority carriers in the substrate, Rp is the range of the incident ion and Rp k as assumed. In our experiments this later assumption was satisfied by Rp 10 lm and k 0.5 lm. Fig. 4 shows the results of the calculations for various oxide thicknesses. The qualitative agreement between Figs. 1 and 4 is quite obvious; both show the same tendencies (in-
70 60 Induced charge fraction [%]
electrode, while the potentials of all the other electrodes are kept constant. An MOS capacitor can be in three different states. In the accumulation regime (positive bias for n-type and negative bias for p-type substrate) the electric field is practically zero in the substrate; therefore, no or very small charge induction occurs. On the other hand, in the inversion or depletion regime, a depletion layer exists below the BOX where the electric field is not zero and changes with the applied bias. The carriers generated by a high energy heavy ion fall into to two categories: carriers created in the above mentioned depletion region and carriers generated below the depletion region in the field-free part of the substrate. The first group will induce current according to (1.1) and the second group will start to diffuse in the field-free region. These carriers will either recombine or reach the depletion region where they will induce current the same way as the carriers that were created in the depletion region. Using Eq. (1.1) and basic electrostatics of the depletion layer in an MOS capacitor it can be shown that the induced charge due to some qd charge created in the depletion region is
50 40 30 20
50 nm oxide
ð1:3Þ
where eSi and eox are the dielectric permittivities of silicon and silicon-dioxide, xox is the BOX thickness, Q is the total space charge per unit area (excluding the minority carriers at the interface in the inversion regime) in the depletion region and hxi is the distance from the oxide–substrate interface averaged over the space charge distribution in the substrate. Detailed derivation of Eq. (1.2) can be found
100 nm oxide 10
200 nm oxide
0 0
-2
-4
Bias voltage [V] Fig. 4. Model calculations for induced charge fraction for capacitors with various oxide thicknesses on lightly doped n-type substrate. Rp = 11 lm and ldiff = 80 lm were assumed in the calculations.
G. Vizkelethy et al. / Nucl. Instr. and Meth. in Phys. Res. B 249 (2006) 204–208
Induced charge fraction [%]
5 hour annealing
50 40
2 hour annealing
30
1 hour annealing
20 10 0 200
400
150
100
50
0 0
50
100
150
200
250
300
Oxide thickness [nm] Fig. 6. The width of the high charge induction region versus oxide thickness. The solid line is a fit to Eq. (1.5).
of the amount of induced charge as the function of the annealing time. The figure clearly shows that the width of the high charge collection efficiency edge region grows with longer annealing times and after five hour annealing all the traps are passivated and the charge induction profile becomes uniform. We can estimate the oxide thickness dependence of the width of the high charge induction region. Assuming that the concentration of the mobile hydrogen is much less than the density of traps and p ffiffiffiffiffiffiffiffiffi D t L (where D is the diffusion constant of hydrogen, t is the annealing time, L is the width of the high charge induction region) it can be shown that L is proportional to the square root of the oxide thickness [9] pffiffiffiffiffiffi L xox ð1:5Þ
5. Summary
as prepared
0
200
Fig. 6 shows the measured L values for different oxide sizes at the original 30 min annealing. The solid line is a square root fit to the data. Further studies are needed to make this model quantitative. The non-zero induced charge when the ions hit outside the electrode is due to carriers laterally diffusing into the depletion region below the electrode. Because of the exponential nature of the diffusion, the amount of the induced charge decreases quickly with the distance from the edge of the electrode.
70 60
250
Rabbit ear width [μm]
duced charge fraction dependence on applied bias and oxide thickness). The amount of induced charge fraction at saturation agrees well with the simulation, although the slopes of the curves are somewhat steeper from the simulation. The reason of this discrepancy is the trapped charge in the oxide and at the oxide–substrate interface which is not taken into account by this model. Based on the above model, the observed non-uniformity of the amount of induced charge across the electrode can be explained only by the difference in k across the electrode. Or simplifying it even more, it means that the depletion region is not uniform under the oxide across the electrode. There is one obvious reason for a non-uniform depletion region: there is non-uniformly distributed trapped charge along the oxide–substrate interface. After carefully reviewing the manufacturing process, we concluded that the forming gas annealing (10% H and 90% N) to passivate the interface traps, which was satisfactory for smaller capacitors, proved inadequate for these larger capacitors. We can model the annealing as follows. The top contact blocks the hydrogen diffusion and the hydrogen is diffusing in the oxide from the side and it passivates all traps; therefore, there is less interface charge in the passivated region than in the unpassivated one. From that it follows that the depletion region is larger at the edges where the traps are passivated than at the center where there are still unpassivated traps. As the bias increases, the edge region goes into inversion (the depletion region reaches its maximum size) sooner than the central region. When the bias reaches the value where the central region goes into inversion, the charge induction profile becomes homogeneous. To prove our model we annealed 50 nm capacitors for 1, 2 and 5 h under the same conditions as the original 30 min annealing was done. Fig. 5 [6] shows the lateral dependence
207
600
800
Distance from the left edge [μm] Fig. 5. Charge collection efficiency profiles for 50 nm oxide capacitor on lightly doped n-type substrate at 1.25 V bias. The capacitors were annealed for 450 C in 10% H + 90% N for 1, 2 and 5 h. The vertical lines mark the edges of the capacitor.
Unexpectedly high SEU rates were found in modern SOI SRAMs with thin insulating oxides. Model experiments on thermal MOS capacitors showed that charge in the top electrode is induced not only by carriers created in the top silicon layer but also by carriers created in the substrate. A model based on the Gunn-theorem was given to explain the charge induction process in MOS structures. A lateral charge collection efficiency inhomogeneity was found on the model capacitors which was explained by
208
G. Vizkelethy et al. / Nucl. Instr. and Meth. in Phys. Res. B 249 (2006) 204–208
the insufficient passivation during the manufacturing process. References [1] P.E. Dodd, M.R. Shaneyfelt, K.M. Horn, D.S. Walsh, G.L. Hash, T.A. Hill, B.L. Draper, J.R. Schwank, F.W. Sexton, P.S. Winokur, IEEE Trans. Nucl. Sci. NS-48 (2001) 1893. [2] G. Vizkelethy, P.E. Dodd, J.R. Schwank, M.R. Shaneyfelt, D.S. Walsh, F.D. McDaniel, B.L. Doyle, Nucl. Instr. and Meth. B 210 (2003) 211.
[3] J.R. Schwank, P.E. Dodd, M.R. Shaneyfelt, G. Vizkelethy, B.L. Draper, T.A. Hill, D.S. Walsh, G.L. Hash, B.L. Doyle, F.D. McDaniel, IEEE Trans. Nucl. Sci. NS-49 (2002) 2937. [4] V. Ferlet-Cavrois, P. Paillet, J.R. Schwank, G. Vizkelethy, M.R. Shaneyfelt, J. Baggio, A. Torres, O. Flament, IEEE Trans. Nucl. Sci. NS-50 (2003) 2208. [5] G.Vizkelethy, D.K. Brice, B.L. Doyle, in press. [6] G. Vizkelethy, B.L. Doyle, D.K. Brice, P.E. Dodd, M.R. Shaneyfelt, J.R. Schwank, Nucl. Instr. and Meth. B 231 (2005) 467. [7] J.B. Gunn, Solid-State Electron 7 (1964) 739. [8] M.B.H. Breese, J. Appl. Phys. 74 (1993) 2789. [9] W.R. Wampler, private communication.
Nuclear Instruments and Methods in Physics Research B 249 (2006) 204–208 www.elsevier.com/locate/nimb
Heavy ion beam induced current/charge (IBIC) through insulating oxides q Gyorgy Vizkelethy *, David K. Brice, Barney L. Doyle Sandia National Laboratories, P.O. Box 5800, MS 1056, Albuquerque, NM 87185, USA Available online 12 May 2006
Abstract Model experiments were performed on MOS (metal-oxide semiconductor) capacitors to study ion beam induced charge generation in silicon-on-insulator (SOI) devices. Surprisingly large induced charge was found and a lateral non-uniformity of the induced charge was discovered across the top electrode of the capacitor. In this paper we will give a simple model for the charge induction in MOS structures and an explanation of the lateral changes in the amount of induced charge. 2006 Elsevier B.V. All rights reserved.
1. Introduction Traditionally SOI devices were considered more radiation hardened than the ones manufactured by bulk technology. The charge collection volume was assumed to be much smaller in the SOI because it was believed that charge is induced only by the carriers created in the top silicon layer and not by the carriers created below the buried oxide (BOX). In the past the single event upset (SEU) tests seemed to support this assumption. Most recently, new SEU tests on modern SOI static random access memories (SRAMs with BOX thicknesses less than 200 nm) showed unexpectedly high SEU cross-sections [1]. The measured SEU cross-section (8 lm2/bit) was much closer to the combined gate-drain area (6.1 lm2/bit) than to the expected gate-only area (0.6 lm2/bit). SEU imaging performed using a nuclear microprobe [1] proved that the combined drain– gate area is sensitive to SEUs. IBIC measurements showed that the amount of induced charge is much larger than the charge deposited into the top silicon layer above the BOX.
q Sandia is a multi-program laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy’s National Nuclear Security Administration under Contract DEAC04-94AL85000. * Corresponding author. Tel.: +1 505 284 3120; fax: +1 505 844 7775. E-mail address: [email protected] (G. Vizkelethy).
0168-583X/$ - see front matter 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.nimb.2006.03.115
This was a clear indication that the charge induction occurs not only when the carriers move in the top silicon layer but also when they move below the BOX. It was speculated that the enhanced charge induction was due to a conducting channel formed in the BOX along the ion track [1]. To further study the charge induction on SOI devices, IBIC experiments were done on MOS capacitors [2,3]. These experiments showed that the induced charge is close to the sum of the total charge deposited into the top silicon layer and below the BOX and this enhanced charge induction occurs only when the MOS capacitor is in depletion or inversion mode. Further studies combined with TCAD calculations were done recently [4]. Using the well-known Gunn theorem we developed a model [5] to describe the charge induction through insulating oxides and we will give a brief summary in this paper. The detailed study of the MOS capacitors gave some surprising results; namely, the lateral distribution of the induced charge across the top contact was highly non-uniform at low biases while it was quite uniform at higher biases. In this paper we will give a qualitative explanation and present experimental proofs for the model. 2. Experimental Thermal oxide capacitors were manufactured on various substrates (n, p, n+, p+) with thicknesses of 50, 100 and
G. Vizkelethy et al. / Nucl. Instr. and Meth. in Phys. Res. B 249 (2006) 204–208
3. Results
50 -40 V
45 40
Induced charge fraction [%]
200 nm. The polysilicon gate was silicided (Ti) and Al was deposited on the back. The areas of the contacts varied between 0.0012 and 0.11 mm2 and were either square or circular. The IBIC experiments were performed using the Sandia National Laboratories nuclear microprobe. In most experiments 35 MeV Cl ions were focused into a spot about 1 lm2 size and electrostatically scanned along a line or over a square. The typical scan size was around 100 · 100 lm2. The IBIC signal was recorded using Tektronix digital oscilloscopes or a multi-channel analyzer (MCA). For more detailed experimental description see [2].
205
35
-20 V
30 -8V
25 20
-4 V
15 10
0V 5
The IBIC experiments showed that significant charge induction occurs only if the MOS capacitor is in depletion or inversion, i.e. positive top electrode potential for p-type substrate and negative top electrode potential for n-type substrate [2]. The fraction of maximum induced charge for lightly doped (1015 atom/cm3) substrates varied between 20% and 80% depending on the oxide thickness and, as we later discovered, on the position of the ion hit on the capacitor. The amount of induced charge drastically decreased with increasing substrate doping; it became less than 7% for the highly doped (1019 atoms/cm3) ones. Typical bias and oxide thickness dependence of the amount of induced charge is shown in Fig. 1. The induced charge initially increases with increasing bias, then it saturates. Thinner BOX showed larger amount of induced charge than the thicker ones. Fig. 2 [6] shows the induced charge as the function of the distance from the center of the top electrode of the MOS capacitor. The amount of induced charge is the highest at the edge of the electrode, stays constants for about 100 lm, then quickly drops to a level that remains constant to the center of the electrode. Moving away from the edge of the electrodes we found the amount of collected charge 70
Induced charge fraction [%]
60 50
0 0
200
400
600
800
Distance from left edge [μm] Fig. 2. Charge collection efficiency profile for a 200 nm oxide capacitor on lightly doped substrate. The vertical lines mark the edges of the capacitor.
dropping to zero almost exponentially. As the bias increases, the amount of induced charge increases in both the edge and the central regions but the width of the high charge collection edge region (‘‘rabbit ears’’) remains constant. At high enough voltages the difference between the two regions disappears and the charge induction profile becomes flat across the electrode as it was expected. Experiments on MOS capacitors with different BOX thicknesses and different electrode sizes showed that the width of the high charge collection efficiency edge region depends on the thickness of the BOX but not on the electrode size or on the applied bias. Two-dimensional IBIC scans are shown in Fig. 3(a) and (b) at 2 and 40 V. The difference in the amount of induced charge in the edge and central regions indicated an inhomogeneity across the electrode. Secondary ion mass spectroscopy (SIMS) and elastic recoil detection (ERD) measurements were done to determine the concentration distribution of the various elements, mainly to see if there was an inhomogeneous distribution of hydrogen at the oxide–substrate interface. The results of both measurements showed no significant variation of any of the elements or the oxide and silicide layer thicknesses across the electrode.
40
4. Discussion 30 20
According to the Gunn theorem [7], charge is induced when a carrier moves in the electric field generated by the applied bias to the electrodes of a system. More precisely, if a q charge is moving in a system with a number of electrodes, the current induced in the ith electrode is
50 nm oxide 100 nm oxide
10
200 nm oxide 0 0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
Bias voltage [V] Fig. 1. Induced charge fraction as the function of the oxide thickness and applied bias for n-type lightly doped (1015 atom/cm3) substrate.
I i ¼ qv
oE ; oV i
ð1:1Þ
oE where v is the velocity of the charge and oV is the differeni tial of the electric field with respect to the voltage on the ith
206
G. Vizkelethy et al. / Nucl. Instr. and Meth. in Phys. Res. B 249 (2006) 204–208
Fig. 3. IBIC images of a 100 nm oxide capacitor on lightly doped p-type substrate at 2 V (a) and 40 V (b) bias voltages. The thick white line marks the edge of the capacitor.
qi ¼
k=eSi q k=eSi þ xox =eox d
ð1:2Þ
with k ¼ hxi þ Q
ohxi ; oQ
in [5]. The contribution of the charge created in the fieldfree region can be estimated by adding a diffusion term as was shown by Breese [8] R k=eSi ldiff p 1 e ldiff ; ð1:4Þ qi qd k=eSi þ xox =eox Rp where ldiff is the diffusion length of the minority carriers in the substrate, Rp is the range of the incident ion and Rp k as assumed. In our experiments this later assumption was satisfied by Rp 10 lm and k 0.5 lm. Fig. 4 shows the results of the calculations for various oxide thicknesses. The qualitative agreement between Figs. 1 and 4 is quite obvious; both show the same tendencies (in-
70 60 Induced charge fraction [%]
electrode, while the potentials of all the other electrodes are kept constant. An MOS capacitor can be in three different states. In the accumulation regime (positive bias for n-type and negative bias for p-type substrate) the electric field is practically zero in the substrate; therefore, no or very small charge induction occurs. On the other hand, in the inversion or depletion regime, a depletion layer exists below the BOX where the electric field is not zero and changes with the applied bias. The carriers generated by a high energy heavy ion fall into to two categories: carriers created in the above mentioned depletion region and carriers generated below the depletion region in the field-free part of the substrate. The first group will induce current according to (1.1) and the second group will start to diffuse in the field-free region. These carriers will either recombine or reach the depletion region where they will induce current the same way as the carriers that were created in the depletion region. Using Eq. (1.1) and basic electrostatics of the depletion layer in an MOS capacitor it can be shown that the induced charge due to some qd charge created in the depletion region is
50 40 30 20
50 nm oxide
ð1:3Þ
where eSi and eox are the dielectric permittivities of silicon and silicon-dioxide, xox is the BOX thickness, Q is the total space charge per unit area (excluding the minority carriers at the interface in the inversion regime) in the depletion region and hxi is the distance from the oxide–substrate interface averaged over the space charge distribution in the substrate. Detailed derivation of Eq. (1.2) can be found
100 nm oxide 10
200 nm oxide
0 0
-2
-4
Bias voltage [V] Fig. 4. Model calculations for induced charge fraction for capacitors with various oxide thicknesses on lightly doped n-type substrate. Rp = 11 lm and ldiff = 80 lm were assumed in the calculations.
G. Vizkelethy et al. / Nucl. Instr. and Meth. in Phys. Res. B 249 (2006) 204–208
Induced charge fraction [%]
5 hour annealing
50 40
2 hour annealing
30
1 hour annealing
20 10 0 200
400
150
100
50
0 0
50
100
150
200
250
300
Oxide thickness [nm] Fig. 6. The width of the high charge induction region versus oxide thickness. The solid line is a fit to Eq. (1.5).
of the amount of induced charge as the function of the annealing time. The figure clearly shows that the width of the high charge collection efficiency edge region grows with longer annealing times and after five hour annealing all the traps are passivated and the charge induction profile becomes uniform. We can estimate the oxide thickness dependence of the width of the high charge induction region. Assuming that the concentration of the mobile hydrogen is much less than the density of traps and p ffiffiffiffiffiffiffiffiffi D t L (where D is the diffusion constant of hydrogen, t is the annealing time, L is the width of the high charge induction region) it can be shown that L is proportional to the square root of the oxide thickness [9] pffiffiffiffiffiffi L xox ð1:5Þ
5. Summary
as prepared
0
200
Fig. 6 shows the measured L values for different oxide sizes at the original 30 min annealing. The solid line is a square root fit to the data. Further studies are needed to make this model quantitative. The non-zero induced charge when the ions hit outside the electrode is due to carriers laterally diffusing into the depletion region below the electrode. Because of the exponential nature of the diffusion, the amount of the induced charge decreases quickly with the distance from the edge of the electrode.
70 60
250
Rabbit ear width [μm]
duced charge fraction dependence on applied bias and oxide thickness). The amount of induced charge fraction at saturation agrees well with the simulation, although the slopes of the curves are somewhat steeper from the simulation. The reason of this discrepancy is the trapped charge in the oxide and at the oxide–substrate interface which is not taken into account by this model. Based on the above model, the observed non-uniformity of the amount of induced charge across the electrode can be explained only by the difference in k across the electrode. Or simplifying it even more, it means that the depletion region is not uniform under the oxide across the electrode. There is one obvious reason for a non-uniform depletion region: there is non-uniformly distributed trapped charge along the oxide–substrate interface. After carefully reviewing the manufacturing process, we concluded that the forming gas annealing (10% H and 90% N) to passivate the interface traps, which was satisfactory for smaller capacitors, proved inadequate for these larger capacitors. We can model the annealing as follows. The top contact blocks the hydrogen diffusion and the hydrogen is diffusing in the oxide from the side and it passivates all traps; therefore, there is less interface charge in the passivated region than in the unpassivated one. From that it follows that the depletion region is larger at the edges where the traps are passivated than at the center where there are still unpassivated traps. As the bias increases, the edge region goes into inversion (the depletion region reaches its maximum size) sooner than the central region. When the bias reaches the value where the central region goes into inversion, the charge induction profile becomes homogeneous. To prove our model we annealed 50 nm capacitors for 1, 2 and 5 h under the same conditions as the original 30 min annealing was done. Fig. 5 [6] shows the lateral dependence
207
600
800
Distance from the left edge [μm] Fig. 5. Charge collection efficiency profiles for 50 nm oxide capacitor on lightly doped n-type substrate at 1.25 V bias. The capacitors were annealed for 450 C in 10% H + 90% N for 1, 2 and 5 h. The vertical lines mark the edges of the capacitor.
Unexpectedly high SEU rates were found in modern SOI SRAMs with thin insulating oxides. Model experiments on thermal MOS capacitors showed that charge in the top electrode is induced not only by carriers created in the top silicon layer but also by carriers created in the substrate. A model based on the Gunn-theorem was given to explain the charge induction process in MOS structures. A lateral charge collection efficiency inhomogeneity was found on the model capacitors which was explained by
208
G. Vizkelethy et al. / Nucl. Instr. and Meth. in Phys. Res. B 249 (2006) 204–208
the insufficient passivation during the manufacturing process. References [1] P.E. Dodd, M.R. Shaneyfelt, K.M. Horn, D.S. Walsh, G.L. Hash, T.A. Hill, B.L. Draper, J.R. Schwank, F.W. Sexton, P.S. Winokur, IEEE Trans. Nucl. Sci. NS-48 (2001) 1893. [2] G. Vizkelethy, P.E. Dodd, J.R. Schwank, M.R. Shaneyfelt, D.S. Walsh, F.D. McDaniel, B.L. Doyle, Nucl. Instr. and Meth. B 210 (2003) 211.
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