Heteroepitaxial growth of InP on Si substrates

Journal of Crystal Growth 99 (1990) 365—370 North-Holland

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HETEROEPITAXIAL GROWTh OF InP ON Si SUBSTRATES Mitsuru SUGO and Masafumi YAMAGUCHI

*

NTT Opto-electronics Laboratories, 3-1 Morinosato, Wakamiya, Kanagawa 2 43-01, Japan

and M.M. AL-JASSIM Solar Energy Research Institute, 1617 Cole Blvd. Golden, Colorado 80401, USA

Heteroepitaxy of a highly mismatch system (— 8%), lnP/Si has been studied using low pressure organometallic vapor phase epitaxy (OMYPE). Buffer layer effects on residual stress and defect density in InP/Si have been clarified. Using a 1 ~im thick GaAs 2 compared to ~- 4 x 10~dyn/cm2 for InP buffer layer, residual stress in the LisP layer has been reduced to as low as 2 x 108 dyn/cm directly grown on Si and — 6 X io~dyn/cm2 for In? on Si with a 1 ~sm thick GaP buffer layer. Moreover, the GaAs buffer layer has also been confirmed to be effective for improving InP/Si quality by evaluation of etch-it density, X-ray diffraction measurement and observation of cross-sectional transmission electron microscopy. For an InP/GaAs/Si structure, laP growth temperature dependence on surface morphology and etch-pit density is also shown. High quality InP films with etch-pit density of 8 X 106 cm2 has been obtained on Si substrates by using thermal cycle growth and an InP/GaAs/Si structure.

1. Introduction Recently there has been strong interest in the heteroepitaxial growth of 111—V compound semiconductors on Si, because a Ill—V/Si structure is promising in a large area of low cost and high quality optical and electronic devices such as solar cells [1] or light emitting devices [2,3], and monolithic integration of Ill—V optical devices with Si integrated circuits. However, there are two serious problems concerning the growth of Ill—V semiconductors on Si substrates: one is high density dislocation generation and the other is residual stress in grown films due to the large lattice mismatch and the thermal expansion coefficient difference between Ill—V films and Si substrates. The InP heteroepitaxial growth on Si is more difficult than GaAs and GaP on Si because of the larger lattice mismatch (8.1%). The authors have reported the successful growth of InP directly on

*

Present address: NTT Opto-electronics laboratories, Tokai, Ibaraki 319-11, Japan.

0022-0248/90/$03.50 © Elsevier Science Publishers B.V. (North-Holland)

Si [4,5] and that residual strain in an InP/Si system is lower than those in GaAs/Si and GaP/Si systems [6]. However, it is necessary to reduce residual strain in InP/Si and to improve InP/Si quality further in order to obtain high performance InP/Si devices. This paper describes GaAs or GaP buffer layer effects on residual stress and InP crystalline ciuality for the InP/Si system grown using OMVPE. A GaAs buffer layer is found to be effective to reduce the residual stress and dislocation density in InP/Si. For an InP/GaAs/Si structure, the dependence of growth temperature on InP layer quality and the effectiveness of thermal cycling on growth are also described.

2. Exjerimental The OMVPE apparatus used had a horizontal quartz reactor. The pressure in the reactor was kept at about 70 Torr. Triethylgallium (TEG) and trimethylindium (TMI) were used as the Ga and

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Heteroepitaxial growth of laP on Si substrates

In sources, respectively. PH3 and AsH3 were used as the P and As sources, respectively. The Si(100) substrates were degreased and etched just before loading into the reactor. The etching procedure took several repetitions of oxidation by dipping into a H2S04 + H202 solution and oxide removal by dipping into a HF solution. To remove native oxide from the Si surface, the substrates were preheated to 900—1000°Cin a flow of H2 for 10 mm. These substrate pretreatments are essential to suppress antiphase domain formation in grown films [7]. The lnP layers grown directly on Si, GaAs and GaP buffer layers were grown using the two-step growth method. Growth temperature of the first layer is 350, 400 and 450 °Cfor InP, GaAs and GaP, respectively. Growth temperature of the second layer is 600, 700 and 750°C for InP, GaAs and GaP, respectively. On the GaAs or GaP buffer layers, InP was grown at growth temperature of 580~7100C. For all film growths, [V]/[III] ratio > 50 is used. Strain in grown films was estimated from the lattice constant by X-ray diffraction, and stress was calculated from these strain values. The crystalline quality of the heteroepitaxial material was investigated using double crystal X-ray diffraction and by evaluating the etch-pit density (EPD) with an H3 P04 + HBr solution. Cross-sectional transmission electron microscopy (TEM) was also used to reveal the effects of the buffer layer.

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LAYER THICKNESS (pm) Fig. 1. Residual stress in laP films with laP/Si, InP/GaAs/Si and InP/GaP/Si structures as a function of In? layer thickness, where the thicknesses of the Si substrates and the buffer layer are 500 and 1 tim, respectively. Data for GaAs/Si and GaP/Si are also included for comparison [6).

introduced. In this section, we show the effects of these buffer layers on InP crystalline quality and the residual stress in the InP film. Three types of structure, InP/Si, InP/GaAs/Si and lnP/GaP/Si, were fabricated and compared. For the first InP layer grown directly onto Si, a high [VJ/[III] ratio > 300 is essential for obtaining a continuous and single crystalline film [5]. On the GaAs and GaP buffer layers on Si substrates, on the other hand, an InP mirror surface was obtained even at a relatively low [V]/[III] ratio of 50.

3. Results and discussion 3.1.

Effects of GaAs or GaP buffer layers

In the two-step growth of Ill—V semiconductors on Si substrates, control of the crystallinity and surface morphology of the first layer is very important to obtain high-quality films. For InP grown directly onto Si, the first InP layer growth is one of the most difficult processes. This is because of the large lattice mismatch (— 8.1%) and the low decomposition PH3 at low growth temperature ofratetheof first InPthe layer (350—400°C)[5]. In order to improve the InP/Si quality further, a GaP or GaAs buffer layer was

First we show the buffer layer effects on the residual stress in InP on Si substrates. Fig. 1 shows residual stress in InP with various structures as a function of InP layer thickness, where the thickness of the Si substrates and the buffer layer is 500 pm and 1 ~tm, respectively. Data for GaAs/Si and GaP/Si are also included for comparison [6]. Tensile stress was observed for all InP structures. Residual stress for InP/Si is lower than that for GaAs/Si and GaP/Si. Using a GaAs buffer layer, the residual stress in InP is found to 2. be further strain reducedinto the as lowGaAs as 2>
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X-ray diffraction of the GaAs buffer layer [6] This effect of reduction of the residual stress is thought to be attributed to compensation of the tensile strain thermally induced by the GaAs/Si interface with compressive strain thermally induced by the InP/GaAs interface [8]. For the GaP buffer layer, the same effect on residual stress reduction as that achieved with the GaAs buffer layer is expected from considerations of the thermal expansion coefficient of GaP. The experimental result however, indicated that stress 2) in the InP layer of the (— 6 x 108 dyn/cm InP/GaP/Si structure is somewhat higher than that (— 4 X i08 dyn/cm2) in the InP layer grown directly onto Si. A large lattice mismatch between InP and GaP should prevent the compressive strain at the InP/GaP interface from being thermally induced during the cooling process from the growth temperature to room temperature [6]. Buffer layer i~hicknessdependence of residual stress has been described in reference [8]. Next, the buffer layer effects on InP crystalline quality are shown. It is evident that the crystalline quality of an InP layer is dependent on that of the buffer layer. Fig. 2 shows the full width at half maximum (FWHM) of an X-ray rocking curve for InP layers as a function of FWHM for buffer layers, where the thickness of the InP layer was fixed at 3 ~sm and the growth temperature of the InP layer was fixed at 600°C. The FWHM of buffer layers could be changed with their thick-

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ness or annealing conditions. For a GaP buffer layer, the FWHM of — 700” for an InP layer with a buffer layer of FWHM <200” is somewhat lower than that of an InP layer grown directly on Si (— 850”), and the FWHM for an InP layer increased abruptly with increasing FWHM of the buffer layer for an FWHM of a buffer layer > 200”. For a GaAs buffer layer, on the other hand, the FWHM of 500” for an InP layer is lower than that of InP grown directly onto Si and InP grown onto a GaP buffer layer. Moreover, the GaAs buffer layer has an effect on the improvement of the InP layer even when the FWHM of the GaAs buffer layer is higher than 1000” when —

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the thickness of the GaAs buffer layer is — 0.1 ~tm. A GaP buffer layer, on the other hand, has no effect on the improvement of the InP layer when the FWHM is higher than 400” when the thickness of the GaP buffer layer is ~ 0.4 ~tm. The EPD (— 3 X iO~cm2) in the InP/GaAs/Si was also found to be lower than the EPD (— 6 X iO~ cm 2) in the InP/GaP/Si and the EPD (— 10 x 107cm2) in the InP/Si structure, where the InP and buffer layer thicknesses were 3 and I ~tm, respectively. The buffer layer effect on the improvement of the InP crystalline quality should be attributed to the relaxation of the large lattice mismatch between InP and Si. A GaAs buffer layer whose lattice constant is mid-way between InP and Si is found to have a larger effect than that of a GaP buffer layer whose lattice constant is close to Si. The cross-sectional TEM photographs in fig. 3 reveal the excellent effect of the GaAs buffer layer upon defect density. High density of threading dislocations from the InP/Si interface, whose mismatch is 8%, are shown in fig. 3a. Stacking faults were also observed in InP/Si. Using a GaAs buffer layer, the InP/Si mismatch is divided into — 4% for the InP/GaAs interface and — 4% for the GaAs/Si interface. The density of the threading dislocations in the InP layer can be reduced, as shown in fig. 3b.

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3.2. Effects of growth conditions on the lnP/ GaAs / Si structure As described in section 3.1, using a GaAs buffer layer, the reduction of the residual stress and the improvement of the crystalline quality for an InP layer have been achieved. To improve the InP quality further, the growth conditions for the InP of the InP/GaAs/Si structure have been varied in an attempt at optimization. In the two-step growth of InP/Si, the [V]/[IlIJ ratio for the first InP layer growth has been reported to dominate the quality of the second InP layer [5]. In the growth of InP on GaAs/Si, the [V]/[III] ratio dependence on surface morphology, residual stress and EPD was not observed over a [V]/[IIIJ ratio ranging from 50 to 200. In this study, the [V]/[III] ratio was fixed at 140.

Fig. 4. 7~dependence on surface morphology for InP with the InP/GaAs/Si structure. Two types of Si substrates, Si nominally just on the (100) [(a), (c), (e)] and Si cut w h a 4° tilt from the (100) toward [0111 f(b), (d), (fl1~were used. The thicknesses of the GaAs buffer layer and lnP layer are 0.1 and 3 tim, respectively. Values of 7~(in °C): (a), (b) 600; (c), (d) 680; (e). (0 710. The marker indicates 10 ism.

Growth temperature 7~for the InP layer, on the other hand, has obvious effects on the surface morphology and crystalline quality of the InP layer. Fig. 4 shows the 7~dependence on the surface morphology on GaAs/Si. Two types of Si substrates were used, i.e., Si nominally cut as (100) (figs. 4a, 4c and 4e) and Si cut with a 4° tilt from (100) toward [0111 (figs. 4b, 4d and 4f). 0.1 urn thick GaAs buffer layers were grown under the same growth conditions. The 3 usm thick InP layers were grown under the same growth conditions except that 7~was varied. No obvious buffer layer thickness dependence on surface morphology was observed. InP surfaces on Si cut with a 4° tilt from (100) toward [0111 exhibit a finescale roughness compared with those on Si nominally cut on the (100). For InP homoepitaxial

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InP again. This procedure was repeated 4 times. Thermal growth cycle induces a slight surface degradation for the present InP/GaAs/Si system but improves the InP crystalline quality. By ther2 and FWHM 200” obmal during growth, InP films withwere an EPD of 8 cycling X 106 cm tamed, where the InP and GaAs buffer layer —

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growth, it has been reported that, with increasing the surface morphology becomes better in the temperature region 550 < T~< 650°C [9]. For InP heteroepitaxial growth on GaAs/Si the surface morphology becomes rough with increasing 7 in the temperature region 580 < T~<710°C. The dependence of for the InP layer on the EPD for InP of the InP/GaAs/Si structure is shown in fig. 5. Growth conditions are the same for the lnP/GaAs/Si structure in fig. 4. The EPD decreases with increasing T~for <700 °Cand increases with increasing 1~for 7~>700°C. The EPD has a minimum value of 3 )< i0~crn2 at — 700°C. From the above results for the 7~dependence of surface morphology and EPD, it is difficult to choose a in order to produce InP films with a low EPD and smooth surface. Increasing T~results in a decrease in the EPD but increasing surface roughness. To resolve this problem, thermal cycling during growth was performed. This method has been shown to be effective for improving GaAs/Si quality without surface degradation [10]. The thermal growth cycle was performed as follows: After InP growth at 600°C, the sample was cooled to room temperature and annealed at 750°Cfor 15 mm; then cooled to 600°Cto grow —

We have studied OMVPE growth of InP on Si substrates. Using a GaAs buffer layer, residual stress in the InP layer was reduced to as low as 2 x 108 dyn/cm2 compared with 4 x 108 dyn/cm2 for InP directly grown onto Si and 6 X 108 dyn/cm2 for InP onto Si with a GaP buffer layer, where the InP and buffer layer thicknesses are 3 urn and 1 urn, respectively. This effect on the reduction of the residual stress was thought to be attributed to compensation of the tensile strain thermally induced by the GaAs/Si interface with compressive strain thermally induced by the InP/GaAs interface. Moreover, the GaAs buffer layer was found to be more effective than the GaP buffer layer in improving InP/Si quality. The 1 dependence on the surface morphology and EPD for the InP/GaAs/Si structure have also been studied. In the temperature region 580
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Acknowledgements The authors wish to express their sincere thanks to T. Ikegami of NIT Laboratories for his continuous encouragement in the course of this work. They also wish to thank H. Mori, Y. Itoh, S.

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Kondo and M. Tachikawa of NIT Laboratories, and Dr. A. Yamamoto of Fukui University, for useful discussions.

References [1] Y. Itoh, T. Nishioka, A. Yamamoto and M. Yamaguchi, Appl. Phys. Letters 52 (1988) 1617. [2] J.P. van der Ziel, R.D. Dupuos, R.A. Logan, R.M. Mikulyak, C.J. Pinzone and A. Savage, AppI. Phys. Letters 50 (1987) 454 [3] M. Razaghi, M. Defour, R. Bloudeau, F. Omnes, ~ Maurel, 0. Acher, F. Brillouet, J.C.C. Fan and J. Salerno, Appi. Phys. Letters 53 (1988) 2389.

Si substrates

[41A.

Yamamoto, N. Uchida and M. Yarnaguchi, Optoelectronics — Devices and Technologies 1 (1986) 41.

[5] A. Yarnamoto, N. Uchida and M. Yamaguchi, J. Crystal Growth 96 (1989) 369. [6] M. Sugo, N. Uchida, A. Yamamoto, T. Nisbioka and M. Yamaguchi, J. AppI. Phys. 65 (1989) 591.

[7] M. Sugo, A. Yamamoto and M. Yamaguchi, J. Crystal Growth 88 (1988) 229. [81 M. Sugo and M. Yamaguchi, AppI. Phys. Letters 54 (1989) 1754. [9] K. Uwai, N. Susa, 0. Mikami and T. Fukui, Japan. J. AppI. Phys. 23 (1984) L121. [101 M. Yamaguchi, A. Yamamoto, M. Tachikawa, Y. Itoh and M. Sugo, Appi. Phys. Letters 53 (1988) 2293.

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