- Email: [email protected]
Hierarchical digital systems modeling utilizing hardware description languages for computer engineering education
Com,wftm Elecr. Engng Vol. 2 I, No. 5, pp. 3 I l-320, I995
Pergamon
004s7906(95)ooo16-x
Copyright 0 Printed in Great
1995 Elsevier Science Ltd
Britain. All rights reserved 0045-7906/95 $9.50+ 0.09
HIERARCHICAL DIGITAL SYSTEMS MODELING UTILIZING HARDWARE DESCRIPTION LANGUAGES FOR COMPUTER ENGINEERING EDUCATION DAVID JEFF JACKSON Department of Electrical Engineering, P.O. Box 870286, The University of Alabama, Tuscaloosa, AL 35487. U.S.A. (Received
6 June 1995)
Abstract-This paper describes a hierarchical modeling approach and teaching methodology for digital microcomputer system modeling including abstract event modeling, mixed-mode event and timing-based, and gate level modeling. A structured instructional approach to fundamentals of computer design and simulation is given based on the Verilog hardware description language (HDL). Example models are given for common digital system components which illustrate the hierarchical learning model presented. Example simulation methods, various simulation hierarchies, and graphical simulation output are presented for the Verilog models discussed. Aspects of the simulation hierarchy are given with respect to system complexity, and simulation complexity for implementation and testing. Finally, educational aspects and merits, with emphasis on student perception and evaluation, of this language as a design tool are presented. Key words: Digital system modeling, hardware description languages.
1. INTRODUCTION Computer system modeling via a hardware description language (HDL), in a top-down hierarchical fashion, presents the computer architect/educator with a design methodology which effectively addresses several critical issues. These issues include an appropriate consideration of design complexity, design documentation, and cost effective test and debug procedures. Traditional schematic design procedures for large scale systems are inadequate when these issues are fully and properly considered. Additionally, pedagogical considerations for teaching digital microcomputer design are simplified with the incorporation of HDL-based design. Other useful characteristics of HDL design include complete design specification, early design stage simulation capabilities, and the capability of implementation via logic synthesis [l]. Introductions to HDL-based design methodology are given by Sternheim in Ref. [2] and Micheli in Ref. [3]. Modeling computer systems is a process which is well suited to a hierarchical design methodology. Generally, most computer architecture designs proceed in a top-down fashion. The major levels of this hierarchy include instruction set architecture (ISA) design, register transfer language (RTL) design, gate-level design, and ultimately switch and transistor level design. An HDL design methodology may be incorporated into any of these steps and can thus be justified as an effective tool for hierarchical digital system design. The use of an HDL simplifies the design process by allowing a smooth transition, in either direction, between each of the design stages. For example, an ISA design may be completely specified and tested solely as a behavioral simulation. The corresponding RTL description may be modeled as an event-only simulation or a mixed-mode event-and-gate level simulation. Finally, the gate-level design may be derived from the RTL specification and may consist of a gate and switch-level description. Many modeling considerations may be made involving the complexity of the simulation process at each stage in the hierarchy. Generally, the high level stages of the hierarchy are intended to verify the correctness of the ISA or RTL model. As such, the model complexity is simple and general to allow for rapid prototyping of the design. Figure 1 illustrates a possible description/simulation hierarchy and the corresponding level of computer hierarchy which is typically specified by the description. 311
David Jeff Jackson
312
Architecture Description Hierarchy
Modeling Hierarchy
event specification
Instruction Set Architecture
event ant” specwarlon
Register Transfer Language Specification
L-r-J \rt/,
I
I
I
Fig. 1. Modeling
2. A HIERARCHICAL
hierarchy and corresponding
J
computer
description
EDUCATION MODEL: DESIGN
HDL
hierarchy
BASED
DIGITAL
An introductory computer engineering course, for electrical engineering and computer science students, can provide an excellent environment for incorporating HDL-based design at the register transfer level or gate level in the modeling hierarchy. For this course, a prerequisite knowledge of high level language (typically “C”) programming, digital logic, assembly language programming, and general microcomputer hardware should be assumed. After introduction of basic computer architecture fundamentals and nomenclature associated with register transfer languages, a coverage of basic Verilog semantics [8,9] allows the student to design and simulate models, using the Cadence Verilog HDL simulator, of typical digital system components including multiplexers, decoders, and various combinational and sequential networks. Concurrently, a more detailed coverage of Verilog semantics supporting gate-level simulations may be introduced to allow the student to progress downward within the modeling hierarchy. Proceeding downward through the hierarchy allows the 4 weeks
1 week
2 weeks
1 week
2 weeks ,-
Digital Computer s ‘g Fundamentals 2 5i Register C Transfer Language
Verilog Introdnu$ion Procedural Semantics
Behavioral Semantics and Verilog Examples
Gate Level Semantics and Verilog Examples
HDL description of 5 decoders, muftipfexers and common digital ---w E components .% I Project 6 Description
IFig. 2. A typical
Behavioral and Gate Level CPU Descriptions
Gate Level Design Problems
Gate Level Adder Designs Project )Completior *I
6 weeks HDL
learning
and design process
pipeline.
Hierarchical
digital systems modeling
313
student to build successively more complex models and obtain a more complete understanding and appreciation for the design process and the relationships between lower-level gate-level circuits and their corresponding “abstract” modules. Proper emphasis on establishing a modular design approach for HDL-based descriptions of digital components is a significant aspect of the design process. If the student utilizes modular design techniques, subsequent assignments/projects may properly build on previous designs by allowing the student to use previously constructed HDL modules to create more complex designs. For example, a student’s initial assignments may be to build and test HDL descriptions of decoders, multiplexers and other common digital components. Subsequent assignments may then make use of the previously constructed modules as building blocks. A pipelined learning process may be developed, as shown in Fig. 2, to allow the student to completely design and simulate major components of a central processing unit (CPU) within a single semester course. The pipelined learning process may be extended by allowing the student to explore additional CPU design possibilities including microprogrammed vs hardwired design methods, stack oriented machines, and various ALU configurations in a second project. Example behavioral and gate level descriptions given to students are shown in Fig. 3. Additionally, students construct similar descriptions as beginning exercises. As shown, each of these descriptions have the same input/ output interface so that the same input stimulus test file may be used for both the behavioral and gate level descriptions. Examples of this nature reinforce the desirability of a modular design approach throughout the design hierarchy. A gate level ALU description is given as an example of extending the modular approach throughout the design. The design hierarchy is shown in Fig. 4. Each block in the hierarchy consists of a single Verilog module which contains one or more instances of modules in the immediately lower level of the hierarchy. For example, a 16-bit carry skip adder [4] would consist of two 4-bit ripple carry adder (RCA) blocks, two 4-bit RCA blocks with p-term generation circuitry, denoted RCA-P, to allow the carry to effectively “skip” these intermediate blocks, and //This “always&se” construct models //an ideal 2x4 decoder with the output N signals changing immediately upon // any input change. module decode2x4(out,in); input [0: 1] in: output [0:3] out; always 8 in begin case (in) 0: ouk’b0001;
1:out=‘bOOl
0;
2: out=‘bOlOO; 3: ouk’bl 000; endcase end endmodule
//This module models an ideal 2x4 decoder // at the gate level and consists of 2 inverters // and four AND gates. module deccdeZx4(out,in); input [l:O] in; output [3:0] out; //define wire inverter outputs for inputs to AND gates. wire u010,u020; not uO1 (uOlo.in[O]); not ~02 (uMo,in[l]); and and and and
~04 (out[O]. ~01o, ~020); ~05 (out[l].in[O]. ~020); ~06 (out[2]. uOlo,in[l]); ~07 (out[3].in[O],in[i]);
endmodule
Fig. 3. Behavioral and gate level descriptions of a 2 x 4 decoder.
David
314
Jeff Jackson
ALU Module
Carry Skip Adder Module
Ripple Carry Adder Module
Logic Unit Module
2X1
MUX
Ripple Carry Adder Module with P-Terms
Carry Skip Gates
Fig. 4. Hierarchical
design structure
Logic Unit Bit
of a 16-bit ALU.
additional carry skip gates. Circuit diagram and Verilog details for this particular adder are given in Fig. 8. The Verilog descriptions for other example modules are given in Figs 5-7 which include logic diagrams for the components being simulated. Through the provided examples, students are introduced to various aspects of digital system design including procedures for developing modular designs, design verification using suitable test module mux2xl (out,inO.rnl ,s); output out; input inO.inl; input s; wire sn; wire [l:O] 1;
’ 4
or #(lo)
(t[l].inl,
I
I
(t[O],inO,sn):
and #(lo)
in1
I
j
Mul$!axer
not #(IO) (sns); and #(lo)
in0
I
I
s);
out
(out,t[O].t[l]);
endmodule
module mux4xl(out,in.s); output out; input [3:0] in; input (l:O] s; wire [l:O] sn; wire [3:0] t; not #(lo)
EE .E .c
5i.K E z
(sn[O].s[O]);
not #(IO) (sn[l],s[l]);
s[l:0]
and #(IO) (t[O].in[O],sn[O],sn[l]); and #(lo)
(t[l],in[l],
and #(lo)
(t[Z],in[2],sn[O],
and #(lo)
W%in[sl.sIO1. ~411);
4x1 Multiplexer
s[O].sn[l]); s[l]);
‘1’_” out
or #(lo) ~out,t[ol.tlll.t[2l,t[31); endmodule
Fig. 5. Gate level multiplexer
descriptions.
Hierarchical digital systems modeling
315
vectors, and common problems encountered in digital design including propagation considerations and race conditions that may exist in combinational logic circuits. 3. EDUCATIONAL
EXPERIENCES
WITH
VERILOG
delay
HDL
For an introductory course in computer engineering, students are required to perform multiple Verilog-based laboratory exercises and submit two large-scale Verilog designs: a hardwired microprocessor and a microprogrammed microprocessor. The first two laboratories serve to introduce the students to the two major capabilities that Verilog offers the digital designer-gate level simulations and behavioral level simulations. These labs allow the student to become accustomed to the tools without being overwhelmed by the projects themselves. As the students are accustomed to design using discrete IC components, the first lab consists of two basic designs requiring the use of flip-flops and logic gates. In this manner, the student can take a logic diagram, which used to be the end result of their work, and extend that to involve testing the design’s validity. The first circuit to be simulated is a 4-bit comparator. As a requirement for the design, the student must break the design into two modules consisting of the test module and the comparator module. This is the first attempt at directing the student towards a hierarchical design flow. If the student becomes acclimated to the hierarchical design process, they discover significant design time savings which become critical in subsequent laboratory exercises. The second design is a four-bit shift register. This design serves to introduce the student to the use of constructs capable of storing information. The second lab introduces the student to the ease of simulating circuits using Verilog’s behavioral simulation constructs. This is less familiar to the student, but it’s similarity to the high level languages C and Pascal help overcome their discomfort. The first circuit in this lab is an 8-bit comparator capable of generating “less than”, “greater than” and “equal to” outputs. This is a trivial program, so we introduce one of Verilog’s graphical tools at this time-the waves display. The waves display allows the designer to see how several specified signals vary with time; therefore, //This module is derived from the full adder definition and includes // additional logic for computing A+B.A-B,A+B+l ,A+1 ,A-1, and A based //on the control inputs s[O] and s[l]. The truth table is given as follows: II tin // s[l] s[O] tin output I/ __-___ __-I__-----_--II0 00 A II 0 0 1 A+1 Full _ II 0 1 0 A+B Adder II 0 I 1 A+B+l all 1 0 0 A+0 II 1 0 1 A+B’+l (A-B) II 1 1 0 A-l Ill 11 A II I/ The maximum delay through this //module is 60 simulation time steps. // P generation circuitry is included in this model //to allow construction of carry skip adders. II module adder_bit_p(sum,cout,p,a,b,cin.s); input a,b,cin; input [l :0] s; Full Adder ,________________________-outout sumc0ut.p: 1 wire wl .w2\w3; , wire bl,b2,b3; : b: wire bn; I not #(lo) (bnb); and #(lo) (bl, b,s[O]); and #(lo) (b2,bn,s[l]); or #(lo) (b3,bl,b2); xor #(30) (sum,a,b3,cin); \ and i(ld) (wl ,a,b3); Full Adder and #(lo) (w2,a.cin); , Description and #(lo) (wW3,cin); or #(lo) (cout,wl,w2.w3); I or #(lo) (p,a.b3); Fig. 6. Single bit full adder/subtracter
sum
with p-term generation circuitry.
David
316
Jeff Jackson
// Verilog model for a single bit I/ of the logic unit. // //The maximum delay through this module I/ is 40 simulation time steps (including /I 30 simulation time step delays through //the multiplexer module). II ‘include “mux4xl .v’ module lub(out.a,b,s); output out; input a.b; Input [I :0] 5; wire [3:0] mux_in; mux4xl lub_mux (out,mux_rn,s); and #(lo) (mux_rn[O],a,b); or #(lo) (mux_in[l],a.b); xor #(IO) (mux_in[Z],a,b), not #(lo) (mux_in]3].a); endmodule
a+
mux_in[3]
1
I Frg. 7 A smgle bit of the logic
unit.
as part of the assignment the student has to prove the design works by displaying the timing waveforms. The waves display will be used as a major tool in demonstrating and debugging the lab designs so its use is encouraged early on. In the second part of the lab the students add to the basic design, allowing for a bidirectional bus and an internal register in which to load values for comparison. This design change encourages the use of tri-state buffers which are gate-level constructs, therefore alerting the students to the possibility of mixed simulations. As the students are now familiar with the tools and have had some complex design experience, we begin to focus their learning on the aspects of digital design that will aid them in their final projects (the microprocessor designs). Since an arithmetic logic unit will be a critical part of their design, we introduce an g-bit ALU design. The capabilities that the ALU must have are addition, subtraction, increment, decrement, bitwise AND, bitwise OR, bitwise XOR, and one’s complement. To help the student, we encourage the use of a hierarchical design. Since this is strictly a logic based design, the students must implement their designs using gate-level constructs. We encourage the students to look at various adder designs and give extra credit for the use of more complex adders. As a part of their report, the students must determine the minimum and maximum delays through the ALU which will help them when they must integrate this module into a full microprocessor design. Perhaps one of the more traditional design projects, counter design, provides the student with the tools needed to make special purpose registers in their microprocessor design. This lab also exposes the student to one of the practical considerations involved in counter design, cascadability. The 4-bit counter is designed using gate-level constructs, and has the ability to perform count up, count down, parallel load, asynchronous preset. and asynchronous clear. The student must prove the cascadability of their design by building at least an g-bit counter using their basic counter module and no external logic. As part of the report. the student must determine the propagation delay of the counter for each of the functions.
Hierarchical digital systems modeling
317
One of the concepts with which the students have had trouble is the use of k-state gate constructs in connecting circuits to a common bus. The sixth and seventh labs provide experience with tri-state gate designs and point out the advantages they provide. First the student constructs an 8-bit register capable of parallel load and with tri-state outputs. Then they combine eight instances of this module into a single module, a register file with eight registers (REGS x 8), and interconnect them within the module using a common bus. The student must decide how many control signals are needed to allow each register to operate without interfering with the operation of the other registers. Each register is given an initial state and the student designs the simulation to accomplish a series of register transfers specified in the lab and prints out the contents of each of the registers at the conclusion of the simulation. The sixth lab encourages the use of behavioral constructs to step through the various control signals needed to perform the transfers, but the seventh and final lab requires the use of a finite state machine to provide the control signals. This will provide the students with the experience necessary to build up complex sequence of micro-instructions using simple state machines and assorted control logic. Each of the two large-scale designs is similar to the core ALU and register set of first generation 8-bit microprocessors. The Verilog description for the hardwired design was an behavioral register-level transfer design. The microprogrammed CPU design was either an behavioral or gate-level design. Output from an example hardwired design [5], provided to the students, is shown in Fig. 9. For the behavioral hardwired CPU designs, the physical implementation was a register-transfer CPU description, similar to designs described in [1,5-71, which emphasized design fundamentals including proper instruction-set architecture design, register-set design, memory address and buffer register designs, status register design, instruction register design, bussing considerations and ALU design. The primary design goal of this project was the development of a good understanding of a register-transfer language, the necessary components of that language, how the register-transfer //A 16-bit single level carry skip adder based on 4 4-bit ripple carry (RC) blocks. //Intermediate RC blocks contain P-term circuitry for propagating carry. ‘include “rca.v’ ‘include “rca_p.v’ module cs_adder(sum,cout,a,b,cin,s); input [15:0] a,b; input tin; input [I :0] s; output tout; output [15:0] sum; wire 13111co; wire [2:1] ci,cp; wire [3:0] pO,pl; rca block-0 (sum[03:00].co[l ],a[O3:@3],b[03:00],cin,s); rca_p block-1 (sum[07:04],co[2],p0,a[07:04],b(07:041,co[l],S); rca_p block-2 (sum[ll:O6],~0[3],pl,a[ll:O6],b[ll:06l.ci[ll,s); rca block-3 (sum[15:121,cout.a[15:121,b[15:12].ci[21,s); and #(IO) (cp[~l,co~~l,~O[Ol,~O~~l,pO~~1~PO~31~~ or #(lo) (ci[l],cp[ll,co(21); and #(lo) (cp[2l,ci[ll,Pl[O1,~l[ll~~lI2l~Pl(31)~ or #(IO) (ci(2],cp[2],col31): endmodule S
bi’s ai’s
s hi’s ai’s
s bi’s ai’s
s bi’s ai’s
tin
shm
sum
sum
Fig. 8. A 16-bit carry skip adder.
s;m
language detines physical implementation requirements, and how the operation of all components of the CPU may be described by the register-transfer language. The design specifications were very open to allow the student to explore various options within the assignment. The microprogrammed CPU project design goals were the understanding of micromemory or control memory organization, various microsequencing capabilities and requirements, and proper aspects of microinstruction-set architecture design. Output from an example microprogrammed design [5], provided to the students, is shown in Fig. 10. The choice of behavioral vs gate-level design of this project gave motivated students the opportunity to expand on their knowledge of
THE MAN11 HARDWlRtlD
TR=
I
OUTR=
MICROC‘OMPL~TER
q
T=-
Computer
phase
Instruction
type
Hierarchical
************
THE MAN0
digital
modeling
MICROPROGRAMMED
AC = m
CAR = m
PC = m
(‘ND = 0
CURRENT
SBR =
COMPUTER
******************
q
IB
output
319
MICROINSTRUCTION
II:===
Fig. 10. Example
systems
from the Mano
microprogrammed
mrmr
microcomputer.
Verilog and allowed a more complete understanding of the mapping from the Verilog description to a physical realization of their design. Approximately 20% of the design teams chose to implement a gate-level Verilog design and the author believes these students obtained the best understanding of the design fundamentals. The project completion time for the designs was approx. 5 weeks with the students spending approx. 2 weeks on design considerations, IL2 weeks coding the Verilog descriptions. 1 week debugging and testing, and 1 week of project report generation. The size of the Verilog descriptions ranged from several hundred to several thousand lines of code depending on the students grasp of efficient coding techniques, detail of the simulation (event-level vs gate-level descriptions), and detail of the design. Example projects are available via anonymous ftp from ftp.carl.ua.edu. A student opinion survey was conducted to allow the author to evaluate the use Verilog in the described course. This survey was intended to allow the determination of the student opinion of the ease of learning Verilog. the usefulness of Verilog, the amount of class time that should be devoted solely to a description of Verilog, the number of Verilog-related assignments that should be given. and whether or not the use of Verilog added to the learning experience for the class. The majority (81%) of the students felt the semantics and the syntax of the language were simple to understand. The students rated the difficulty of learning the language an average of 5.25 (10 = most difficult) with timing and behavioral programming the most difficult concepts to comprehend. The students rated the usefulness of Verilog as 8.00 (10 = very useful). Approximately half (54%) of the students felt the time spent learning Verilog, approx. 2 weeks, was adequate but also felt that additional examples and documentation would be helpful. The remaining students felt that an additional one or two weeks were necessary to introduce Verilog. The majority of students (84%) felt that Verilog added to the learning experience in the course.
320
David
Jeff Jackson
The survey also reflected the fact that the majority of the students felt that a formal laboratory with additional Verilog-oriented assignments would be beneficial for the course and would likely enhance their understanding of the course material. The majority of the students also felt that more emphasis on gate-level descriptions would then be feasible and preferable. 4. CONCLUSIONS The Verilog HDL has been introduced into a computer engineering course to establish and test a hierarchical design and teaching methodology. A hierarchy of modeling techniques from event to gate-level descriptions has also been presented. HDL descriptions have been used to describe various aspects of computer architecture fundamentals including instruction set architecture design, register transfer languages, microprogramming fundamentals, and gate level designs of basic digital components. These aspects, when presented in a hierarchical fashion, allow the computer engineering student to explore many different design possibilities when given an open-ended project or assignment. From a pedagogical perspective, it is seen that a mixed event and gate-level description provides the most insight to CPU design, and to the intricacies of an HDL description, while at the same time maintaining a reasonable degree of complexity and student involvement. Also, the incorporation of HDL-based design into an undergraduate course is seen as a highly economically feasible introduction to modern digital systems design. REFERENCES I. E. Sternheim, R. Singh and Y. Trivedr, D@ul Design nirh Verilog ” HDL. Automata Publishing Company, Cupertino, Calif. (1990). and Y. Trivedr. Digital Design and Synfhesis wifh Verilog HDL. Automata 2. E. Sternheim, R. Singh, R. Mahavan Publishing Company, San Jose, Calif. (1993). 3. G. Micheli, Synfhesis and Optimization of Digifd Circ.urf.s. McGraw---Hill, New York (1994). 4. J. L. Hennessy and D. A. Patterson. Compufrr ArchirucfurP: A Quanfifafizv Approach. Morgan Kaufmann, San Mateo, Calif. (1990). Englewood Cliffs, N.J. (1993). 5. M. Morris Mano, Computer Syrfem Architecfurr, 3rd edn. PrenticeeHall. 6. D. J. Jackson and S. J. Hannah, Enhancing computer engineering education with Veriloa” HDL. Proceedings I of _ fhe Twenty-Fourth Soufheasfern Symposium on_Svstem Theor:,, pp. 125-128 (1993). I. D. E. Thomas and P. Moorby, The Verilog ’ Hrrrdwure Descriprion Language. Kluwer Academic Publishers, Norwell, Mass. (1991). 8. Verilog-XL Rcjkence Manual. Vol. 1, Ver. I .h. Cadence Design Systems Inc. (1991). 9. Verilog-XL Reference Manual. Vol. 2. Ver. 1.6. Cadence Design Systems Inc. (1991).
AUTHOR’S BIOGRAPHY David Jeff Jackson received a BS in physics in 1984 and a MS in electrical engineering
in 1986. both from Auburn University. He received the Ph.D. from The University of Alabama in 1990. He has been an assistant professor in electrical engineering at The University of Alabama since 1990. His research interests include hardware description languages, parallel and distributed computing, and fractal image compression. Professor Jackson is a member of the IEEE, ACM, IEEE Computer Society, ASEE and numerous other professional societies.
Pergamon
004s7906(95)ooo16-x
Copyright 0 Printed in Great
1995 Elsevier Science Ltd
Britain. All rights reserved 0045-7906/95 $9.50+ 0.09
HIERARCHICAL DIGITAL SYSTEMS MODELING UTILIZING HARDWARE DESCRIPTION LANGUAGES FOR COMPUTER ENGINEERING EDUCATION DAVID JEFF JACKSON Department of Electrical Engineering, P.O. Box 870286, The University of Alabama, Tuscaloosa, AL 35487. U.S.A. (Received
6 June 1995)
Abstract-This paper describes a hierarchical modeling approach and teaching methodology for digital microcomputer system modeling including abstract event modeling, mixed-mode event and timing-based, and gate level modeling. A structured instructional approach to fundamentals of computer design and simulation is given based on the Verilog hardware description language (HDL). Example models are given for common digital system components which illustrate the hierarchical learning model presented. Example simulation methods, various simulation hierarchies, and graphical simulation output are presented for the Verilog models discussed. Aspects of the simulation hierarchy are given with respect to system complexity, and simulation complexity for implementation and testing. Finally, educational aspects and merits, with emphasis on student perception and evaluation, of this language as a design tool are presented. Key words: Digital system modeling, hardware description languages.
1. INTRODUCTION Computer system modeling via a hardware description language (HDL), in a top-down hierarchical fashion, presents the computer architect/educator with a design methodology which effectively addresses several critical issues. These issues include an appropriate consideration of design complexity, design documentation, and cost effective test and debug procedures. Traditional schematic design procedures for large scale systems are inadequate when these issues are fully and properly considered. Additionally, pedagogical considerations for teaching digital microcomputer design are simplified with the incorporation of HDL-based design. Other useful characteristics of HDL design include complete design specification, early design stage simulation capabilities, and the capability of implementation via logic synthesis [l]. Introductions to HDL-based design methodology are given by Sternheim in Ref. [2] and Micheli in Ref. [3]. Modeling computer systems is a process which is well suited to a hierarchical design methodology. Generally, most computer architecture designs proceed in a top-down fashion. The major levels of this hierarchy include instruction set architecture (ISA) design, register transfer language (RTL) design, gate-level design, and ultimately switch and transistor level design. An HDL design methodology may be incorporated into any of these steps and can thus be justified as an effective tool for hierarchical digital system design. The use of an HDL simplifies the design process by allowing a smooth transition, in either direction, between each of the design stages. For example, an ISA design may be completely specified and tested solely as a behavioral simulation. The corresponding RTL description may be modeled as an event-only simulation or a mixed-mode event-and-gate level simulation. Finally, the gate-level design may be derived from the RTL specification and may consist of a gate and switch-level description. Many modeling considerations may be made involving the complexity of the simulation process at each stage in the hierarchy. Generally, the high level stages of the hierarchy are intended to verify the correctness of the ISA or RTL model. As such, the model complexity is simple and general to allow for rapid prototyping of the design. Figure 1 illustrates a possible description/simulation hierarchy and the corresponding level of computer hierarchy which is typically specified by the description. 311
David Jeff Jackson
312
Architecture Description Hierarchy
Modeling Hierarchy
event specification
Instruction Set Architecture
event ant” specwarlon
Register Transfer Language Specification
L-r-J \rt/,
I
I
I
Fig. 1. Modeling
2. A HIERARCHICAL
hierarchy and corresponding
J
computer
description
EDUCATION MODEL: DESIGN
HDL
hierarchy
BASED
DIGITAL
An introductory computer engineering course, for electrical engineering and computer science students, can provide an excellent environment for incorporating HDL-based design at the register transfer level or gate level in the modeling hierarchy. For this course, a prerequisite knowledge of high level language (typically “C”) programming, digital logic, assembly language programming, and general microcomputer hardware should be assumed. After introduction of basic computer architecture fundamentals and nomenclature associated with register transfer languages, a coverage of basic Verilog semantics [8,9] allows the student to design and simulate models, using the Cadence Verilog HDL simulator, of typical digital system components including multiplexers, decoders, and various combinational and sequential networks. Concurrently, a more detailed coverage of Verilog semantics supporting gate-level simulations may be introduced to allow the student to progress downward within the modeling hierarchy. Proceeding downward through the hierarchy allows the 4 weeks
1 week
2 weeks
1 week
2 weeks ,-
Digital Computer s ‘g Fundamentals 2 5i Register C Transfer Language
Verilog Introdnu$ion Procedural Semantics
Behavioral Semantics and Verilog Examples
Gate Level Semantics and Verilog Examples
HDL description of 5 decoders, muftipfexers and common digital ---w E components .% I Project 6 Description
IFig. 2. A typical
Behavioral and Gate Level CPU Descriptions
Gate Level Design Problems
Gate Level Adder Designs Project )Completior *I
6 weeks HDL
learning
and design process
pipeline.
Hierarchical
digital systems modeling
313
student to build successively more complex models and obtain a more complete understanding and appreciation for the design process and the relationships between lower-level gate-level circuits and their corresponding “abstract” modules. Proper emphasis on establishing a modular design approach for HDL-based descriptions of digital components is a significant aspect of the design process. If the student utilizes modular design techniques, subsequent assignments/projects may properly build on previous designs by allowing the student to use previously constructed HDL modules to create more complex designs. For example, a student’s initial assignments may be to build and test HDL descriptions of decoders, multiplexers and other common digital components. Subsequent assignments may then make use of the previously constructed modules as building blocks. A pipelined learning process may be developed, as shown in Fig. 2, to allow the student to completely design and simulate major components of a central processing unit (CPU) within a single semester course. The pipelined learning process may be extended by allowing the student to explore additional CPU design possibilities including microprogrammed vs hardwired design methods, stack oriented machines, and various ALU configurations in a second project. Example behavioral and gate level descriptions given to students are shown in Fig. 3. Additionally, students construct similar descriptions as beginning exercises. As shown, each of these descriptions have the same input/ output interface so that the same input stimulus test file may be used for both the behavioral and gate level descriptions. Examples of this nature reinforce the desirability of a modular design approach throughout the design hierarchy. A gate level ALU description is given as an example of extending the modular approach throughout the design. The design hierarchy is shown in Fig. 4. Each block in the hierarchy consists of a single Verilog module which contains one or more instances of modules in the immediately lower level of the hierarchy. For example, a 16-bit carry skip adder [4] would consist of two 4-bit ripple carry adder (RCA) blocks, two 4-bit RCA blocks with p-term generation circuitry, denoted RCA-P, to allow the carry to effectively “skip” these intermediate blocks, and //This “always&se” construct models //an ideal 2x4 decoder with the output N signals changing immediately upon // any input change. module decode2x4(out,in); input [0: 1] in: output [0:3] out; always 8 in begin case (in) 0: ouk’b0001;
1:out=‘bOOl
0;
2: out=‘bOlOO; 3: ouk’bl 000; endcase end endmodule
//This module models an ideal 2x4 decoder // at the gate level and consists of 2 inverters // and four AND gates. module deccdeZx4(out,in); input [l:O] in; output [3:0] out; //define wire inverter outputs for inputs to AND gates. wire u010,u020; not uO1 (uOlo.in[O]); not ~02 (uMo,in[l]); and and and and
~04 (out[O]. ~01o, ~020); ~05 (out[l].in[O]. ~020); ~06 (out[2]. uOlo,in[l]); ~07 (out[3].in[O],in[i]);
endmodule
Fig. 3. Behavioral and gate level descriptions of a 2 x 4 decoder.
David
314
Jeff Jackson
ALU Module
Carry Skip Adder Module
Ripple Carry Adder Module
Logic Unit Module
2X1
MUX
Ripple Carry Adder Module with P-Terms
Carry Skip Gates
Fig. 4. Hierarchical
design structure
Logic Unit Bit
of a 16-bit ALU.
additional carry skip gates. Circuit diagram and Verilog details for this particular adder are given in Fig. 8. The Verilog descriptions for other example modules are given in Figs 5-7 which include logic diagrams for the components being simulated. Through the provided examples, students are introduced to various aspects of digital system design including procedures for developing modular designs, design verification using suitable test module mux2xl (out,inO.rnl ,s); output out; input inO.inl; input s; wire sn; wire [l:O] 1;
’ 4
or #(lo)
(t[l].inl,
I
I
(t[O],inO,sn):
and #(lo)
in1
I
j
Mul$!axer
not #(IO) (sns); and #(lo)
in0
I
I
s);
out
(out,t[O].t[l]);
endmodule
module mux4xl(out,in.s); output out; input [3:0] in; input (l:O] s; wire [l:O] sn; wire [3:0] t; not #(lo)
EE .E .c
5i.K E z
(sn[O].s[O]);
not #(IO) (sn[l],s[l]);
s[l:0]
and #(IO) (t[O].in[O],sn[O],sn[l]); and #(lo)
(t[l],in[l],
and #(lo)
(t[Z],in[2],sn[O],
and #(lo)
W%in[sl.sIO1. ~411);
4x1 Multiplexer
s[O].sn[l]); s[l]);
‘1’_” out
or #(lo) ~out,t[ol.tlll.t[2l,t[31); endmodule
Fig. 5. Gate level multiplexer
descriptions.
Hierarchical digital systems modeling
315
vectors, and common problems encountered in digital design including propagation considerations and race conditions that may exist in combinational logic circuits. 3. EDUCATIONAL
EXPERIENCES
WITH
VERILOG
delay
HDL
For an introductory course in computer engineering, students are required to perform multiple Verilog-based laboratory exercises and submit two large-scale Verilog designs: a hardwired microprocessor and a microprogrammed microprocessor. The first two laboratories serve to introduce the students to the two major capabilities that Verilog offers the digital designer-gate level simulations and behavioral level simulations. These labs allow the student to become accustomed to the tools without being overwhelmed by the projects themselves. As the students are accustomed to design using discrete IC components, the first lab consists of two basic designs requiring the use of flip-flops and logic gates. In this manner, the student can take a logic diagram, which used to be the end result of their work, and extend that to involve testing the design’s validity. The first circuit to be simulated is a 4-bit comparator. As a requirement for the design, the student must break the design into two modules consisting of the test module and the comparator module. This is the first attempt at directing the student towards a hierarchical design flow. If the student becomes acclimated to the hierarchical design process, they discover significant design time savings which become critical in subsequent laboratory exercises. The second design is a four-bit shift register. This design serves to introduce the student to the use of constructs capable of storing information. The second lab introduces the student to the ease of simulating circuits using Verilog’s behavioral simulation constructs. This is less familiar to the student, but it’s similarity to the high level languages C and Pascal help overcome their discomfort. The first circuit in this lab is an 8-bit comparator capable of generating “less than”, “greater than” and “equal to” outputs. This is a trivial program, so we introduce one of Verilog’s graphical tools at this time-the waves display. The waves display allows the designer to see how several specified signals vary with time; therefore, //This module is derived from the full adder definition and includes // additional logic for computing A+B.A-B,A+B+l ,A+1 ,A-1, and A based //on the control inputs s[O] and s[l]. The truth table is given as follows: II tin // s[l] s[O] tin output I/ __-___ __-I__-----_--II0 00 A II 0 0 1 A+1 Full _ II 0 1 0 A+B Adder II 0 I 1 A+B+l all 1 0 0 A+0 II 1 0 1 A+B’+l (A-B) II 1 1 0 A-l Ill 11 A II I/ The maximum delay through this //module is 60 simulation time steps. // P generation circuitry is included in this model //to allow construction of carry skip adders. II module adder_bit_p(sum,cout,p,a,b,cin.s); input a,b,cin; input [l :0] s; Full Adder ,________________________-outout sumc0ut.p: 1 wire wl .w2\w3; , wire bl,b2,b3; : b: wire bn; I not #(lo) (bnb); and #(lo) (bl, b,s[O]); and #(lo) (b2,bn,s[l]); or #(lo) (b3,bl,b2); xor #(30) (sum,a,b3,cin); \ and i(ld) (wl ,a,b3); Full Adder and #(lo) (w2,a.cin); , Description and #(lo) (wW3,cin); or #(lo) (cout,wl,w2.w3); I or #(lo) (p,a.b3); Fig. 6. Single bit full adder/subtracter
sum
with p-term generation circuitry.
David
316
Jeff Jackson
// Verilog model for a single bit I/ of the logic unit. // //The maximum delay through this module I/ is 40 simulation time steps (including /I 30 simulation time step delays through //the multiplexer module). II ‘include “mux4xl .v’ module lub(out.a,b,s); output out; input a.b; Input [I :0] 5; wire [3:0] mux_in; mux4xl lub_mux (out,mux_rn,s); and #(lo) (mux_rn[O],a,b); or #(lo) (mux_in[l],a.b); xor #(IO) (mux_in[Z],a,b), not #(lo) (mux_in]3].a); endmodule
a+
mux_in[3]
1
I Frg. 7 A smgle bit of the logic
unit.
as part of the assignment the student has to prove the design works by displaying the timing waveforms. The waves display will be used as a major tool in demonstrating and debugging the lab designs so its use is encouraged early on. In the second part of the lab the students add to the basic design, allowing for a bidirectional bus and an internal register in which to load values for comparison. This design change encourages the use of tri-state buffers which are gate-level constructs, therefore alerting the students to the possibility of mixed simulations. As the students are now familiar with the tools and have had some complex design experience, we begin to focus their learning on the aspects of digital design that will aid them in their final projects (the microprocessor designs). Since an arithmetic logic unit will be a critical part of their design, we introduce an g-bit ALU design. The capabilities that the ALU must have are addition, subtraction, increment, decrement, bitwise AND, bitwise OR, bitwise XOR, and one’s complement. To help the student, we encourage the use of a hierarchical design. Since this is strictly a logic based design, the students must implement their designs using gate-level constructs. We encourage the students to look at various adder designs and give extra credit for the use of more complex adders. As a part of their report, the students must determine the minimum and maximum delays through the ALU which will help them when they must integrate this module into a full microprocessor design. Perhaps one of the more traditional design projects, counter design, provides the student with the tools needed to make special purpose registers in their microprocessor design. This lab also exposes the student to one of the practical considerations involved in counter design, cascadability. The 4-bit counter is designed using gate-level constructs, and has the ability to perform count up, count down, parallel load, asynchronous preset. and asynchronous clear. The student must prove the cascadability of their design by building at least an g-bit counter using their basic counter module and no external logic. As part of the report. the student must determine the propagation delay of the counter for each of the functions.
Hierarchical digital systems modeling
317
One of the concepts with which the students have had trouble is the use of k-state gate constructs in connecting circuits to a common bus. The sixth and seventh labs provide experience with tri-state gate designs and point out the advantages they provide. First the student constructs an 8-bit register capable of parallel load and with tri-state outputs. Then they combine eight instances of this module into a single module, a register file with eight registers (REGS x 8), and interconnect them within the module using a common bus. The student must decide how many control signals are needed to allow each register to operate without interfering with the operation of the other registers. Each register is given an initial state and the student designs the simulation to accomplish a series of register transfers specified in the lab and prints out the contents of each of the registers at the conclusion of the simulation. The sixth lab encourages the use of behavioral constructs to step through the various control signals needed to perform the transfers, but the seventh and final lab requires the use of a finite state machine to provide the control signals. This will provide the students with the experience necessary to build up complex sequence of micro-instructions using simple state machines and assorted control logic. Each of the two large-scale designs is similar to the core ALU and register set of first generation 8-bit microprocessors. The Verilog description for the hardwired design was an behavioral register-level transfer design. The microprogrammed CPU design was either an behavioral or gate-level design. Output from an example hardwired design [5], provided to the students, is shown in Fig. 9. For the behavioral hardwired CPU designs, the physical implementation was a register-transfer CPU description, similar to designs described in [1,5-71, which emphasized design fundamentals including proper instruction-set architecture design, register-set design, memory address and buffer register designs, status register design, instruction register design, bussing considerations and ALU design. The primary design goal of this project was the development of a good understanding of a register-transfer language, the necessary components of that language, how the register-transfer //A 16-bit single level carry skip adder based on 4 4-bit ripple carry (RC) blocks. //Intermediate RC blocks contain P-term circuitry for propagating carry. ‘include “rca.v’ ‘include “rca_p.v’ module cs_adder(sum,cout,a,b,cin,s); input [15:0] a,b; input tin; input [I :0] s; output tout; output [15:0] sum; wire 13111co; wire [2:1] ci,cp; wire [3:0] pO,pl; rca block-0 (sum[03:00].co[l ],a[O3:@3],b[03:00],cin,s); rca_p block-1 (sum[07:04],co[2],p0,a[07:04],b(07:041,co[l],S); rca_p block-2 (sum[ll:O6],~0[3],pl,a[ll:O6],b[ll:06l.ci[ll,s); rca block-3 (sum[15:121,cout.a[15:121,b[15:12].ci[21,s); and #(IO) (cp[~l,co~~l,~O[Ol,~O~~l,pO~~1~PO~31~~ or #(lo) (ci[l],cp[ll,co(21); and #(lo) (cp[2l,ci[ll,Pl[O1,~l[ll~~lI2l~Pl(31)~ or #(IO) (ci(2],cp[2],col31): endmodule S
bi’s ai’s
s hi’s ai’s
s bi’s ai’s
s bi’s ai’s
tin
shm
sum
sum
Fig. 8. A 16-bit carry skip adder.
s;m
language detines physical implementation requirements, and how the operation of all components of the CPU may be described by the register-transfer language. The design specifications were very open to allow the student to explore various options within the assignment. The microprogrammed CPU project design goals were the understanding of micromemory or control memory organization, various microsequencing capabilities and requirements, and proper aspects of microinstruction-set architecture design. Output from an example microprogrammed design [5], provided to the students, is shown in Fig. 10. The choice of behavioral vs gate-level design of this project gave motivated students the opportunity to expand on their knowledge of
THE MAN11 HARDWlRtlD
TR=
I
OUTR=
MICROC‘OMPL~TER
q
T=-
Computer
phase
Instruction
type
Hierarchical
************
THE MAN0
digital
modeling
MICROPROGRAMMED
AC = m
CAR = m
PC = m
(‘ND = 0
CURRENT
SBR =
COMPUTER
******************
q
IB
output
319
MICROINSTRUCTION
II:===
Fig. 10. Example
systems
from the Mano
microprogrammed
mrmr
microcomputer.
Verilog and allowed a more complete understanding of the mapping from the Verilog description to a physical realization of their design. Approximately 20% of the design teams chose to implement a gate-level Verilog design and the author believes these students obtained the best understanding of the design fundamentals. The project completion time for the designs was approx. 5 weeks with the students spending approx. 2 weeks on design considerations, IL2 weeks coding the Verilog descriptions. 1 week debugging and testing, and 1 week of project report generation. The size of the Verilog descriptions ranged from several hundred to several thousand lines of code depending on the students grasp of efficient coding techniques, detail of the simulation (event-level vs gate-level descriptions), and detail of the design. Example projects are available via anonymous ftp from ftp.carl.ua.edu. A student opinion survey was conducted to allow the author to evaluate the use Verilog in the described course. This survey was intended to allow the determination of the student opinion of the ease of learning Verilog. the usefulness of Verilog, the amount of class time that should be devoted solely to a description of Verilog, the number of Verilog-related assignments that should be given. and whether or not the use of Verilog added to the learning experience for the class. The majority (81%) of the students felt the semantics and the syntax of the language were simple to understand. The students rated the difficulty of learning the language an average of 5.25 (10 = most difficult) with timing and behavioral programming the most difficult concepts to comprehend. The students rated the usefulness of Verilog as 8.00 (10 = very useful). Approximately half (54%) of the students felt the time spent learning Verilog, approx. 2 weeks, was adequate but also felt that additional examples and documentation would be helpful. The remaining students felt that an additional one or two weeks were necessary to introduce Verilog. The majority of students (84%) felt that Verilog added to the learning experience in the course.
320
David
Jeff Jackson
The survey also reflected the fact that the majority of the students felt that a formal laboratory with additional Verilog-oriented assignments would be beneficial for the course and would likely enhance their understanding of the course material. The majority of the students also felt that more emphasis on gate-level descriptions would then be feasible and preferable. 4. CONCLUSIONS The Verilog HDL has been introduced into a computer engineering course to establish and test a hierarchical design and teaching methodology. A hierarchy of modeling techniques from event to gate-level descriptions has also been presented. HDL descriptions have been used to describe various aspects of computer architecture fundamentals including instruction set architecture design, register transfer languages, microprogramming fundamentals, and gate level designs of basic digital components. These aspects, when presented in a hierarchical fashion, allow the computer engineering student to explore many different design possibilities when given an open-ended project or assignment. From a pedagogical perspective, it is seen that a mixed event and gate-level description provides the most insight to CPU design, and to the intricacies of an HDL description, while at the same time maintaining a reasonable degree of complexity and student involvement. Also, the incorporation of HDL-based design into an undergraduate course is seen as a highly economically feasible introduction to modern digital systems design. REFERENCES I. E. Sternheim, R. Singh and Y. Trivedr, D@ul Design nirh Verilog ” HDL. Automata Publishing Company, Cupertino, Calif. (1990). and Y. Trivedr. Digital Design and Synfhesis wifh Verilog HDL. Automata 2. E. Sternheim, R. Singh, R. Mahavan Publishing Company, San Jose, Calif. (1993). 3. G. Micheli, Synfhesis and Optimization of Digifd Circ.urf.s. McGraw---Hill, New York (1994). 4. J. L. Hennessy and D. A. Patterson. Compufrr ArchirucfurP: A Quanfifafizv Approach. Morgan Kaufmann, San Mateo, Calif. (1990). Englewood Cliffs, N.J. (1993). 5. M. Morris Mano, Computer Syrfem Architecfurr, 3rd edn. PrenticeeHall. 6. D. J. Jackson and S. J. Hannah, Enhancing computer engineering education with Veriloa” HDL. Proceedings I of _ fhe Twenty-Fourth Soufheasfern Symposium on_Svstem Theor:,, pp. 125-128 (1993). I. D. E. Thomas and P. Moorby, The Verilog ’ Hrrrdwure Descriprion Language. Kluwer Academic Publishers, Norwell, Mass. (1991). 8. Verilog-XL Rcjkence Manual. Vol. 1, Ver. I .h. Cadence Design Systems Inc. (1991). 9. Verilog-XL Reference Manual. Vol. 2. Ver. 1.6. Cadence Design Systems Inc. (1991).
AUTHOR’S BIOGRAPHY David Jeff Jackson received a BS in physics in 1984 and a MS in electrical engineering
in 1986. both from Auburn University. He received the Ph.D. from The University of Alabama in 1990. He has been an assistant professor in electrical engineering at The University of Alabama since 1990. His research interests include hardware description languages, parallel and distributed computing, and fractal image compression. Professor Jackson is a member of the IEEE, ACM, IEEE Computer Society, ASEE and numerous other professional societies.