- Email: [email protected]
High ESD performance, low power CMOS LNA for GPS applications
ARTICLE IN PRESS
Journal of Electrostatics 59 (2003) 179–192
High ESD performance, low power CMOS LNA for GPS applications$ Paul Lerouxa,*, Vesselin Vassileva,b, Michiel Steyaerta, Herman Maesa,b a
K.U. Leuven, Department of Electrical Engineering, ESAT-MICAS, Kasteelpark Arenberg 10, B-3001 Leuven-Heverlee, Belgium b IMEC, Kapeldreef 75, 3001 Leuven-Heverlee, Belgium
Received 6 November 2002; received in revised form 28 February 2003; accepted 10 March 2003
Abstract This paper describes the design of a high performance 0.25 mm CMOS low noise amplifier (LNA) for the global positioning system (GPS) operating at 1.57 GHz. The LNA features a 1.5 dB noise figure. The input ESD-protection is in the order of 3 kV HBM and the power consumption is only 6 mW. r 2003 Elsevier Science B.V. All rights reserved. Keywords: ESD protection; CMOS LNA; GPS
1. Introduction In the recent years, a lot of research has been performed on the possibility of using pure CMOS, rather than bipolar or BiCMOS technologies for RF-applications. An example of such an application is global positioning system (GPS). The performance specifications of high-end GPS receivers are quite severe, requiring designs with good sensitivity as well as low noise amplifiers (LNAs) with low noise figure and high gain. One of the main bottlenecks for introducing CMOS RF circuits to the market is their susceptibility to ESD. It is due to both gate oxide breakdown and junction degradation related problems, caused by the decreased oxide thickness and increased $
r 2002. Reprinted with permission, after revision, from Electrical Overstress/Electrostatic Discharge Symposium Proceedings, EOS-24, Charlotte, NC, USA, October 8–10, 2002. *Corresponding author. Tel.: +32-16321877; fax: +32-16321975. E-mail address: [email protected] (P. Leroux). 0304-3886/03/$ - see front matter r 2003 Elsevier Science B.V. All rights reserved. doi:10.1016/S0304-3886(03)00063-9
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doping levels in the scaled down technologies [1]. The ESD problems are further increased by the tight design window for the high performance RF circuits, not allowing large ESD devices to be used as protection elements [2]. Before CMOS LNAs can be introduced to the market they need to satisfy the ESD standard of minimum 2 kV HBM. This paper shows that it is possible to design an LNA with good RF-performance while providing good ESD-immunity. Most CMOS ESD-protection structures have parasitics that are detrimental for the LNA performance. They commonly feature two large clamping devices with a current limiting resistor in between. The resistance added at the input (up to a few hundred ohms), would be detrimental for the noise figure of the LNA. The introduced parasitic input capacitance also has a serious influence on the LNA performance. This influence will be explained briefly in the first section. The design and layout of the 1.57 GHz LNA are discussed in the following sections, together with the ESD and RF characterization results. 2. Design 2.1. LNA design considerations Fig. 1 depicts the input of an inductively degenerated, common source LNA. Consider first the ideal case where no parasitic input capacitance, Cp ; is present. VS and RS represent the signal source that feeds the LNA. This is the output of either the antenna or a bandpass channel select filter. In both cases the impedance of the source is 50 O. As a consequence the LNA input should be matched to 50 O in order to absorb as much signal power as possible and to avoid distortions in the filter characteristic due to incorrect termination. Since the common source amplifier ideally has no input resistance, only input capacitance, the source degeneration inductor LS provides an ‘artificial’ resistive input impedance equal to oT LS : The gate–source capacitance is tuned out by a gate inductor, Lg ; in order to create a purely resistive input.
Fig. 1. Influence of Cp on LNA performance.
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However, in real life, some parasitic input capacitance is always present. Part of it is coming from the input bonding pad, another part belongs to the gate–drain capacitance. A normal ESD-protection network adds even more capacitance to that. This capacitance, Cp ; increases the noise figure of the LNA and decreases its gain. It also places an upper bound on the attainable input impedance values. If oCp is too high, it even becomes impossible to obtain an input match without an external matching circuit. It is instructive to define two reference planes 1 and 2 and to look at the different impedance levels at these nodes. Looking towards the source at reference plane in Fig. 1, the gate sees an equivalent input resistance Req larger than 50 O, and a series inductance Leq slightly larger than Lg : They are given by [3] Req ¼
Leq ¼
RS ; o20 Cp2 R2s þ ð1 o20 Cp Lg Þ2 Lg Cp ðo20 L2g þ R2s Þ o20 Cp2 R2s þ ð1 o20 Cp Lg Þ2
:
The noise factor of the LNA may be shown to be approximately given by 2 2 o0 g adð1 jc2 jÞ o0 g 2 gm Req þ : F ¼1þ þ kgm Req or a oT a k
ð1Þ
ð2Þ
ð3Þ
Notice that the noise factor features a term directly proportional to gm Req ; coming from the classical drain noise, and a term inversely proportional to gm Req coming from the non-quasistatic noise. Due to the presence of Cp and hence, the higher value for Req ; the noise figure is primarily determined by the classical drain noise contribution. As the ESD-protection circuit even increases Cp ; Req becomes larger and the noise figure increases further. Cp also has an influence on power gain. In order to have a high power gain, a high squared output current (jiout j2 ) is required for a given available source power, Pav : Its value may be calculated as a function of Req : 2 oT Pav 2 ; ð4Þ jiout j ¼ o0 Req where Pav is the available input power from the antenna. Rin is the real part of the impedance, seen to the right of reference plane 2. It is equal to Req for a perfect input match. The power gain Gt is then given by Rload oT 2 : ð5Þ Gt ¼ 4 Req o0 If the value of Cp increases, Req becomes larger and the amount of output current decreases. Hence, a higher Cp implies a lower power gain. However this decrease in gain may be somewhat compensated by lowering the value of Rin ; i.e. by reducing the source degeneration inductance Ls : In our design, we targeted at an S11 of 12 dB.
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The dependence of the LNA linearity, characterized by its IIP3, on the VGS VT (Vgt ), technology and input matching is shown in the following equation: ! 4 Vgt ð1 þ YVgt Þ2 ð2 þ YVgt Þ IIP3½dBm E 16 þ 10 log 3 Y sffiffiffiffiffiffiffiffiffiffi! 50 O þ 20 log o0 Cgs ðReq þ Rin Þ : ð6Þ Req The first part of this equation is derived from the well-known MOS current equation under mobility degradation which is modeled by the factor Y: For a transistor without matching section (only the first term in (6)), the IIP3 improves with increasing VGS VT and deteriorates with deeper submicron technologies. For a matched transistor, the dependencies get more complex because the IIP3 decreases with decreasing equivalent source resistance (Req ). The 16 term converts the units from dBVamp to dBmav : 2.2. The 1.57 GHz LNA for GPS A simplified schematic of the circuit is shown in Fig. 2. The biasing details are not shown. The circuit uses the same topology discussed in the previous section. The input bonding wire is used as gate tuning inductor since the Q of an on-chip inductor would be too low resulting in a high noise figure. The input bonding pad is shielded from the substrate by grounding the bottom metal layer. This drastically increases the Q of the bond pad capacitance and prevents noise coupling from the substrate. Furthermore, the pad capacitance has been minimized by using only the top metal layer and octagonal layout. Limiting this capacitance was of extreme importance to create a sufficiently large headroom for the capacitance of the ESD devices. The details of the ESD-protection network will be discussed in the next section.
Fig. 2. Simplified LNA schematic.
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The source degeneration inductor, Ls ; is implemented as two parallel bonding wires. The load inductor, Ld ; is realized on chip. Its series resistance is depicted as Rs and its parasitic capacitance to the patterned ground shield beneath it, is included in C1 : C1 (together with the pad capacitance Cbp;out ) and bonding wire Lout constitute the output matching network for obtaining a 50 O output impedance. Eqs. (1)–(6) have been used to describe the design space of the LNA and to visualize the influence of the equivalent source resistance (Req ) and the transistor sizing on the noise figure, gain and linearity of the LNA. A higher value for Req is beneficial for the linearity but is bad for noise and gain performance. Since, for the GPS application, the latter constraints are more binding, Req is chosen sufficiently low. As Req increases with the amount of parasitic input capacitance (1) the capacitance available for the ESD-protection is limited. Moreover, the tolerated capacitance decreases with the operating frequency of the circuit. The LNA, operating at 1.57 GHz, has been simulated and optimized both with and without the ESD-protection diodes. Simulations were done with HSPICE. The MOS model that was used is level 49, BSIM3v3. Both the MOS transistors and the diodes were placed within a subcircuit to include extra parasitics that are not implemented in the BSIM3v3 model. This allowed us to model the Non-QuasiStatic effect of the channel charge buildup which has a significant influence on the RFperformance. We also included bulk and well resistances for both the diodes and transistors which influences both high-frequency and high-current behavior. The noise figure and power gain are plotted vs. the capacitance of the ESDprotection diodes in Fig. 3. The other contributors to the capacitance are also taken into account in these simulations but they are not included in the value of CESD : It is seen in this figure that the NF increases from 0.9 to 1.5 dB for a capacitance of 350 fF. The power gain decreases from 19.3 to 15.7 dB. Beyond this capacitance
Fig. 3. LNA noise figure and power gain as a function of ESD-capacitance.
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Table 1 Comparison between the simulated RF-performance of the LNA with and without input ESD-protection
Power consumption Current consumption Supply voltage S11 @ 1.57 GHz S21 @ 1.57 GHz S12 S22 @ 1.57 GHz NF @ 1.57 GHz IIP3
Without ESD-protection
With ESD-protection
9 mW 6 mA 1.5 V 14 dB 19.3 dB o30 dB 23 dB 0.9 dB 6.8 dBm
9 mW 6 mA 1.5 V 14 dB 18.4 dB o30 dB 25 dB 1.0 dB 5.1 dBm
value the circuit can no longer be matched to 50 O without an external matching network. For higher frequencies this effect becomes more pronounced, i.e. the curves will be steeper and the cut-off capacitance becomes lower. In our design the ESD diodes have a total capacitance of about 100 fF yielding ESD protection of 3 kV HBM. Table 1 shows a comparison between the main simulation results with and without ESD-protection. This table confirms the theoretical discussion given above. Adding the ESD-protection at the input reduces the power gain from 19.3 to 18.4 dB. The noise figure increases from 0.9 to 1 dB. The IIP3 improves from 6.8 to –5.1 dBm. All these effects are attributed to the increased parasitic input capacitance causing an increased value of the equivalent input impedance, Req : 2.3. ESD protection design considerations The ESD protection device network was designed as shown in Fig. 4. It consists of two diodes, D1 and D2, between the RF input and the power supply busses and of a stack of five diodes D3D7 between Vdd and Vss : The goal is to provide an explicit ESD discharge current path for all possible stress combinations between the input, Vdd and Vss : The use of diodes was based on the fact that they are very efficient and robust ESD devices. Furthermore, their characteristics are fairly simple to model and simulate, allowing a reliable sizing of these devices. Since the LNA was designed for a fully integrated GPS receiver, where the output node of the LNA directly connects to the mixer input, no output ESD-protection is required. Key considerations in the D1–D2 input diodes design is their capacitance, and their high frequency and high current resistance. The first two affect the RF performance of the LNA (as shown earlier), the second influences the ESD performance of the circuit and, in particular, the bias developed on the input node/gate of the LNA during the ESD pulse. Both the capacitance and the resistance should be kept at minimum, requiring suitable diode optimization. The diodes can be laid out as one finger or multiple finger devices. It is a wellknown fact that the junction capacitance of the diode is related mostly to the bottom
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Vdd
D1 D3-D7
in D2
Vss
Fig. 4. The p+n-well diode-based ESD protection network designed around the core RF-LNA circuit.
plate of the diode while the current flows mostly through the sidewall. Hence to minimize the capacitance and the resistance of the diode we need to minimize the area and maximize the perimeter. This clearly pleads in favor of a multiple finger structure. Moreover, a one finger diode may give current crowding at the corners, yielding dangerous hot spots where breakdown may initiate. To avoid this the diodes were implemented with several fingers. These fingers may be realized either as squares or stripes. Stripes give the advantage of a very low resistance since the average distance from a p+ to n+ contact is minimal while still providing sufficient contacts per finger. On the other hand, current crowding and the resulting hot spots may occur at the small ends of the stripes. This problem may be somewhat alleviated by removing the contact closest to the end of the stripe in order to increase the resistance in that path preventing current crowding. When using squares, the average resistance will be a little higher than with stripes but a uniform current distribution is more easily obtained. The chip discussed in this paper uses a multiple finger structure of square diodes. The area of the squares was chosen as small as possible while keeping more than one via for each square. The area of one diode square in our design is 9 mm2 giving a total area of 36 mm2 for a total capacitance of 50 fF per diode (one to Vdd and one to ground). The layout of the diodes is illustrated in Fig. 5. Simulation of the low frequency input capacitance Cin ; due to D1 and D2, as function of the applied DC input and Vdd biases is shown in Fig. 6. Since the value of Cin is relatively constant around the DC operating point, it does not significantly degrade the linearity of the circuit. The design of the diode string D3–D7 between the supply rails was done based on the Vdd to Vss leakage current specifications and the small high current resistance requirements. In an n-well CMOS technology a p+n-well diode is actually a pnp transistor [4]. Hence, when you connect a series of diodes and some current is injected in the top diode, the current through the next diode is reduced by a factor 1 þ b; where b is the current amplification of the parasitic bipolar transistor. As a consequence the chain of diodes will start to conduct at a voltage which is lower than the sum of their individual cut-in voltages. This necessitates that sufficient diodes are connected in series such that the current leakage at the operating supply voltage remains negligible. Since N diodes in series are needed and the on-resistance of the
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Fig. 5. Layout of the input protection diodes.
Fig. 6. The simulated input capacitance contribution of D1 and D2 as a function of the applied input DC bias.
clamp should be lower than the on-resistance of the input diodes, these diodes are sized at least n times larger than the input diodes. In this way, the supply clamp withstands higher ESD-stress than the input diodes ensuring that the latter is the limiting factor in the ESD-performance. The increased capacitance of the diode string is not a problem since it just adds to the on-chip decoupling capacitance and does not influence the RF performance. As illustrated in Fig. 7, the diodes in the clamp consist of a multiple finger structure comparable to the input diodes. In this example, three diodes are connected
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Fig. 7. Layout of the supply clamp.
Fig. 8. TLP results for three stress combinations on the nodes, see Fig. 3. The plot represents both the high current device IV characteristics IESD ¼ f ðVdev Þ and the leakage current between the stressed pins, Ileakage ¼ f ðIESD Þ: The jump in Ileakage indicates the ESD failure threshold level. The TLP reverse breakdown characteristic of D2 is also shown.
in series and each diode consists of three fingers. On the chip, however, five diodes are connected in series based on the leakage current specification for a supply of up to 2 V. Each diode therefore consists of twenty fingers which are interconnected with metal.
3. Measurement results 3.1. ESD-protection results Fig. 8 represents the measured Transmission Line Pulse (TLP) characteristics of the LNA circuit for three different stress combinations: INPUT to VDD ; INPUT to
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Table 2 Comparison between the achieved TLP and HBM thresholds for the major pin stress combinations. The other possible stress polarities thresholds can be represented by these results as well. The HBM results stem from a separate on-wafer HBM test Stress polarity þ
IN VDD INþ VSS þ VSS VDD þ VSS VDD
TLP: It2 [A]
HBM: VHBM [V]
1.67 1.62 3.2 4.2
3.2 k 3.2 k >4 k >4 k
VSS and VDD to VSS : For the TLP characterization, a home built 500 O system was used, having 100 ns fixed pulse length, 700 ps pulse rise time, and providing current amplitudes from 5 mA to 4A [5]. The results show that the TLP ESD robustness of the input diodes is of about 1.67 A which corresponds to 2.5 kV Human Body Model (HBM) ESD stress. The diode resistance may be calculated by taking the derivative of Vdev ; the voltage over the ESD-protection device, to the current through the device, IESD : For the input diodes, it is in the order of 2 O. The ESD robustness of the D3–D7 diode stack is B3.25 A, corresponding to B4.9 kV HBM stress and total resistance also in the order of 2 O. The correlation of the TLP results to the HBM performance is for a first-order evaluation only and is done by transforming the TLP It2 current through the 1.5 kO HBM model resistance. Fig. 8 also shows that the IN+ to VDD is more robust than VDD 2VSS : The reason is that in the first case, the ESD current gives only a voltage drop over D1 yielding a reverse voltage divided over six diodes (D2–D7). In the latter case, the ESD current gives a voltage drop over 5 forward diodes (albeit larger ones) which is divided over only 2 smaller reverse diodes, D1 and D2. This will initiate reverse breakdown sooner. Table 2 presents the ESD thresholds, achieved from the actual separate on wafer HBM testing. The worst case ESD stress combination for the circuit is when it is stressed between the input and ground nodes. In this case, the ESD current flows from the input pad through D1, the Vdd bus, the D3–D7 stack and the Vss bus to the Vss output pad. The overall ESD robustness in this case is determined by the lowest of the ESD thresholds of the different components in the current path: D1, D3–D7, the reverse breakdown of D2 and the ESD robustness of the input gate of the LNA. The measured ESD TLP threshold in this case was 1.62 A. The results for the other major stress combination are represented in Table 2. Implementing ESD circuit simulations, one can additionally study and optimize the protection network operation by monitoring the currents and bias developed on the circuit nodes. Fig. 9 represents some results from such a first order 3 kV HBM HSPICE simulation when the stress was applied between the input and the Vss pads. An HBM tester model calibrated to a standard HBM test system and high-current diode models, calibrated to the stand-alone device actual TLP performances were used in the simulations. The rest of the LNA circuit was simulated using the standard, non-ESD HSPICE models. It is justified by the fact that, for these HBM
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Fig. 9. Simulation of 3 kV HBM stress between the input and Vss circuit nodes. The currents through the diodes and the bias developed on the input and Vdd pads are shown.
simulated ESD stress levels, no other core-circuit devices showed to be biased above their nominal operation regime. From the simulation results shown in Fig. 9 one can see that, although most of the HBM current (ID1 B1:6 A) goes through D1 and D3–D7 chain to ground, still significant amount of stress current (ID2 ) goes through D2, operating in reverse breakdown. Knowing the TLP thresholds of the diodes in the different operating modes, it becomes possible to evaluate by simulations the maximum HBM level the diode protection network can survive. Comparing Fig. 9 with Fig. 8 shows that the most likely failure for the circuit in this test is the reverse breakdown of D2, since it is only able to carry about 200 mA in reverse operation. However, it should be noted that simulation of the diode in reverse was not very accurately modeled and the real current through the reverse diode is significantly lower as can also be seen in Fig. 8. Another possible danger for the circuit at higher HBM stress levels, is also indicated in Fig. 9. Increasing the level of the applied ESD stress current will further increase the bias developed on the Vdd bus, above the level of 8–9 V the typical breakdown voltage of the NMOS devices for this particular technology. This will cause snapback and possible degradation of the core RF devices attached to Vdd : It is also seen, that, for this stress level, the bias VIN ; developed on the input pad, is lower than the transient gate oxide breakdown voltage which is typically above 20 V for the given technology generation. Hence, it is unlikely that the ESD failure of the circuit will be caused by the input gate oxide breakdown.
3.2. RF measurement results The LNA has been implemented in a standard 0.25 mm 4M1P CMOS process. It occupies an area of 0.73 mm2. A photograph of the IC is shown in Fig. 10.
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Fig. 10. Micrograph of the LNA.
Fig. 11. Measured power gain and input reflection of the LNA.
For the RF measurements, the LNA is glued on a ceramic substrate and is wire bonded to 50 O strip-lines. The substrate is than mounted in a Copper-Beryllium box which serves as a reference ground. The LNA is biased in two operating regimes drawing 4 and 6 mA from a 1.5 V supply. The complete S-parameter set has been measured using an HP network analyzer. The power gain, S21, is plotted in Fig. 11 for both operating regimes. The maximum power gain at 1.57 GHz is 15.5 and 16.5 dB, respectively. This figure also shows the input reflection of the circuit: S11 is 12 and –13 dB, respectively. The reverse isolation (S12) is measured to be larger than 30 dB throughout the entire range of the network analyzer (300 kHz–3 GHz). The output reflection, S22 is 14 dB. Fig. 12 depicts the measured noise figure for both operating regimes. At 6 mW power consumption, the LNA has a NF of 1.5 dB at 1.57 GHz. In the 9 mW regime the NF is 1.3 dB.
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Fig. 12. Measured Noise Figure of the LNA.
Fig. 13. Measured LNA output power for a two tone test.
The input referred IP3 is 7 and 5 dBm, respectively, for the 6 and the 9 mW bias regime. Fig. 13 shows the measured output power vs. input power for a two tone test in the 6 mW regime. The squares indicate the power of the fundamental signal, the circles indicate the power of the intermodulation terms. The intercept point is at 7 dBm input power. A summary of the RF-performance is given in Table 3. 4. Conclusion This work shows that, even in a standard submicron CMOS technology, a high RF-performance may be combined with a good level of ESD-protection satisfying
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Table 3 Summary of the measured RF-performance of the LNA
Power consumption Current consumption Supply voltage S11 @ 1.57 GHz S21 @ 1.57 GHz S12 S22 @ 1.57 GHz NF @ 1.57 GHz IIP3
Bias condition A
Bias condition B
6 mW 4 mA 1.5 V 12 dB 15.5 dB o30 dB 14 dB 1.5 dB 7 dBm
9 mW 6 mA 1.5 V 13 dB 16.5 dB o30 dB 14 dB 1.3 dB 5 dBm
the industrial specification of 2 kV HBM. This has been demonstrated with a competitive LNA with a low noise figure of 1.5 dB and a gain of 15.5 dB at a very low power consumption of 6 mW. The ESD-protection network at the RF input and the supply clamp yield a protection level of over 3 kV HBM.
Acknowledgements The authors would like to thank Kawasaki Microelectronics Inc. for processing the circuit.
References [1] A. Amerasekera, et al., Analysis of snapback behaviour on the ESD capability of sub-20um NMOS, in: Proceedings of the IRPS 99, 1999, pp. 159–166. [2] M. Radhakrishnan, et al., ESD reliability issues in RF CMOS circuits, in: Proceedings of the IWPSD 2001, International Workshop on the Physics of Semiconductor Devices, December 2001. [3] P. Leroux, J. Janssens, M. Steyaert, A 0.8 dB NF ESD-protected 9 mW CMOS LNA operating at 1.23 GHz, in Journal of Solid State Circuits, June 2002, pp. 760–765. [4] T.J. Maloney, S. Dabral, Novel clamp circuits for IC power supply protection, in: Proceedings of the EOS/ESD Symposium, 1995, p.1. [5] S. Servaes, B. Keppens, ESD characterization of IC’s—Transmission line pulser, Industrial Engineering Thesis, 1996.
Journal of Electrostatics 59 (2003) 179–192
High ESD performance, low power CMOS LNA for GPS applications$ Paul Lerouxa,*, Vesselin Vassileva,b, Michiel Steyaerta, Herman Maesa,b a
K.U. Leuven, Department of Electrical Engineering, ESAT-MICAS, Kasteelpark Arenberg 10, B-3001 Leuven-Heverlee, Belgium b IMEC, Kapeldreef 75, 3001 Leuven-Heverlee, Belgium
Received 6 November 2002; received in revised form 28 February 2003; accepted 10 March 2003
Abstract This paper describes the design of a high performance 0.25 mm CMOS low noise amplifier (LNA) for the global positioning system (GPS) operating at 1.57 GHz. The LNA features a 1.5 dB noise figure. The input ESD-protection is in the order of 3 kV HBM and the power consumption is only 6 mW. r 2003 Elsevier Science B.V. All rights reserved. Keywords: ESD protection; CMOS LNA; GPS
1. Introduction In the recent years, a lot of research has been performed on the possibility of using pure CMOS, rather than bipolar or BiCMOS technologies for RF-applications. An example of such an application is global positioning system (GPS). The performance specifications of high-end GPS receivers are quite severe, requiring designs with good sensitivity as well as low noise amplifiers (LNAs) with low noise figure and high gain. One of the main bottlenecks for introducing CMOS RF circuits to the market is their susceptibility to ESD. It is due to both gate oxide breakdown and junction degradation related problems, caused by the decreased oxide thickness and increased $
r 2002. Reprinted with permission, after revision, from Electrical Overstress/Electrostatic Discharge Symposium Proceedings, EOS-24, Charlotte, NC, USA, October 8–10, 2002. *Corresponding author. Tel.: +32-16321877; fax: +32-16321975. E-mail address: [email protected] (P. Leroux). 0304-3886/03/$ - see front matter r 2003 Elsevier Science B.V. All rights reserved. doi:10.1016/S0304-3886(03)00063-9
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doping levels in the scaled down technologies [1]. The ESD problems are further increased by the tight design window for the high performance RF circuits, not allowing large ESD devices to be used as protection elements [2]. Before CMOS LNAs can be introduced to the market they need to satisfy the ESD standard of minimum 2 kV HBM. This paper shows that it is possible to design an LNA with good RF-performance while providing good ESD-immunity. Most CMOS ESD-protection structures have parasitics that are detrimental for the LNA performance. They commonly feature two large clamping devices with a current limiting resistor in between. The resistance added at the input (up to a few hundred ohms), would be detrimental for the noise figure of the LNA. The introduced parasitic input capacitance also has a serious influence on the LNA performance. This influence will be explained briefly in the first section. The design and layout of the 1.57 GHz LNA are discussed in the following sections, together with the ESD and RF characterization results. 2. Design 2.1. LNA design considerations Fig. 1 depicts the input of an inductively degenerated, common source LNA. Consider first the ideal case where no parasitic input capacitance, Cp ; is present. VS and RS represent the signal source that feeds the LNA. This is the output of either the antenna or a bandpass channel select filter. In both cases the impedance of the source is 50 O. As a consequence the LNA input should be matched to 50 O in order to absorb as much signal power as possible and to avoid distortions in the filter characteristic due to incorrect termination. Since the common source amplifier ideally has no input resistance, only input capacitance, the source degeneration inductor LS provides an ‘artificial’ resistive input impedance equal to oT LS : The gate–source capacitance is tuned out by a gate inductor, Lg ; in order to create a purely resistive input.
Fig. 1. Influence of Cp on LNA performance.
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However, in real life, some parasitic input capacitance is always present. Part of it is coming from the input bonding pad, another part belongs to the gate–drain capacitance. A normal ESD-protection network adds even more capacitance to that. This capacitance, Cp ; increases the noise figure of the LNA and decreases its gain. It also places an upper bound on the attainable input impedance values. If oCp is too high, it even becomes impossible to obtain an input match without an external matching circuit. It is instructive to define two reference planes 1 and 2 and to look at the different impedance levels at these nodes. Looking towards the source at reference plane in Fig. 1, the gate sees an equivalent input resistance Req larger than 50 O, and a series inductance Leq slightly larger than Lg : They are given by [3] Req ¼
Leq ¼
RS ; o20 Cp2 R2s þ ð1 o20 Cp Lg Þ2 Lg Cp ðo20 L2g þ R2s Þ o20 Cp2 R2s þ ð1 o20 Cp Lg Þ2
:
The noise factor of the LNA may be shown to be approximately given by 2 2 o0 g adð1 jc2 jÞ o0 g 2 gm Req þ : F ¼1þ þ kgm Req or a oT a k
ð1Þ
ð2Þ
ð3Þ
Notice that the noise factor features a term directly proportional to gm Req ; coming from the classical drain noise, and a term inversely proportional to gm Req coming from the non-quasistatic noise. Due to the presence of Cp and hence, the higher value for Req ; the noise figure is primarily determined by the classical drain noise contribution. As the ESD-protection circuit even increases Cp ; Req becomes larger and the noise figure increases further. Cp also has an influence on power gain. In order to have a high power gain, a high squared output current (jiout j2 ) is required for a given available source power, Pav : Its value may be calculated as a function of Req : 2 oT Pav 2 ; ð4Þ jiout j ¼ o0 Req where Pav is the available input power from the antenna. Rin is the real part of the impedance, seen to the right of reference plane 2. It is equal to Req for a perfect input match. The power gain Gt is then given by Rload oT 2 : ð5Þ Gt ¼ 4 Req o0 If the value of Cp increases, Req becomes larger and the amount of output current decreases. Hence, a higher Cp implies a lower power gain. However this decrease in gain may be somewhat compensated by lowering the value of Rin ; i.e. by reducing the source degeneration inductance Ls : In our design, we targeted at an S11 of 12 dB.
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The dependence of the LNA linearity, characterized by its IIP3, on the VGS VT (Vgt ), technology and input matching is shown in the following equation: ! 4 Vgt ð1 þ YVgt Þ2 ð2 þ YVgt Þ IIP3½dBm E 16 þ 10 log 3 Y sffiffiffiffiffiffiffiffiffiffi! 50 O þ 20 log o0 Cgs ðReq þ Rin Þ : ð6Þ Req The first part of this equation is derived from the well-known MOS current equation under mobility degradation which is modeled by the factor Y: For a transistor without matching section (only the first term in (6)), the IIP3 improves with increasing VGS VT and deteriorates with deeper submicron technologies. For a matched transistor, the dependencies get more complex because the IIP3 decreases with decreasing equivalent source resistance (Req ). The 16 term converts the units from dBVamp to dBmav : 2.2. The 1.57 GHz LNA for GPS A simplified schematic of the circuit is shown in Fig. 2. The biasing details are not shown. The circuit uses the same topology discussed in the previous section. The input bonding wire is used as gate tuning inductor since the Q of an on-chip inductor would be too low resulting in a high noise figure. The input bonding pad is shielded from the substrate by grounding the bottom metal layer. This drastically increases the Q of the bond pad capacitance and prevents noise coupling from the substrate. Furthermore, the pad capacitance has been minimized by using only the top metal layer and octagonal layout. Limiting this capacitance was of extreme importance to create a sufficiently large headroom for the capacitance of the ESD devices. The details of the ESD-protection network will be discussed in the next section.
Fig. 2. Simplified LNA schematic.
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The source degeneration inductor, Ls ; is implemented as two parallel bonding wires. The load inductor, Ld ; is realized on chip. Its series resistance is depicted as Rs and its parasitic capacitance to the patterned ground shield beneath it, is included in C1 : C1 (together with the pad capacitance Cbp;out ) and bonding wire Lout constitute the output matching network for obtaining a 50 O output impedance. Eqs. (1)–(6) have been used to describe the design space of the LNA and to visualize the influence of the equivalent source resistance (Req ) and the transistor sizing on the noise figure, gain and linearity of the LNA. A higher value for Req is beneficial for the linearity but is bad for noise and gain performance. Since, for the GPS application, the latter constraints are more binding, Req is chosen sufficiently low. As Req increases with the amount of parasitic input capacitance (1) the capacitance available for the ESD-protection is limited. Moreover, the tolerated capacitance decreases with the operating frequency of the circuit. The LNA, operating at 1.57 GHz, has been simulated and optimized both with and without the ESD-protection diodes. Simulations were done with HSPICE. The MOS model that was used is level 49, BSIM3v3. Both the MOS transistors and the diodes were placed within a subcircuit to include extra parasitics that are not implemented in the BSIM3v3 model. This allowed us to model the Non-QuasiStatic effect of the channel charge buildup which has a significant influence on the RFperformance. We also included bulk and well resistances for both the diodes and transistors which influences both high-frequency and high-current behavior. The noise figure and power gain are plotted vs. the capacitance of the ESDprotection diodes in Fig. 3. The other contributors to the capacitance are also taken into account in these simulations but they are not included in the value of CESD : It is seen in this figure that the NF increases from 0.9 to 1.5 dB for a capacitance of 350 fF. The power gain decreases from 19.3 to 15.7 dB. Beyond this capacitance
Fig. 3. LNA noise figure and power gain as a function of ESD-capacitance.
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Table 1 Comparison between the simulated RF-performance of the LNA with and without input ESD-protection
Power consumption Current consumption Supply voltage S11 @ 1.57 GHz S21 @ 1.57 GHz S12 S22 @ 1.57 GHz NF @ 1.57 GHz IIP3
Without ESD-protection
With ESD-protection
9 mW 6 mA 1.5 V 14 dB 19.3 dB o30 dB 23 dB 0.9 dB 6.8 dBm
9 mW 6 mA 1.5 V 14 dB 18.4 dB o30 dB 25 dB 1.0 dB 5.1 dBm
value the circuit can no longer be matched to 50 O without an external matching network. For higher frequencies this effect becomes more pronounced, i.e. the curves will be steeper and the cut-off capacitance becomes lower. In our design the ESD diodes have a total capacitance of about 100 fF yielding ESD protection of 3 kV HBM. Table 1 shows a comparison between the main simulation results with and without ESD-protection. This table confirms the theoretical discussion given above. Adding the ESD-protection at the input reduces the power gain from 19.3 to 18.4 dB. The noise figure increases from 0.9 to 1 dB. The IIP3 improves from 6.8 to –5.1 dBm. All these effects are attributed to the increased parasitic input capacitance causing an increased value of the equivalent input impedance, Req : 2.3. ESD protection design considerations The ESD protection device network was designed as shown in Fig. 4. It consists of two diodes, D1 and D2, between the RF input and the power supply busses and of a stack of five diodes D3D7 between Vdd and Vss : The goal is to provide an explicit ESD discharge current path for all possible stress combinations between the input, Vdd and Vss : The use of diodes was based on the fact that they are very efficient and robust ESD devices. Furthermore, their characteristics are fairly simple to model and simulate, allowing a reliable sizing of these devices. Since the LNA was designed for a fully integrated GPS receiver, where the output node of the LNA directly connects to the mixer input, no output ESD-protection is required. Key considerations in the D1–D2 input diodes design is their capacitance, and their high frequency and high current resistance. The first two affect the RF performance of the LNA (as shown earlier), the second influences the ESD performance of the circuit and, in particular, the bias developed on the input node/gate of the LNA during the ESD pulse. Both the capacitance and the resistance should be kept at minimum, requiring suitable diode optimization. The diodes can be laid out as one finger or multiple finger devices. It is a wellknown fact that the junction capacitance of the diode is related mostly to the bottom
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Vdd
D1 D3-D7
in D2
Vss
Fig. 4. The p+n-well diode-based ESD protection network designed around the core RF-LNA circuit.
plate of the diode while the current flows mostly through the sidewall. Hence to minimize the capacitance and the resistance of the diode we need to minimize the area and maximize the perimeter. This clearly pleads in favor of a multiple finger structure. Moreover, a one finger diode may give current crowding at the corners, yielding dangerous hot spots where breakdown may initiate. To avoid this the diodes were implemented with several fingers. These fingers may be realized either as squares or stripes. Stripes give the advantage of a very low resistance since the average distance from a p+ to n+ contact is minimal while still providing sufficient contacts per finger. On the other hand, current crowding and the resulting hot spots may occur at the small ends of the stripes. This problem may be somewhat alleviated by removing the contact closest to the end of the stripe in order to increase the resistance in that path preventing current crowding. When using squares, the average resistance will be a little higher than with stripes but a uniform current distribution is more easily obtained. The chip discussed in this paper uses a multiple finger structure of square diodes. The area of the squares was chosen as small as possible while keeping more than one via for each square. The area of one diode square in our design is 9 mm2 giving a total area of 36 mm2 for a total capacitance of 50 fF per diode (one to Vdd and one to ground). The layout of the diodes is illustrated in Fig. 5. Simulation of the low frequency input capacitance Cin ; due to D1 and D2, as function of the applied DC input and Vdd biases is shown in Fig. 6. Since the value of Cin is relatively constant around the DC operating point, it does not significantly degrade the linearity of the circuit. The design of the diode string D3–D7 between the supply rails was done based on the Vdd to Vss leakage current specifications and the small high current resistance requirements. In an n-well CMOS technology a p+n-well diode is actually a pnp transistor [4]. Hence, when you connect a series of diodes and some current is injected in the top diode, the current through the next diode is reduced by a factor 1 þ b; where b is the current amplification of the parasitic bipolar transistor. As a consequence the chain of diodes will start to conduct at a voltage which is lower than the sum of their individual cut-in voltages. This necessitates that sufficient diodes are connected in series such that the current leakage at the operating supply voltage remains negligible. Since N diodes in series are needed and the on-resistance of the
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Fig. 5. Layout of the input protection diodes.
Fig. 6. The simulated input capacitance contribution of D1 and D2 as a function of the applied input DC bias.
clamp should be lower than the on-resistance of the input diodes, these diodes are sized at least n times larger than the input diodes. In this way, the supply clamp withstands higher ESD-stress than the input diodes ensuring that the latter is the limiting factor in the ESD-performance. The increased capacitance of the diode string is not a problem since it just adds to the on-chip decoupling capacitance and does not influence the RF performance. As illustrated in Fig. 7, the diodes in the clamp consist of a multiple finger structure comparable to the input diodes. In this example, three diodes are connected
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Fig. 7. Layout of the supply clamp.
Fig. 8. TLP results for three stress combinations on the nodes, see Fig. 3. The plot represents both the high current device IV characteristics IESD ¼ f ðVdev Þ and the leakage current between the stressed pins, Ileakage ¼ f ðIESD Þ: The jump in Ileakage indicates the ESD failure threshold level. The TLP reverse breakdown characteristic of D2 is also shown.
in series and each diode consists of three fingers. On the chip, however, five diodes are connected in series based on the leakage current specification for a supply of up to 2 V. Each diode therefore consists of twenty fingers which are interconnected with metal.
3. Measurement results 3.1. ESD-protection results Fig. 8 represents the measured Transmission Line Pulse (TLP) characteristics of the LNA circuit for three different stress combinations: INPUT to VDD ; INPUT to
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Table 2 Comparison between the achieved TLP and HBM thresholds for the major pin stress combinations. The other possible stress polarities thresholds can be represented by these results as well. The HBM results stem from a separate on-wafer HBM test Stress polarity þ
IN VDD INþ VSS þ VSS VDD þ VSS VDD
TLP: It2 [A]
HBM: VHBM [V]
1.67 1.62 3.2 4.2
3.2 k 3.2 k >4 k >4 k
VSS and VDD to VSS : For the TLP characterization, a home built 500 O system was used, having 100 ns fixed pulse length, 700 ps pulse rise time, and providing current amplitudes from 5 mA to 4A [5]. The results show that the TLP ESD robustness of the input diodes is of about 1.67 A which corresponds to 2.5 kV Human Body Model (HBM) ESD stress. The diode resistance may be calculated by taking the derivative of Vdev ; the voltage over the ESD-protection device, to the current through the device, IESD : For the input diodes, it is in the order of 2 O. The ESD robustness of the D3–D7 diode stack is B3.25 A, corresponding to B4.9 kV HBM stress and total resistance also in the order of 2 O. The correlation of the TLP results to the HBM performance is for a first-order evaluation only and is done by transforming the TLP It2 current through the 1.5 kO HBM model resistance. Fig. 8 also shows that the IN+ to VDD is more robust than VDD 2VSS : The reason is that in the first case, the ESD current gives only a voltage drop over D1 yielding a reverse voltage divided over six diodes (D2–D7). In the latter case, the ESD current gives a voltage drop over 5 forward diodes (albeit larger ones) which is divided over only 2 smaller reverse diodes, D1 and D2. This will initiate reverse breakdown sooner. Table 2 presents the ESD thresholds, achieved from the actual separate on wafer HBM testing. The worst case ESD stress combination for the circuit is when it is stressed between the input and ground nodes. In this case, the ESD current flows from the input pad through D1, the Vdd bus, the D3–D7 stack and the Vss bus to the Vss output pad. The overall ESD robustness in this case is determined by the lowest of the ESD thresholds of the different components in the current path: D1, D3–D7, the reverse breakdown of D2 and the ESD robustness of the input gate of the LNA. The measured ESD TLP threshold in this case was 1.62 A. The results for the other major stress combination are represented in Table 2. Implementing ESD circuit simulations, one can additionally study and optimize the protection network operation by monitoring the currents and bias developed on the circuit nodes. Fig. 9 represents some results from such a first order 3 kV HBM HSPICE simulation when the stress was applied between the input and the Vss pads. An HBM tester model calibrated to a standard HBM test system and high-current diode models, calibrated to the stand-alone device actual TLP performances were used in the simulations. The rest of the LNA circuit was simulated using the standard, non-ESD HSPICE models. It is justified by the fact that, for these HBM
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Fig. 9. Simulation of 3 kV HBM stress between the input and Vss circuit nodes. The currents through the diodes and the bias developed on the input and Vdd pads are shown.
simulated ESD stress levels, no other core-circuit devices showed to be biased above their nominal operation regime. From the simulation results shown in Fig. 9 one can see that, although most of the HBM current (ID1 B1:6 A) goes through D1 and D3–D7 chain to ground, still significant amount of stress current (ID2 ) goes through D2, operating in reverse breakdown. Knowing the TLP thresholds of the diodes in the different operating modes, it becomes possible to evaluate by simulations the maximum HBM level the diode protection network can survive. Comparing Fig. 9 with Fig. 8 shows that the most likely failure for the circuit in this test is the reverse breakdown of D2, since it is only able to carry about 200 mA in reverse operation. However, it should be noted that simulation of the diode in reverse was not very accurately modeled and the real current through the reverse diode is significantly lower as can also be seen in Fig. 8. Another possible danger for the circuit at higher HBM stress levels, is also indicated in Fig. 9. Increasing the level of the applied ESD stress current will further increase the bias developed on the Vdd bus, above the level of 8–9 V the typical breakdown voltage of the NMOS devices for this particular technology. This will cause snapback and possible degradation of the core RF devices attached to Vdd : It is also seen, that, for this stress level, the bias VIN ; developed on the input pad, is lower than the transient gate oxide breakdown voltage which is typically above 20 V for the given technology generation. Hence, it is unlikely that the ESD failure of the circuit will be caused by the input gate oxide breakdown.
3.2. RF measurement results The LNA has been implemented in a standard 0.25 mm 4M1P CMOS process. It occupies an area of 0.73 mm2. A photograph of the IC is shown in Fig. 10.
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Fig. 10. Micrograph of the LNA.
Fig. 11. Measured power gain and input reflection of the LNA.
For the RF measurements, the LNA is glued on a ceramic substrate and is wire bonded to 50 O strip-lines. The substrate is than mounted in a Copper-Beryllium box which serves as a reference ground. The LNA is biased in two operating regimes drawing 4 and 6 mA from a 1.5 V supply. The complete S-parameter set has been measured using an HP network analyzer. The power gain, S21, is plotted in Fig. 11 for both operating regimes. The maximum power gain at 1.57 GHz is 15.5 and 16.5 dB, respectively. This figure also shows the input reflection of the circuit: S11 is 12 and –13 dB, respectively. The reverse isolation (S12) is measured to be larger than 30 dB throughout the entire range of the network analyzer (300 kHz–3 GHz). The output reflection, S22 is 14 dB. Fig. 12 depicts the measured noise figure for both operating regimes. At 6 mW power consumption, the LNA has a NF of 1.5 dB at 1.57 GHz. In the 9 mW regime the NF is 1.3 dB.
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Fig. 12. Measured Noise Figure of the LNA.
Fig. 13. Measured LNA output power for a two tone test.
The input referred IP3 is 7 and 5 dBm, respectively, for the 6 and the 9 mW bias regime. Fig. 13 shows the measured output power vs. input power for a two tone test in the 6 mW regime. The squares indicate the power of the fundamental signal, the circles indicate the power of the intermodulation terms. The intercept point is at 7 dBm input power. A summary of the RF-performance is given in Table 3. 4. Conclusion This work shows that, even in a standard submicron CMOS technology, a high RF-performance may be combined with a good level of ESD-protection satisfying
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Table 3 Summary of the measured RF-performance of the LNA
Power consumption Current consumption Supply voltage S11 @ 1.57 GHz S21 @ 1.57 GHz S12 S22 @ 1.57 GHz NF @ 1.57 GHz IIP3
Bias condition A
Bias condition B
6 mW 4 mA 1.5 V 12 dB 15.5 dB o30 dB 14 dB 1.5 dB 7 dBm
9 mW 6 mA 1.5 V 13 dB 16.5 dB o30 dB 14 dB 1.3 dB 5 dBm
the industrial specification of 2 kV HBM. This has been demonstrated with a competitive LNA with a low noise figure of 1.5 dB and a gain of 15.5 dB at a very low power consumption of 6 mW. The ESD-protection network at the RF input and the supply clamp yield a protection level of over 3 kV HBM.
Acknowledgements The authors would like to thank Kawasaki Microelectronics Inc. for processing the circuit.
References [1] A. Amerasekera, et al., Analysis of snapback behaviour on the ESD capability of sub-20um NMOS, in: Proceedings of the IRPS 99, 1999, pp. 159–166. [2] M. Radhakrishnan, et al., ESD reliability issues in RF CMOS circuits, in: Proceedings of the IWPSD 2001, International Workshop on the Physics of Semiconductor Devices, December 2001. [3] P. Leroux, J. Janssens, M. Steyaert, A 0.8 dB NF ESD-protected 9 mW CMOS LNA operating at 1.23 GHz, in Journal of Solid State Circuits, June 2002, pp. 760–765. [4] T.J. Maloney, S. Dabral, Novel clamp circuits for IC power supply protection, in: Proceedings of the EOS/ESD Symposium, 1995, p.1. [5] S. Servaes, B. Keppens, ESD characterization of IC’s—Transmission line pulser, Industrial Engineering Thesis, 1996.