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High figure-of-merit SOI power LDMOS for power integrated circuits
Engineering Science and Technology, an International Journal 18 (2015) 141e149
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High figure-of-merit SOI power LDMOS for power integrated circuits Yashvir Singh*, Rahul Singh Rawat Department of Electronics & Communication Engineering, G. B. Pant Engineering College, Pauri Garhwal, Uttarakhand 246 194, India
a r t i c l e i n f o
a b s t r a c t
Article history: Received 4 August 2014 Received in revised form 18 October 2014 Accepted 18 October 2014 Available online 5 December 2014
The structural modifications in the conventional power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS) are carried out to improve the breakdown voltage, on-resistance, gatecharge and figure-of-merits of the device with reduced cell pitch. The modified device has planer structure implemented on silicon-on-insulator which is suitable for low to medium voltage power integrated circuits. The proposed LDMOS consists of two gate electrodes placed vertically in two separate trenches build in the drift region and single source and drain contacts are taken on the top. The trench structure reduces the electric field inside the drift region and allow increased drift layer doping concentration leading to higher breakdown voltage, lower specific on-resistance, reduced gate-drain charge, and substantial improvement in the figure-of-merits. Using two-dimensional simulations, the performance of the proposed LDMOS is optimized and results are compared with the conventional LDMOS. Our simulation results show that the proposed device exhibits 110% higher breakdown voltage, 40% reduction in cell pitch, 19% lower specific on-resistance, 30% lower gate-to-drain charge leading to 5.5 times improvement in Baliga's figure-of-merit and 43% reduction in dynamic figure-of-merit over the conventional device. Copyright © 2014, The Authors. Production and hosting by Elsevier B.V. on behalf of Karabuk University. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/bync-nd/3.0/).
Keywords: Power LDMOS SOI Breakdown voltage On-resistance Figure-of-merit
1. Introduction The power integrated circuits (PICs) have gained importance due to their advantages of small size, low cost, less power consumption, and increased reliability. The PICs operating in low to medium voltage range (60e100 V) are used in many applications [1e4] such as automotive electronics, light-emitting diode drivers, plasma display panels, PC peripheral, and portable power management products. For fabricating PICs, silicon-on-insulator (SOI) technology is a preferred choice because it provides superior isolation between various devices on the chip. In such circuits, the key power device is laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS). A power LDMOS is designed to achieve higher breakdown voltage while minimizing specific onresistance in order to reduce conduction losses. The specific onresistance (RON) is defined as the product of total on-resistance and area of the device. Both the breakdown voltage (VBR) and the on-resistance of SOI LDMOS are dependent on the length and doping of the drift region. A long drift region length and low doping
* Corresponding author. E-mail address: [email protected] (Y. Singh). Peer review under responsibility of Karabuk University.
is required to achieve high breakdown voltage in a conventional LDMOS (CLDMOS) which unfortunately, increases the on-resistance of the device. Conversely, a shorter drift region length with higher doping reduces the on-resistance but adversely affects the breakdown voltage. Therefore, there is always a trade-off between the breakdown voltage and the on-resistance. One measure of this 2 =R trade-off is the Baliga's figure-of-merit (BFOM ¼ VBR ON ) which should be as high as possible for a better designed LDMOS. For PICs applications, it is also important to estimate the switching performance of an LDMOS. In order to reduce the switching losses, the gate-charge in general and the gate-to-drain charge (Qgd) in particular should be minimized for a given on-resistance. The switching performance of an LDMOS is evaluated by dynamic figure-of-merit (FOM ¼ RON.Qgd). For improving the static and dynamic performance of a CLDMOS, several modifications in the conventional design have been reported [5e9] by incorporating the trench structures in the drift region. These devices have successfully demonstrated to achieve low on-resistance and high breakdown voltage by increasing the drift region doping while reducing the electric field inside the drift region. Furthermore, a lower cell pitch of the device is desirable to get cost advantage with increased packaging density of PICs. A lateral trench gate LDMOS structure was reported [8] which utilized a trench for channel formation in the drift layer on SOI and
http://dx.doi.org/10.1016/j.jestch.2014.10.004 2215-0986/Copyright © 2014, The Authors. Production and hosting by Elsevier B.V. on behalf of Karabuk University. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/3.0/).
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achieved a BFOM of 6.68 MW/cm2 with a cell length of 6 mm. Another trench-gate LDMOS was proposed [9] on thin SOI consisting of two trenches in the drift region on both sides of the pbody region. This device is demonstrated to have a BFOM of 12.87 MW/cm2 for a cell pitch of 5 mm and also provides significant improvement in switching performance. In this structure, further reduction in the cell pitch of the LDMOS was limited by the lateral dimensions of the device due to the dual drain contacts symmetrically placed on both sides of the trench-structure. In order to improve the BFOM with reduced cell pitch, we propose a trenchgate LDMOS structure called TGLDMOS in which two trenches are created in the drift region on both side of p-body where gate electrodes are placed. The unit cell of the device contains only single drain and source contacts and hence provides a reduction in cell pitch. Based on two-dimensional simulations, it is demonstrated that the proposed structure provides a BFOM of 22.40 MW/ cm2 with a reduced cell pitch of 3 mm while maintaining a good switching performance. 2. Device structure The schematic cross-sectional views of the conventional and proposed LDMOS structures implemented on thin SOI are shown in Fig. 1. Both the devices have Nþ-polysilicon gates with identical gate
LG
Gate LFP
Source P
+
N
Drain
t ox +
P
1
LD
A
2
N
+
t epi
N −Drift t BOX
BOX (a)
Substrate L Gate
tox1 Gate tox2
Source N+ P + LG P B 3
N+ tox3
N −Drift
N+
5
t ox
4
tox4
Drain
L1
C 6 L2
tepi
td tBOX
BOX (b)
Substrate L SiO2
+
N Poly
length of 0.5 mm. As shown in Fig. 1(a), the CLDMOS is a planer device with gate, source and drain contacts on the top of the structure. When a positive gate voltage higher than threshold voltage is applied, a channel is formed in the p-body region under the gate and current flows from drain to source for positive drain voltage. Under off-state, the gate is shorted to the source and applied positive drain voltage causes spreading of depletion region in the N-drift layer. The breakdown of the device occurs when the electric field inside the drift region reaches the critical field of the material. The gate electrode is extended over the drift region to act as field-plate which reduces the electric field on the silicon surface and improves the breakdown voltage. However, the electric field still peaks on the surface at the end of field-plate (point ‘A’) which limits further improvement in the breakdown voltage. It may be noted that the length of field-plate is among the critical parameters which affect breakdown voltage. At a drift region doping of 2 1016 cm3, the optimized structural parameters of the CLDMOS are listed in Table 1. The total cell pitch of the conventional device is 5 mm. On the other hand, as shown in Fig. 1(b), the proposed TGLDMOS structure has two trenches filled with oxide in the Ndrift region on both sides of P-body region. The gate electrodes are symmetrically placed in both the trenches and gate polysilicon is extended over the drift region to work as vertical field-plate. Two channels are formed simultaneously in the P-body along the sidewalls of trenches when a positive gate voltage is applied and current flows from the drain to source through the bulk of drift region for positive drain voltages. The presence of two trenches substantially reduces the electric field in the drift region [10]. The trenchstructure causes the reduced-surface field (RESURF) effect which leads to full depletion of the drift region resulting large improvement in the breakdown voltage of the proposed device. At breakdown, the peak electric field occurs at point ‘C’ in the TGLDMOS. It is noteworthy that the TGLDMOS structure reported in [8] has a deep Pþ-sinker, spacing between the trench gate and Nþ-drain diffusion, and a source field-plate over the trench gate and the drift region. These structural modifications limit the lateral dimensions and hence restrict the further reduction in the cell of the device. On the other hand, the proposed TGLDMOS unit cell contains single drain and source contacts and two gates placed vertically in separate trenches without any horizontal field-plate leading to reduced cell pitch of the device. Moreover, the trench structure folds the drift region in vertical and horizontal directions leading to reduced cell pitch of 3 mm. The optimized device design allow higher drift layer doping of 3 1016 cm3 in the TGLDMOS. The breakdown voltage and on-resistance of the proposed structure are affected by
Silicon
Metal
Fig. 1. A schematic cross-sectional view of the unit cell of the (a) CLDMOS (b) TGLDMOS.
Table 1 Optimized parameters of the CLDMOS and TGLDMOS. Parameter
Unit
CLDMOS
TGLDMOS
Cell pitch, L Gate length, LG Field-plate length, LFP Drift region length, LD Drift region length 1, L1 Drift region length 2, L2 Gate oxide thickness, tox Oxide thickness, tox1 Oxide thickness, tox2 Oxide thickness, tox3 Oxide thickness, tox4 Epitaxial layer thickness, tepi Drift region thickness, td Buried oxide thickness, tBOX Drift region doping, Nd P-body doping
mm mm mm mm mm mm mm mm mm mm mm mm mm mm
5.00 0.50 1.50 2.10 e e 0.03 e e e e 0.60 e 0.60 2 1016 8 1016
3.00 0.50 e e 1.22 0.60 0.03 0.18 0.64 0.30 0.25 2.25 0.60 0.70 3 1016 8 1016
cm3 cm3
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3. Comparison of simulated results To understand the effect of structural parameters on the performance of the CLDMOS and TGLDMOS devices, we have created both the structures in the device simulator (ATLAS) [12]. Twodimensional numerical simulations were carried out by invoking suitable models in the simulator such as Shockley-Read-Hall model (SRH), Fermi-Dirac model (FERMIDIRAC), concentration dependent mobility model (CONMOB), electric-field-dependent mobility model (FLDMOB), and the Selberherrs impact ionization model (IMPACT SELB). Using the identical simulation models and their parameters for both the structures, the simulated characteristics are compared to evaluate their performance as discussed below: 3.1. ON-resistance Fig. 2 shows the simulated drain characteristics of the CLDMOS and TGLDMOS at gate-source voltage (VGS) of 6 V for low values of drain-source voltages (VDS) such that the devices operate in the linear region. These characteristics are used to determine the onresistance of the devices. The total on-resistance of an LDMOS is a series combination of channel resistance, drift region resistance, drain and source contact resistances. From Fig. 2, the total onresistance is calculated as the ratio of drain voltage to drain current and is multiplied by the pitch length to get the specific onresistance (RON). The specific on-resistance of the CLDMOS and TGLDMOS are found to be 52 and 42 mU-mm2, respectively resulting 19% reduction in RON for the proposed device. It may be noted that although, the drain current in the TGLDMOS is lower than that of the CLDMOS but the reduced pitch length leads to smaller RON. Fig. 3 shows the variation of specific on-resistance with
2 1
0
0.1
0.2 0.3 0.4 Drain Voltage, VDS (V)
0.5
Fig. 2. Drain characteristics of the CLDMOS and the TGLDMOS in the linear region for VGS ¼ 6 V.
2
4 3 5 Gate Voltage, VGS (V)
6
Fig. 3. Specific on-resistance variation with applied gate-source bias for the CLDMOS and TGLDMOS.
the gate-source bias for the CLDMOS and the TGLDMOS. Initially, as VGS is increased, the on-resistance of both the devices decreases rapidly because of enhancement in the channel conduction. As VGS is further increased, the on-resistance saturates to a particular value indicating that the channel is fully created and the onresistance is mainly limited by the drift region resistance. We observe that for entire range of VGS, the proposed device exhibits lower RON as compared to the conventional device. The threshold voltage of the TGLDMOS (1.34 V) is found to be close to that of the CLDMOS (1.58 V). The substrate of both the devices is kept at grounded potential (0 V).
3.2. Breakdown voltage The simulated breakdown characteristics of the TGLDMOS compared with that of the CLDMOS under off state are shown in Fig. 4. At zero gate bias, there is no path for conduction of electrons
2.5
3
0
50
0 1
TGLDMOS CLDMOS
4
TGLDMOS CLDMOS
100
Drain Current, ID (mA/mm)
Drain Current, ID (mA/mm)
5
150 ON−Resistance, (mΩ−mm2 )
various structural parameters whose optimized values are given in Table 1. Note that the proposed device provides 40% reduction in the cell pitch as compared to the CLDMOS. This will result a lower area of fabrication as the drift region resistance is reduced. The proposed TGLDMOS device may be fabricated using a process as reported for other trench-gate structures [10,11]. The TGLDMOS structure requires few additional fabrication steps as compared to the conventional device.
143
TGLDMOS CLDMOS
2.0 1.5 1.0 0.5 0
0
20
80 60 40 Drain Voltage, VDS (V)
100
Fig. 4. Off-state breakdown characteristics of the CLDMOS and TGLDMOS.
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Fig. 5. Two-dimensional electric field distribution in the drift region of the (a) CLDMOS and (b) TGLDMOS at VDS ¼ 35 V.
from source to drain because the channel is not created in P-base. This results in a normally-off device with the drain voltage mostly supported by the N-drift region. The breakdown voltage is taken as drain to source voltage at which drain current exceeds 0.1 mA/mm. As seen, the breakdown voltage of CLDMOS and TGLDMOS structures are 46 and 97 V, respectively resulting 110% improvement in the breakdown voltage. In order to understand such large enhancement in the breakdown voltage, it is useful to examine the electric field profile inside the drift region of both the devices. Fig. 5 shows the two-dimensional electric field distribution in the drift region of the CLDMOS and TGLDMOS at VDS ¼ 35 V. As seen from the Fig. 5(a), in case of the conventional device, the electric field is crowded on the silicon surface at the end of field-plate (point ‘A’). On the other hand, for the proposed structure, the maximum electric field occurs at the bottom edge of the trench (point ‘B’). In order to know magnitude of maximum electric field in the drift region of two devices, Fig. 6 gives the electric field variation along the horizontal cut line (1e2 in Fig. 1(a)) located on the top surface of
drift region in the CLDMOS and along the cut line (3e4 in Fig. 1(b)) at the bottom edges of two trenches in the TGLDMOS at VDS ¼ 35 V. As seen, the peak electric field in the proposed structure is significantly lower than that in the conventional device leading to higher breakdown voltage of the TGLDMOS. It is apparent that in case of the proposed device, the charge increases from source to drain with the applied voltage which modulates the electric field in the drift region resulting enhanced breakdown voltage. Fig. 7 illustrates a two-dimensional view of the electric field in the CLDMOS and the TGLDMOS when the applied drain-source voltage is equal to their breakdown voltages. As seen, the peak of electric field remains at point ‘A’ in the conventional device whereas it shifts to point ‘C’ in the proposed device. The peak electric fields at these points can be seen in Fig. 8 which gives the electric variation along the horizontal cut line 1-2 in the CLDMOS and the vertical cut line 5e6 (as in Fig. 1(b)) along the side-wall of trench near the drain. As seen, the peak electric fields in both structures are equal which verify the breakdown of the CLDMOS and TGLDMOS at point ‘A’ and ‘C’,
Y. Singh, R.S. Rawat / Engineering Science and Technology, an International Journal 18 (2015) 141e149
0.8
0.2
merit (BFOM) for the CLDMOS and TGLDMOS is calculated as 4.07 and 22.40 MW/cm2, respectively. This provides 5.5 times improvement in the BFOM of the proposed device as compared with the conventional device. Further, the dynamic losses figure-ofmerit (FOM ¼ RON.Qgd) of the TGLDMOS structure is found to be 26 mU-nC as compared to 46 mU-nC of the CLDMOS resulting 43% reduction in FOM. A comparison summary of static and dynamic performance of the proposed device with that of the other reported SOI LDMOS devices is given in Table 2. The proposed TGLDMOS structure exhibits significantly higher BFOM than the other counterparts, which demonstrates better suitability of the proposed device for low to medium voltage power applications. The switching performance of the proposed TGLDMOS is comparable to that of the LTDGMOS [9].
0.1
4. Device optimization
TGLDMOS CLDMOS
0.7 Electric Field, (MV/cm)
145
VDS =35V
0.6 0.5
A
0.4 B
0.3
0
0
0.5
1 2 1.5 Distance, (µm)
2.5
3
Fig. 6. Electric field variation in the drift region of the CLDMOS along cut line 1e2 and the TGLDMOS along cut line 3e4 at VDS ¼ 35 V.
respectively. It is noteworthy that the maximum electric field in the TGLDMOS occurs below the semiconductor surface (away from the dielectrics) which typically yields higher critical electric field strength. 3.3. Gate charge analysis Gate charge (Qg) is the amount of charge required on the gate to turn on the LDMOS for a given on-resistance. This gives an estimation of switching performance of the device. In order to minimize the switching losses of a power LDMOS, the gate charge should be as low as possible. Fig. 9 shows the gate charge curves of the TGLDMOS and the CLDMOS devices. These characteristics are obtained using mixed mode simulations in the device simulator. The circuit used to perform the gate-charge transient is given in the inset of this figure. In these simulations, the device width is kept 4000 mm for both the structures. As seen, for a given VGS, the total Qg of the TGLDMOS is lower than that of the CLDMOS. Moreover, the gate-to-drain charge (Qgd) is taken as the amount of charge that must be input to overcome the “Miller” effect as the drain voltage falls. This occurs during the plateau of the VGS waveform where the voltage is constant. From Fig. 9, the Qgd of the proposed TGLDMOS and CLDMOS devices are found to be 0.62 and 0.88 nC/mm2, respectively. The proposed device gives 30% lower Qgd as compared to the conventional device. This reduction in Qgd is due to lower gate-to-drain capacitance (Cgd) of the proposed device when compared to the CLDMOS as shown in Fig. 10. The CLDMOS structure exhibits higher value of Cgd due to presence of a gate field-plate over the drift region with thin oxide (tox) whereas the TGLDMOS device has thicker oxides (tox2 & tox3) between the gate and the drift region resulting lower Cgd. 3.4. Figure-of-merit In the previous subsections, it is observed that the TGLDMOS not only provides lower specific on-resistance but also enhances the breakdown voltage. This indicates that the performance of the TGLDMOS is superior to that of the CLDMOS and yields conditions for a better trade-off between the breakdown voltage and specific on-resistance. From our simulation results, the Baliga's figure-of-
In this section, we will investigate the effect of physical parameters on the performance of the TGLDMOS structure. The breakdown voltage and on-resistance are influenced by various device parameters such as the drift region concentration (ND), length of drift region (L2), drift region thickness (td), the epitaxial layer thickness (tepi), and the oxide thickness (tox2, tox3, tox4). These parameters are optimized in such a way that the device provides optimal trade-off between the breakdown voltage and the specific on-resistance resulting maximum BFOM. The dependence of the breakdown voltage and BFOM on the doping concentration of drift layer in the TGLDMOS is given in Fig. 11. As the doping concentration increases, the breakdown voltage of the structure enhances due to spreading of the depletion layer over the entire drift region which causes reduction in electric field inside the device. In other words, full depletion of the whole drift region is responsible for higher breakdown voltage. This is due to RESURF effect caused by the presence of trenches in the drift region. However, as the drift layer doping is increased above 3 1016 cm3, the drift region is not fully depleted at the drain side and causes an increased electric field inside the device leading to a rapid drop in breakdown voltage. The structure provides maximum BFOM at an optimum doping of 3 1016. Fig. 12 shows the effect of drift region length (L2) on the breakdown voltage and figure-of-merit. It is observed that the breakdown voltage of the device decreases as L2 is varied from 0.40 to 0.85 mm due to increase in the peak electric field at trench bottom. However, the onresistance of the structure is reduced marginally due to increase in cross-sectional area for flow of the drain current. This leads to an optimum BFOM for a length of 0.6 mm. In the next step, we have optimised the drift region thickness (td) by analysing its influence on the breakdown voltage and figure-of-merit as shown in Fig. 13. It can be seen that the breakdown voltage decreases slowly for variation of td from 0.20 to 0.65 mm and reduces rapidly thereafter. This is due to change in the electric field distribution in the device with td. This thickness also affects the on-resistance of the device due to change in drift region resistance. The optimized value of td is obtained as 0.6 mm corresponding to maximum BFOM. Fig. 14 gives a trade-off between the breakdown voltage and onresistance for change in epitaxial layer thickness (tepi) of the TGLDMOS. Keeping the td & tox3 fixed, the variation in tepi scales the length of vertical field-plate (the downward extension of the gate-polysilicon). The breakdown voltage of the structure improves as tepi is increased from 1.6 to 2.6 mm and saturates to a maximum value for further increase in tepi. On the other hand, the on-resistance is also affected by tepi resulting a significant improvement in the BFOM for increase in tepi from 1.6 to 2.25 mm. However, the performance of device degrades after 2.25 mm as optimum value of tepi. The other key dimensions of the structure
Fig. 7. Two-dimensional electric field distribution at breakdown voltage in the drift region of the (a) CLDMOS and (b) TGLDMOS.
5 TGLDMOS CLDMOS At breakdown
Gate Voltage, VGS (V)
Electric Field, (MV/cm)
1.5
1 C
A
0.5
0
0
0.5
2 1.5 1 Distance, (µm )
2.5
3
Fig. 8. Electric field variation in the drift region of the CLDMOS along cut line 1e2 and the TGLDMOS along cut line 5e6 at breakdown voltage.
4 3
10 V 100 μA CGD 10 μA
C GS
2 1 0 0
CLDMOS TGLDMOS
0.4
0.8
1.2
1.6
Gate Charge, Qg /AA (nC/mm2)
2.0
Fig. 9. Gate-charge characteristics of the TGLDMOS and CLDMOS.
140
CLDMOS TGLDMOS
120
−15 10
−16 10
5
0
15
10
20
Breakdown Voltage FOM
25
Drain Voltage, VDS (V)
147
40 35 30
100
Figure of Merit, (MW/cm 2)
−14 10
Breakdown Voltage, (V)
Gate−Drain Capacitance (F/µ m)
Y. Singh, R.S. Rawat / Engineering Science and Technology, an International Journal 18 (2015) 141e149
25 80
20 60
15
40
10
20
5
0
0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Drift Region Length, L2 (µ m)
Fig. 10. Gate-drain capacitance of the TGLDMOS and CLDMOS.
Fig. 12. Breakdown voltage and figure-of-merit variation with drift region length (L2) of the TGLDMOS.
Breakdown Voltage FOM
25
80
20
60
15
40
10
20
5
0
breakdown voltage on tox2, tox3, and tox4 are illustrated in Figs. 15e17, respectively. It may be noted that the on-resistance of the device is not affected by these dimensions and hence the trends of BFOM curves are same as that of the breakdown voltage. Simulation results show that the optimum values of oxide thickness are tox2 ¼ 0.65 mm, tox3 ¼ 0.30 mm, tox4 ¼ 0.25 mm. It is to be pointed out that the variation in the oxide thickness, tox1 does not affect the breakdown voltage and the on-resistance of the TGLDMOS. However, the gate-source capacitance increases by reducing the tox1 thickness. The optimised values of all parameters are given in Table 1 which are used in simulations to compare the performance of the proposed device with that of the conventional counterpart.
0
0
1
2
3
5
4
6
7
140
16
Doping, ND (x10 cm 3 )
affecting the breakdown voltage are the oxide thickness tox2, tox3, and tox4. These parameters modulate the electric field distribution inside the device and maximum breakdown voltage is achieved for an optimum value of parameters so that the electric field profile in the device becomes more uniform. Dependence of the
Table 2 Performance comparison of power LDMOS devices. Device structure
VBR (V)
RON (mU-cm2)
BFOM VBR2/ RON (MW/cm2)
Qgd nC/cm2
FOM Qgd.RON (mUenC)
CLDMOS TGLDMOS [8] LTDGMOS [9] TGLDMOS (This work)
46.0 97.4 69.0 97.0
0.52 1.42 0.37 0.42
4.07 6.68 12.87 22.40
88 e 63 62
46 e 23 26
120 Breakdown Voltage, (V)
Fig. 11. Breakdown voltage and figure-of-merit as a function of drift region doping of the TGLDMOS.
Breakdown Voltage FOM
35 30 Figure of Merit, (MW/cm2)
Breakdown Voltage, (V)
100
Figure of Merit, (MW/cm 2 )
30
120
100
25
80
20
60
15
40
10
20
5
0
0
0.6 0.2 0.8 0.4 Drift Region Thickness, td (μm)
0 1.0
Fig. 13. Breakdown voltage and figure-of-merit variation with the drift region thickness (td) of the TGLDMOS.
Y. Singh, R.S. Rawat / Engineering Science and Technology, an International Journal 18 (2015) 141e149
140
Breakdown Voltage FOM
Breakdown Voltage, (V )
120 100
35 30 25
80
20
60 15 40 10
20
Figure of Merit, (MW/cm 2)
148
5 0 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 Epitaxial Layer Thickness, tepi (μ m) Fig. 14. Breakdown voltage and figure-of-merit variation with epitaxial layer thickness (tepi) of the TGLDMOS.
Fig. 16. Dependence of breakdown voltage and figure-of-merit on oxide thickness, tox3 of the TGLDMOS.
5. Conclusion
130
Breakdown Voltage, (V)
120 110
Breakdown Voltage FOM
50 45 40
100
35
90
30
80 70
25 20
60
15
50
10
40 30
5
Figure of Merit, ( MW/cm2 )
A power LDMOS structure on SOI is presented which utilizes two vertical gates placed in two trenches on both sides of P-base region. The proposed trench structure suppresses the electric field in the drift region and allow higher drift layer concentration with reduced pitch length leading to a superior performance in terms of maximum breakdown voltage, minimum specific on-resistance, reduced gate-charge, and higher figure-of-merits. Numerical simulations are used to analyse and evaluate the performance of the proposed device and results are compared with that of the conventional device. The device parameters such as drift region concentration (ND), drift region length (L2), drift region thickness (td), epitaxial layer thickness (tepi), and oxide thickness (tox2, tox3, tox4) are varied in order to see their influences on the device performance. These parameters are optimised to obtain maximum figureof-merit. Based on simulations results, it is demonstrated that the
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Oxide Thickness, t ox2 (µ m )
Fig. 15. Breakdown voltage and figure-of-merit variation with oxide thickness, tox2 of the TGLDMOS.
Fig. 17. Breakdown voltage and figure-of-merit variation with thickness, tox4 of the TGLDMOS.
proposed structure can provides 110% improvement in breakdown voltage, 19% reduction in specific on-resistance, 30% decrease in gate-to-drain charge and 40% lower cell pitch when compared with the conventional LDMOS. The Baliga's figure-of-merit of the proposed device is 22.40 MW/cm2 which is significantly higher than that of the other similar structures reported in literature. These improvements in the performance of the proposed device are achieved at the cost of few additional fabrication steps. Our results show that the proposed device is a suitable power LDMOS for power integrated circuits. References [1] M. Zitouni, F. Morancho, H. Tranduc, P. Rossel, J. Buxo, I. Pags, et al., A new lateral power MOSFET for smart power ICs: the LUDMOS concept, Microelectron. J. 30 (1999) 551e561.
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[8] I. Cortes, P.F. Martnez, D. Flores, S. Hidalgo, J. Rebollo, The thin SOI TGLDMOS transistor: a suitable power structure for low voltage applications, Semicond. Sci. Technol. 22 (2007) 1183e1188. [9] Y. Singh, M. Punetha, A lateral trench dual gate power MOSFET on thin SOI for improved performance, ECS J. Solid State Sci. Technol. 2 (2013) 113e117. [10] X. Luo, T.F. Lei, Y.G. Wang, G.L. Yao, Y.H. Jiang, K. Zhou, et al., Low onresistance SOI dual-trench-gate MOSFET, IEEE Trans. Electron Devices 59 (2012) 504e509. [11] N. Fujishima, A. Sugi, S. Kajiwara, Kunio Matsubara, Y. Nagayasu, C.A.T. Salama., A high-density low on-resistance trench lateral power MOSFET with a trench bottom source contact, IEEE Trans. Electron Devices 49 (2002) 1462e1468. [12] Atlas users manual, Device Simulation Software, Silvaco Int., Santa Clara, 2010.
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Full length article
High figure-of-merit SOI power LDMOS for power integrated circuits Yashvir Singh*, Rahul Singh Rawat Department of Electronics & Communication Engineering, G. B. Pant Engineering College, Pauri Garhwal, Uttarakhand 246 194, India
a r t i c l e i n f o
a b s t r a c t
Article history: Received 4 August 2014 Received in revised form 18 October 2014 Accepted 18 October 2014 Available online 5 December 2014
The structural modifications in the conventional power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS) are carried out to improve the breakdown voltage, on-resistance, gatecharge and figure-of-merits of the device with reduced cell pitch. The modified device has planer structure implemented on silicon-on-insulator which is suitable for low to medium voltage power integrated circuits. The proposed LDMOS consists of two gate electrodes placed vertically in two separate trenches build in the drift region and single source and drain contacts are taken on the top. The trench structure reduces the electric field inside the drift region and allow increased drift layer doping concentration leading to higher breakdown voltage, lower specific on-resistance, reduced gate-drain charge, and substantial improvement in the figure-of-merits. Using two-dimensional simulations, the performance of the proposed LDMOS is optimized and results are compared with the conventional LDMOS. Our simulation results show that the proposed device exhibits 110% higher breakdown voltage, 40% reduction in cell pitch, 19% lower specific on-resistance, 30% lower gate-to-drain charge leading to 5.5 times improvement in Baliga's figure-of-merit and 43% reduction in dynamic figure-of-merit over the conventional device. Copyright © 2014, The Authors. Production and hosting by Elsevier B.V. on behalf of Karabuk University. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/bync-nd/3.0/).
Keywords: Power LDMOS SOI Breakdown voltage On-resistance Figure-of-merit
1. Introduction The power integrated circuits (PICs) have gained importance due to their advantages of small size, low cost, less power consumption, and increased reliability. The PICs operating in low to medium voltage range (60e100 V) are used in many applications [1e4] such as automotive electronics, light-emitting diode drivers, plasma display panels, PC peripheral, and portable power management products. For fabricating PICs, silicon-on-insulator (SOI) technology is a preferred choice because it provides superior isolation between various devices on the chip. In such circuits, the key power device is laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS). A power LDMOS is designed to achieve higher breakdown voltage while minimizing specific onresistance in order to reduce conduction losses. The specific onresistance (RON) is defined as the product of total on-resistance and area of the device. Both the breakdown voltage (VBR) and the on-resistance of SOI LDMOS are dependent on the length and doping of the drift region. A long drift region length and low doping
* Corresponding author. E-mail address: [email protected] (Y. Singh). Peer review under responsibility of Karabuk University.
is required to achieve high breakdown voltage in a conventional LDMOS (CLDMOS) which unfortunately, increases the on-resistance of the device. Conversely, a shorter drift region length with higher doping reduces the on-resistance but adversely affects the breakdown voltage. Therefore, there is always a trade-off between the breakdown voltage and the on-resistance. One measure of this 2 =R trade-off is the Baliga's figure-of-merit (BFOM ¼ VBR ON ) which should be as high as possible for a better designed LDMOS. For PICs applications, it is also important to estimate the switching performance of an LDMOS. In order to reduce the switching losses, the gate-charge in general and the gate-to-drain charge (Qgd) in particular should be minimized for a given on-resistance. The switching performance of an LDMOS is evaluated by dynamic figure-of-merit (FOM ¼ RON.Qgd). For improving the static and dynamic performance of a CLDMOS, several modifications in the conventional design have been reported [5e9] by incorporating the trench structures in the drift region. These devices have successfully demonstrated to achieve low on-resistance and high breakdown voltage by increasing the drift region doping while reducing the electric field inside the drift region. Furthermore, a lower cell pitch of the device is desirable to get cost advantage with increased packaging density of PICs. A lateral trench gate LDMOS structure was reported [8] which utilized a trench for channel formation in the drift layer on SOI and
http://dx.doi.org/10.1016/j.jestch.2014.10.004 2215-0986/Copyright © 2014, The Authors. Production and hosting by Elsevier B.V. on behalf of Karabuk University. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/3.0/).
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achieved a BFOM of 6.68 MW/cm2 with a cell length of 6 mm. Another trench-gate LDMOS was proposed [9] on thin SOI consisting of two trenches in the drift region on both sides of the pbody region. This device is demonstrated to have a BFOM of 12.87 MW/cm2 for a cell pitch of 5 mm and also provides significant improvement in switching performance. In this structure, further reduction in the cell pitch of the LDMOS was limited by the lateral dimensions of the device due to the dual drain contacts symmetrically placed on both sides of the trench-structure. In order to improve the BFOM with reduced cell pitch, we propose a trenchgate LDMOS structure called TGLDMOS in which two trenches are created in the drift region on both side of p-body where gate electrodes are placed. The unit cell of the device contains only single drain and source contacts and hence provides a reduction in cell pitch. Based on two-dimensional simulations, it is demonstrated that the proposed structure provides a BFOM of 22.40 MW/ cm2 with a reduced cell pitch of 3 mm while maintaining a good switching performance. 2. Device structure The schematic cross-sectional views of the conventional and proposed LDMOS structures implemented on thin SOI are shown in Fig. 1. Both the devices have Nþ-polysilicon gates with identical gate
LG
Gate LFP
Source P
+
N
Drain
t ox +
P
1
LD
A
2
N
+
t epi
N −Drift t BOX
BOX (a)
Substrate L Gate
tox1 Gate tox2
Source N+ P + LG P B 3
N+ tox3
N −Drift
N+
5
t ox
4
tox4
Drain
L1
C 6 L2
tepi
td tBOX
BOX (b)
Substrate L SiO2
+
N Poly
length of 0.5 mm. As shown in Fig. 1(a), the CLDMOS is a planer device with gate, source and drain contacts on the top of the structure. When a positive gate voltage higher than threshold voltage is applied, a channel is formed in the p-body region under the gate and current flows from drain to source for positive drain voltage. Under off-state, the gate is shorted to the source and applied positive drain voltage causes spreading of depletion region in the N-drift layer. The breakdown of the device occurs when the electric field inside the drift region reaches the critical field of the material. The gate electrode is extended over the drift region to act as field-plate which reduces the electric field on the silicon surface and improves the breakdown voltage. However, the electric field still peaks on the surface at the end of field-plate (point ‘A’) which limits further improvement in the breakdown voltage. It may be noted that the length of field-plate is among the critical parameters which affect breakdown voltage. At a drift region doping of 2 1016 cm3, the optimized structural parameters of the CLDMOS are listed in Table 1. The total cell pitch of the conventional device is 5 mm. On the other hand, as shown in Fig. 1(b), the proposed TGLDMOS structure has two trenches filled with oxide in the Ndrift region on both sides of P-body region. The gate electrodes are symmetrically placed in both the trenches and gate polysilicon is extended over the drift region to work as vertical field-plate. Two channels are formed simultaneously in the P-body along the sidewalls of trenches when a positive gate voltage is applied and current flows from the drain to source through the bulk of drift region for positive drain voltages. The presence of two trenches substantially reduces the electric field in the drift region [10]. The trenchstructure causes the reduced-surface field (RESURF) effect which leads to full depletion of the drift region resulting large improvement in the breakdown voltage of the proposed device. At breakdown, the peak electric field occurs at point ‘C’ in the TGLDMOS. It is noteworthy that the TGLDMOS structure reported in [8] has a deep Pþ-sinker, spacing between the trench gate and Nþ-drain diffusion, and a source field-plate over the trench gate and the drift region. These structural modifications limit the lateral dimensions and hence restrict the further reduction in the cell of the device. On the other hand, the proposed TGLDMOS unit cell contains single drain and source contacts and two gates placed vertically in separate trenches without any horizontal field-plate leading to reduced cell pitch of the device. Moreover, the trench structure folds the drift region in vertical and horizontal directions leading to reduced cell pitch of 3 mm. The optimized device design allow higher drift layer doping of 3 1016 cm3 in the TGLDMOS. The breakdown voltage and on-resistance of the proposed structure are affected by
Silicon
Metal
Fig. 1. A schematic cross-sectional view of the unit cell of the (a) CLDMOS (b) TGLDMOS.
Table 1 Optimized parameters of the CLDMOS and TGLDMOS. Parameter
Unit
CLDMOS
TGLDMOS
Cell pitch, L Gate length, LG Field-plate length, LFP Drift region length, LD Drift region length 1, L1 Drift region length 2, L2 Gate oxide thickness, tox Oxide thickness, tox1 Oxide thickness, tox2 Oxide thickness, tox3 Oxide thickness, tox4 Epitaxial layer thickness, tepi Drift region thickness, td Buried oxide thickness, tBOX Drift region doping, Nd P-body doping
mm mm mm mm mm mm mm mm mm mm mm mm mm mm
5.00 0.50 1.50 2.10 e e 0.03 e e e e 0.60 e 0.60 2 1016 8 1016
3.00 0.50 e e 1.22 0.60 0.03 0.18 0.64 0.30 0.25 2.25 0.60 0.70 3 1016 8 1016
cm3 cm3
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3. Comparison of simulated results To understand the effect of structural parameters on the performance of the CLDMOS and TGLDMOS devices, we have created both the structures in the device simulator (ATLAS) [12]. Twodimensional numerical simulations were carried out by invoking suitable models in the simulator such as Shockley-Read-Hall model (SRH), Fermi-Dirac model (FERMIDIRAC), concentration dependent mobility model (CONMOB), electric-field-dependent mobility model (FLDMOB), and the Selberherrs impact ionization model (IMPACT SELB). Using the identical simulation models and their parameters for both the structures, the simulated characteristics are compared to evaluate their performance as discussed below: 3.1. ON-resistance Fig. 2 shows the simulated drain characteristics of the CLDMOS and TGLDMOS at gate-source voltage (VGS) of 6 V for low values of drain-source voltages (VDS) such that the devices operate in the linear region. These characteristics are used to determine the onresistance of the devices. The total on-resistance of an LDMOS is a series combination of channel resistance, drift region resistance, drain and source contact resistances. From Fig. 2, the total onresistance is calculated as the ratio of drain voltage to drain current and is multiplied by the pitch length to get the specific onresistance (RON). The specific on-resistance of the CLDMOS and TGLDMOS are found to be 52 and 42 mU-mm2, respectively resulting 19% reduction in RON for the proposed device. It may be noted that although, the drain current in the TGLDMOS is lower than that of the CLDMOS but the reduced pitch length leads to smaller RON. Fig. 3 shows the variation of specific on-resistance with
2 1
0
0.1
0.2 0.3 0.4 Drain Voltage, VDS (V)
0.5
Fig. 2. Drain characteristics of the CLDMOS and the TGLDMOS in the linear region for VGS ¼ 6 V.
2
4 3 5 Gate Voltage, VGS (V)
6
Fig. 3. Specific on-resistance variation with applied gate-source bias for the CLDMOS and TGLDMOS.
the gate-source bias for the CLDMOS and the TGLDMOS. Initially, as VGS is increased, the on-resistance of both the devices decreases rapidly because of enhancement in the channel conduction. As VGS is further increased, the on-resistance saturates to a particular value indicating that the channel is fully created and the onresistance is mainly limited by the drift region resistance. We observe that for entire range of VGS, the proposed device exhibits lower RON as compared to the conventional device. The threshold voltage of the TGLDMOS (1.34 V) is found to be close to that of the CLDMOS (1.58 V). The substrate of both the devices is kept at grounded potential (0 V).
3.2. Breakdown voltage The simulated breakdown characteristics of the TGLDMOS compared with that of the CLDMOS under off state are shown in Fig. 4. At zero gate bias, there is no path for conduction of electrons
2.5
3
0
50
0 1
TGLDMOS CLDMOS
4
TGLDMOS CLDMOS
100
Drain Current, ID (mA/mm)
Drain Current, ID (mA/mm)
5
150 ON−Resistance, (mΩ−mm2 )
various structural parameters whose optimized values are given in Table 1. Note that the proposed device provides 40% reduction in the cell pitch as compared to the CLDMOS. This will result a lower area of fabrication as the drift region resistance is reduced. The proposed TGLDMOS device may be fabricated using a process as reported for other trench-gate structures [10,11]. The TGLDMOS structure requires few additional fabrication steps as compared to the conventional device.
143
TGLDMOS CLDMOS
2.0 1.5 1.0 0.5 0
0
20
80 60 40 Drain Voltage, VDS (V)
100
Fig. 4. Off-state breakdown characteristics of the CLDMOS and TGLDMOS.
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Fig. 5. Two-dimensional electric field distribution in the drift region of the (a) CLDMOS and (b) TGLDMOS at VDS ¼ 35 V.
from source to drain because the channel is not created in P-base. This results in a normally-off device with the drain voltage mostly supported by the N-drift region. The breakdown voltage is taken as drain to source voltage at which drain current exceeds 0.1 mA/mm. As seen, the breakdown voltage of CLDMOS and TGLDMOS structures are 46 and 97 V, respectively resulting 110% improvement in the breakdown voltage. In order to understand such large enhancement in the breakdown voltage, it is useful to examine the electric field profile inside the drift region of both the devices. Fig. 5 shows the two-dimensional electric field distribution in the drift region of the CLDMOS and TGLDMOS at VDS ¼ 35 V. As seen from the Fig. 5(a), in case of the conventional device, the electric field is crowded on the silicon surface at the end of field-plate (point ‘A’). On the other hand, for the proposed structure, the maximum electric field occurs at the bottom edge of the trench (point ‘B’). In order to know magnitude of maximum electric field in the drift region of two devices, Fig. 6 gives the electric field variation along the horizontal cut line (1e2 in Fig. 1(a)) located on the top surface of
drift region in the CLDMOS and along the cut line (3e4 in Fig. 1(b)) at the bottom edges of two trenches in the TGLDMOS at VDS ¼ 35 V. As seen, the peak electric field in the proposed structure is significantly lower than that in the conventional device leading to higher breakdown voltage of the TGLDMOS. It is apparent that in case of the proposed device, the charge increases from source to drain with the applied voltage which modulates the electric field in the drift region resulting enhanced breakdown voltage. Fig. 7 illustrates a two-dimensional view of the electric field in the CLDMOS and the TGLDMOS when the applied drain-source voltage is equal to their breakdown voltages. As seen, the peak of electric field remains at point ‘A’ in the conventional device whereas it shifts to point ‘C’ in the proposed device. The peak electric fields at these points can be seen in Fig. 8 which gives the electric variation along the horizontal cut line 1-2 in the CLDMOS and the vertical cut line 5e6 (as in Fig. 1(b)) along the side-wall of trench near the drain. As seen, the peak electric fields in both structures are equal which verify the breakdown of the CLDMOS and TGLDMOS at point ‘A’ and ‘C’,
Y. Singh, R.S. Rawat / Engineering Science and Technology, an International Journal 18 (2015) 141e149
0.8
0.2
merit (BFOM) for the CLDMOS and TGLDMOS is calculated as 4.07 and 22.40 MW/cm2, respectively. This provides 5.5 times improvement in the BFOM of the proposed device as compared with the conventional device. Further, the dynamic losses figure-ofmerit (FOM ¼ RON.Qgd) of the TGLDMOS structure is found to be 26 mU-nC as compared to 46 mU-nC of the CLDMOS resulting 43% reduction in FOM. A comparison summary of static and dynamic performance of the proposed device with that of the other reported SOI LDMOS devices is given in Table 2. The proposed TGLDMOS structure exhibits significantly higher BFOM than the other counterparts, which demonstrates better suitability of the proposed device for low to medium voltage power applications. The switching performance of the proposed TGLDMOS is comparable to that of the LTDGMOS [9].
0.1
4. Device optimization
TGLDMOS CLDMOS
0.7 Electric Field, (MV/cm)
145
VDS =35V
0.6 0.5
A
0.4 B
0.3
0
0
0.5
1 2 1.5 Distance, (µm)
2.5
3
Fig. 6. Electric field variation in the drift region of the CLDMOS along cut line 1e2 and the TGLDMOS along cut line 3e4 at VDS ¼ 35 V.
respectively. It is noteworthy that the maximum electric field in the TGLDMOS occurs below the semiconductor surface (away from the dielectrics) which typically yields higher critical electric field strength. 3.3. Gate charge analysis Gate charge (Qg) is the amount of charge required on the gate to turn on the LDMOS for a given on-resistance. This gives an estimation of switching performance of the device. In order to minimize the switching losses of a power LDMOS, the gate charge should be as low as possible. Fig. 9 shows the gate charge curves of the TGLDMOS and the CLDMOS devices. These characteristics are obtained using mixed mode simulations in the device simulator. The circuit used to perform the gate-charge transient is given in the inset of this figure. In these simulations, the device width is kept 4000 mm for both the structures. As seen, for a given VGS, the total Qg of the TGLDMOS is lower than that of the CLDMOS. Moreover, the gate-to-drain charge (Qgd) is taken as the amount of charge that must be input to overcome the “Miller” effect as the drain voltage falls. This occurs during the plateau of the VGS waveform where the voltage is constant. From Fig. 9, the Qgd of the proposed TGLDMOS and CLDMOS devices are found to be 0.62 and 0.88 nC/mm2, respectively. The proposed device gives 30% lower Qgd as compared to the conventional device. This reduction in Qgd is due to lower gate-to-drain capacitance (Cgd) of the proposed device when compared to the CLDMOS as shown in Fig. 10. The CLDMOS structure exhibits higher value of Cgd due to presence of a gate field-plate over the drift region with thin oxide (tox) whereas the TGLDMOS device has thicker oxides (tox2 & tox3) between the gate and the drift region resulting lower Cgd. 3.4. Figure-of-merit In the previous subsections, it is observed that the TGLDMOS not only provides lower specific on-resistance but also enhances the breakdown voltage. This indicates that the performance of the TGLDMOS is superior to that of the CLDMOS and yields conditions for a better trade-off between the breakdown voltage and specific on-resistance. From our simulation results, the Baliga's figure-of-
In this section, we will investigate the effect of physical parameters on the performance of the TGLDMOS structure. The breakdown voltage and on-resistance are influenced by various device parameters such as the drift region concentration (ND), length of drift region (L2), drift region thickness (td), the epitaxial layer thickness (tepi), and the oxide thickness (tox2, tox3, tox4). These parameters are optimized in such a way that the device provides optimal trade-off between the breakdown voltage and the specific on-resistance resulting maximum BFOM. The dependence of the breakdown voltage and BFOM on the doping concentration of drift layer in the TGLDMOS is given in Fig. 11. As the doping concentration increases, the breakdown voltage of the structure enhances due to spreading of the depletion layer over the entire drift region which causes reduction in electric field inside the device. In other words, full depletion of the whole drift region is responsible for higher breakdown voltage. This is due to RESURF effect caused by the presence of trenches in the drift region. However, as the drift layer doping is increased above 3 1016 cm3, the drift region is not fully depleted at the drain side and causes an increased electric field inside the device leading to a rapid drop in breakdown voltage. The structure provides maximum BFOM at an optimum doping of 3 1016. Fig. 12 shows the effect of drift region length (L2) on the breakdown voltage and figure-of-merit. It is observed that the breakdown voltage of the device decreases as L2 is varied from 0.40 to 0.85 mm due to increase in the peak electric field at trench bottom. However, the onresistance of the structure is reduced marginally due to increase in cross-sectional area for flow of the drain current. This leads to an optimum BFOM for a length of 0.6 mm. In the next step, we have optimised the drift region thickness (td) by analysing its influence on the breakdown voltage and figure-of-merit as shown in Fig. 13. It can be seen that the breakdown voltage decreases slowly for variation of td from 0.20 to 0.65 mm and reduces rapidly thereafter. This is due to change in the electric field distribution in the device with td. This thickness also affects the on-resistance of the device due to change in drift region resistance. The optimized value of td is obtained as 0.6 mm corresponding to maximum BFOM. Fig. 14 gives a trade-off between the breakdown voltage and onresistance for change in epitaxial layer thickness (tepi) of the TGLDMOS. Keeping the td & tox3 fixed, the variation in tepi scales the length of vertical field-plate (the downward extension of the gate-polysilicon). The breakdown voltage of the structure improves as tepi is increased from 1.6 to 2.6 mm and saturates to a maximum value for further increase in tepi. On the other hand, the on-resistance is also affected by tepi resulting a significant improvement in the BFOM for increase in tepi from 1.6 to 2.25 mm. However, the performance of device degrades after 2.25 mm as optimum value of tepi. The other key dimensions of the structure
Fig. 7. Two-dimensional electric field distribution at breakdown voltage in the drift region of the (a) CLDMOS and (b) TGLDMOS.
5 TGLDMOS CLDMOS At breakdown
Gate Voltage, VGS (V)
Electric Field, (MV/cm)
1.5
1 C
A
0.5
0
0
0.5
2 1.5 1 Distance, (µm )
2.5
3
Fig. 8. Electric field variation in the drift region of the CLDMOS along cut line 1e2 and the TGLDMOS along cut line 5e6 at breakdown voltage.
4 3
10 V 100 μA CGD 10 μA
C GS
2 1 0 0
CLDMOS TGLDMOS
0.4
0.8
1.2
1.6
Gate Charge, Qg /AA (nC/mm2)
2.0
Fig. 9. Gate-charge characteristics of the TGLDMOS and CLDMOS.
140
CLDMOS TGLDMOS
120
−15 10
−16 10
5
0
15
10
20
Breakdown Voltage FOM
25
Drain Voltage, VDS (V)
147
40 35 30
100
Figure of Merit, (MW/cm 2)
−14 10
Breakdown Voltage, (V)
Gate−Drain Capacitance (F/µ m)
Y. Singh, R.S. Rawat / Engineering Science and Technology, an International Journal 18 (2015) 141e149
25 80
20 60
15
40
10
20
5
0
0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Drift Region Length, L2 (µ m)
Fig. 10. Gate-drain capacitance of the TGLDMOS and CLDMOS.
Fig. 12. Breakdown voltage and figure-of-merit variation with drift region length (L2) of the TGLDMOS.
Breakdown Voltage FOM
25
80
20
60
15
40
10
20
5
0
breakdown voltage on tox2, tox3, and tox4 are illustrated in Figs. 15e17, respectively. It may be noted that the on-resistance of the device is not affected by these dimensions and hence the trends of BFOM curves are same as that of the breakdown voltage. Simulation results show that the optimum values of oxide thickness are tox2 ¼ 0.65 mm, tox3 ¼ 0.30 mm, tox4 ¼ 0.25 mm. It is to be pointed out that the variation in the oxide thickness, tox1 does not affect the breakdown voltage and the on-resistance of the TGLDMOS. However, the gate-source capacitance increases by reducing the tox1 thickness. The optimised values of all parameters are given in Table 1 which are used in simulations to compare the performance of the proposed device with that of the conventional counterpart.
0
0
1
2
3
5
4
6
7
140
16
Doping, ND (x10 cm 3 )
affecting the breakdown voltage are the oxide thickness tox2, tox3, and tox4. These parameters modulate the electric field distribution inside the device and maximum breakdown voltage is achieved for an optimum value of parameters so that the electric field profile in the device becomes more uniform. Dependence of the
Table 2 Performance comparison of power LDMOS devices. Device structure
VBR (V)
RON (mU-cm2)
BFOM VBR2/ RON (MW/cm2)
Qgd nC/cm2
FOM Qgd.RON (mUenC)
CLDMOS TGLDMOS [8] LTDGMOS [9] TGLDMOS (This work)
46.0 97.4 69.0 97.0
0.52 1.42 0.37 0.42
4.07 6.68 12.87 22.40
88 e 63 62
46 e 23 26
120 Breakdown Voltage, (V)
Fig. 11. Breakdown voltage and figure-of-merit as a function of drift region doping of the TGLDMOS.
Breakdown Voltage FOM
35 30 Figure of Merit, (MW/cm2)
Breakdown Voltage, (V)
100
Figure of Merit, (MW/cm 2 )
30
120
100
25
80
20
60
15
40
10
20
5
0
0
0.6 0.2 0.8 0.4 Drift Region Thickness, td (μm)
0 1.0
Fig. 13. Breakdown voltage and figure-of-merit variation with the drift region thickness (td) of the TGLDMOS.
Y. Singh, R.S. Rawat / Engineering Science and Technology, an International Journal 18 (2015) 141e149
140
Breakdown Voltage FOM
Breakdown Voltage, (V )
120 100
35 30 25
80
20
60 15 40 10
20
Figure of Merit, (MW/cm 2)
148
5 0 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 Epitaxial Layer Thickness, tepi (μ m) Fig. 14. Breakdown voltage and figure-of-merit variation with epitaxial layer thickness (tepi) of the TGLDMOS.
Fig. 16. Dependence of breakdown voltage and figure-of-merit on oxide thickness, tox3 of the TGLDMOS.
5. Conclusion
130
Breakdown Voltage, (V)
120 110
Breakdown Voltage FOM
50 45 40
100
35
90
30
80 70
25 20
60
15
50
10
40 30
5
Figure of Merit, ( MW/cm2 )
A power LDMOS structure on SOI is presented which utilizes two vertical gates placed in two trenches on both sides of P-base region. The proposed trench structure suppresses the electric field in the drift region and allow higher drift layer concentration with reduced pitch length leading to a superior performance in terms of maximum breakdown voltage, minimum specific on-resistance, reduced gate-charge, and higher figure-of-merits. Numerical simulations are used to analyse and evaluate the performance of the proposed device and results are compared with that of the conventional device. The device parameters such as drift region concentration (ND), drift region length (L2), drift region thickness (td), epitaxial layer thickness (tepi), and oxide thickness (tox2, tox3, tox4) are varied in order to see their influences on the device performance. These parameters are optimised to obtain maximum figureof-merit. Based on simulations results, it is demonstrated that the
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Oxide Thickness, t ox2 (µ m )
Fig. 15. Breakdown voltage and figure-of-merit variation with oxide thickness, tox2 of the TGLDMOS.
Fig. 17. Breakdown voltage and figure-of-merit variation with thickness, tox4 of the TGLDMOS.
proposed structure can provides 110% improvement in breakdown voltage, 19% reduction in specific on-resistance, 30% decrease in gate-to-drain charge and 40% lower cell pitch when compared with the conventional LDMOS. The Baliga's figure-of-merit of the proposed device is 22.40 MW/cm2 which is significantly higher than that of the other similar structures reported in literature. These improvements in the performance of the proposed device are achieved at the cost of few additional fabrication steps. Our results show that the proposed device is a suitable power LDMOS for power integrated circuits. References [1] M. Zitouni, F. Morancho, H. Tranduc, P. Rossel, J. Buxo, I. Pags, et al., A new lateral power MOSFET for smart power ICs: the LUDMOS concept, Microelectron. J. 30 (1999) 551e561.
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