High-k dielectrics for future generation memory devices (Invited Paper)

Microelectronic Engineering 86 (2009) 1789–1795

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High-k dielectrics for future generation memory devices (Invited Paper) J.A. Kittl a,*, K. Opsomer a, M. Popovici a, N. Menou a, B. Kaczer a, X.P. Wang a, C. Adelmann a, M.A. Pawlak a, K. Tomida a, A. Rothschild a, B. Govoreanu a, R. Degraeve a, M. Schaekers a, M. Zahid a, A. Delabie a, J. Meersschaut a, W. Polspoel a, S. Clima a, G. Pourtois a, W. Knaepen b, C. Detavernier b, V.V. Afanas’ev c, T. Blomberg d, D. Pierreux e, J. Swerts e, P. Fischer e, J.W. Maes e, D. Manger f, W. Vandervorst a, T. Conard a, A. Franquet a, P. Favia a, H. Bender a, B. Brijs a, S. Van Elshocht a, M. Jurczak a, J. Van Houdt a, D.J. Wouters a a

IMEC, Kapeldreef 75, Leuven 3001, Belgium Dept. of Solid State Sciences, Universiteit Gent, Krijgslaan 281/s1, 9000 Gent, Belgium Dept. of Physics and Astronomy, Katholieke Universiteit Leuven, Celestijnenlaan 200D, 3001 Leuven, Belgium d ASM Microchemistry, Väinö Auerin Katu 12 A, 00560 Helsinki, Finland e ASM Belgium, Kapeldreef 75, 3001 Leuven, Belgium f Qimonda, Kapeldreef 75, 3001 Leuven, Belgium b c

a r t i c l e

i n f o

Article history: Received 3 March 2009 Accepted 5 March 2009 Available online 13 March 2009 Keywords: High-k DRAM Flash SrTiO3

a b s t r a c t The requirements and development of high-k dielectric films for application in storage cells of future generation flash and Dynamic Random Access Memory (DRAM) devices are reviewed. Dielectrics with kvalue in the 9–30 range are studied as insulators between charge storage layers and control gates in flash devices. For this application, large band gaps (>6 eV) and band offsets are required, as well as low trap densities. Materials studied include aluminates and scandates. For DRAM metal–insulator–metal (MIM) capacitors, aggressive scaling of the equivalent oxide thickness (with targets down to 0.3 nm) drives the research towards dielectrics with k-values >50. Due to the high aspect ratio of MIMCap structures, highly conformal deposition techniques are needed, triggering a substantial effort to develop Atomic Layer Deposition (ALD) processes for the deposition of metal gates and high-k dielectrics. Materials studied include Sr- and Ba-based perovskites, with SrTiO3 as one of the most promising candidates, as well as tantalates, titanates and niobates. Ó 2009 Elsevier B.V. All rights reserved.

1. Introduction Recently, much work has focused on the development of high-k dielectrics and metal gates for high-performance logic Complementary Metal–Oxide–Semiconductor (CMOS) applications [1–6]. At the center of this effort and as motivation, was the need to continue to scale equivalent oxide thickness (EOT) without increase in gate leakage. Production-worthy Hf-based high-k dielectric/metal gate solutions were developed achieving band edge work-functions using either replacement gate flows or gate first flows. For this application, the materials studied had k-values in the 10–30 range, with band gaps typically in the 5.8–9 eV range. At the same time, high-k dielectrics are also of great interest for application in mass storage memory devices. In particular, they are being investigated for applications in storage cells for the two largest commodity memory markets: NAND flash and

* Corresponding author. E-mail address: [email protected] (J.A. Kittl). 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.03.045

Dynamic Random Access Memory (DRAM). The requirements and materials studied are different than those for high-performance logic, and are specific for each application. In both cases, the introduction of high-k dielectrics is driven by scaling. However, the requirements are quite different, leading to different groups of materials targeted for DRAM and flash applications. Fig. 1 shows the trend of band gap as a function of dielectric constant observed for high-k dielectrics in general (data for dielectric films studied in this work, in good agreement with literature reports) [2,3]. Within this trend, the regions of interest for next generation DRAM and flash applications are indicated. As will be overviewed in the next section, materials with very high permittivity are of interest for DRAM capacitors, in which very low EOT values are targeted. In contrast, relatively large band gaps and band offsets are needed for flash applications, resulting on the selection of materials with moderate k-values. In this paper, we present an overview of the development of high-k dielectrics for storage cells for application in NAND flash and DRAM metal–insulator–metal capacitors (MIMCaps), with emphasis and examples from work performed at IMEC.

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10

Al2 O3 flash YAlO3 HfAlO3 LaAlO3 GdScO3 HfSiO 4 Gd2O3 DyScO3 DRAM ZrO2BaZrO Sc2O3 3 Ta2O 5 Si 3N4 Dy O 2 3HfO 2 Nb 2O5 SrTiO3 Y2 O 3 HfTiO 4 TiO2

SiO2

Band Gap (eV)

8 6 4 2 0 1

10

100

1000

Dielectric Constant Fig. 1. Dielectric constant vs. optical band gap for several high-k dielectrics. Regions of interest for future generation NAND flash and DRAM MIMcap devices are indicated.

2. High-k dielectrics for DRAM MIMCap A significant effort on high-k dielectrics had been devoted already more than a decade ago for application in DRAM storage capacitors [7–10]. The motivation here was also scaling, in this case, the need to scale the size of DRAM cells, or equivalently, to increase their packing density. The target of these efforts was the introduction of high-k dielectrics to increase capacity per unit area as an alternative to the development of complex high aspect ratio structures which increase the area of the capacitors per wafer unit area. Materials such as SrTiO3 (STO) and BaSrTiO3 (BST) with k-values in excess of 100 and relatively small band gaps (3.2 eV) were investigated in combination with high WF metal electrodes, typically Pt [7–10]. Non-conformal deposition techniques, such as RF magnetron sputtering and pulsed laser ablation, were typically studied in this phase [7–10]. However, this effort was abandoned at that time, and the industry opted to continue the path of geometrical scaling with trench or stack capacitors with increasing aspect ratios, leading to extreme geometries which resulted in very high capacitor area per wafer area. Recently, the need to continue scaling led again to interest in high-k dielectrics for this application, but in this case, with the added complexity of an implementation with high aspect ratio geometries. In order to maintain low leakage and also as a way to minimize equivalent oxide thickness (EOT), metal–insulatormetal capacitors (MIMCap) using metals with high work function (WF) are investigated. A key difference with respect to the earlier work is that in order to be compatible with the very high aspect ratios of DRAM capacitors used today in production, highly conformal deposition techniques are mandatory. Layer thicknesses are also geometrical constrained to few tens of nm for the whole MIMCap stack. Atomic Layer Deposition (ALD) appears as the most promising technique to fulfill the aggressive conformality and thickness-control requirements of DRAM MIMcaps, triggering a substantial effort to develop ALD processes for the deposition of metal gates and high-k dielectrics for this application [11–15], as well as optimization of the films and stacks obtained. For future generation DRAMs, roadmap requirements indicate a need for extremely low EOT values (0.5 nm going down to 0.35 nm), while maintaining very low leakage currents (10 8 A/ cm2 at 1 V). In order to meet these requirements, alternative dielectrics with k-values in excess of 50 are needed. Materials that were previously explored for planar MIMcaps are now studied for applications in high aspect ratio geometries, resulting in quite different constraints. At this extremely low EOT values, optimization of electrodes and dielectric/electrode interfaces is also necessary,

to minimize EOT penalties from these contributions. Selection of a high WF metal electrode compatible with the high-k dielectric is, thus, also challenging. While Pt has excellent properties as high WF metal electrode and was used successfully in much of the previous experimental work [7–10], it is not considered as a viable candidate for mass production due to the difficulty of etching and prohibitive cost. Ru-based electrodes are considered [13–15], but cost is also an issue in this case, in addition to its complex interaction with oxygen. Manufacturing-friendly, low cost electrodes are preferred, such as TiN or Ni, although their scaling potential is questionable. Fig. 2 summarizes the requirements for future generation DRAM MIMcaps. As a first example, TiN/ZAZ/TiN MIMcaps were recently introduced, where ZAZ is a tri-layer of ZrO2/Al2O3/ZrO2 [16]. The intercalation of a thin amorphous Al2O3 layer between two ZrO2 films results in leakage reduction at same EOT value when compared to single layer ZrO2. We investigated the use of an ASM A412 batch LPCVD furnace for the ALD deposition of TiN, ZrO2 and Al2O3. Fig. 3 shows transmission electron microscopy (TEM) characterization of the TiN/ZAZ/TiN MIMcap stack. The dielectric stack is 10 nm thick, the ZrO2 top and bottom layers are crystalline and the Al2O3 interlayer is clearly visible. EOT values in the 0.75– 0.85 nm range were obtained in this work, with leakage currents in the 10-8 A/cm2 range at 1 V. Typical k-values for optimized capacitors are 30. It is expected, however, that ZAZ will not provide a solution for further EOT scaling into the sub-0.6 nm range. In order to achieve further EOT scaling, materials with higher-kvalues are being considered. ALD processes for deposition of the different materials investigated are developed, and the layers subjected to several screening criteria. As listed in Fig. 2, one of the requirements for next generation DRAMs is that processing temperatures be maintained below 650 °C. For this reason, the dielectrics considered have either to have high enough k-values in the as-deposited state (typically amorphous), or crystallize into the phase with large k-value at or below 650 °C. In situ X-ray diffraction (IS-XRD) is a valuable tool for a screening assessment of crystallization temperatures (as well as of the phases formed) for candidate films. Fig. 4a shows examples of IS-XRD patterns collected for some of the dielectrics under consideration. It is observed that the crystallization temperatures (Tcryst) of Ta2O5 and BaZrO3 are too high and do not meet the DRAM requirements. Addition of Nb reduces the crystallization temperature of the alloy Nb–Ta pentoxides (adequate Tcryst was also found for Nb2O5 films). HfTiO4 films crystallize into the orthorhombic phase at a temperature close to that required. It is important to consider, however, TM

Fig. 2. Schematic of DRAM MIMcap structure, requirements and strategy for future generation DRAM MIMcaps.

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Fig. 3. (a) High resolution TEM image and (b) HAADF-STEM (Z-contrast) analysis of ZAZ stack. TiN, Al2O3 and ZrO2 layers were deposited by ALD. TiN and ZrO2 layers are crystalline.

that the crystallization temperature (and the phases formed) of thin films may depend on the substrate, capping layers, composition, contaminants, anneal ambient and film thickness. IS-XRD studies are, thus, conducted for a variety of conditions to extract these dependences. Fig. 4b illustrates the anneal temperatures needed for several high-k dielectrics and their k-values. This type of analysis serves as initial screening criteria. While HfTiO4 or (Nb–Ta)2O5 films may provide intermediate solutions (e.g. leakage currents down to the 10 7 A/cm2 range were obtained at 1 V with single layer HfTiO4 films at EOT 0.8 nm), it is unlikely that they can be scaled with low leakage to EOT values below 0.5 nm. From the different materials studied in this work, one of the most promising is SrTiO3. For this reason, but also as model system exemplifying the methods and techniques used for the other systems as well, we go into more details for this system.

a Two Theta (deg)

20 35 20 35

Ta2O5 (Nb-Ta)2O5

Recently, ALD STO using Sr(thd)2 as Sr-precursor was reported with promising results on noble like metal electrodes such as Ru and Pt [13–15]. However, these processes required either high deposition temperatures (>350 °C) and/or post-deposition anneals in oxidizing ambients, making STO incompatible with manufacturing-friendly, lower cost electrodes such as TiN. An alternative precursor set using Sr(t-Bu3Cp)2 was also reported [11,12] for STO growth. We further explored this alternative precursor system for the growth of STO films for DRAM MIMcap applications [17]. The STO layers were deposited by ALD in a cross-flow ASM PulsarÒ 2000 reactor, at reactor temperatures in the 250–300 °C range, using Sr(t-Bu3Cp)2, H2O, and Ti(OCH3)4. By changing the Sr-precursor and the Ti-precursor pulse sequence (Fig. 5), ALD allows the growth of a wide compositional variety of STO films from pure TiO2 to Sr-rich STO, with straight forward composition tuning. This is typical for well behaved ALD processes. In ALD, the film growth is determined by self-limiting surface reactions, guaranteeing conformal deposition (Fig. 5 inset) in high aspect ratio structures. The crystallization behavior of STO films was also studied by ISXRD [17]. Fig. 6 shows the IS-XRD patterns of STO films on TiN for three different Sr–Ti compositions, corresponding to Sr/(Sr + Ti) atomic ratios of 0.43 (‘‘Ti-rich”), 0.57 (‘‘Std. Comp.”) and 0.64 (‘‘Sr-rich”). The crystallization temperature increases as the com-

26 38

BaZrO3

a

25 40

Sr(tBu3Cp)2

HfTiO4

100

300 500 700 Temperature (oC)

H2O

Ti(OCH3)4

N2 carrier gas

900

n*Sr-cycle

b

100

b TiO2 (Rutile)

Nb2O5 HfTiO SrTaO 4 3 Bi-Ta-O

10 200

400

Ta2O5

600

m*Ti-cycle

x* Full cycle

BaTiO3

BaZrO3

800

1000

Anneal Temperature (oC) Fig. 4. (a) IS-XRD patterns (0.2 °C/s ramp in N2) showing the crystallization of several oxide thin films. Crystallization temperatures for BaZrO3 and Ta2O5 are too high for the requirements of future generation DRAMs. (b) Dielectric constants vs. required anneal temperatures for several high-k dielectrics, shaded area corresponds to region of interest for future DRAM MIMcaps. For all films, except Bi–Ta–O, the anneal temperatures correspond to those needed for crystallization.

Sr/(Sr+Ti) atomic ratio

Dielectric Constant

1000

SrTiO3

H2O

0.7 0.6 0.5 0.4

400 nm

0.3 0.2 0.1 0.0

0

0.2

0.4

0.6

0.8

1.0

Sr/(Sr+Ti) cycle ratio (n/(n+m)) Fig. 5. (a) Schematic of low temperature ALD SrTiO3 deposition process and (b) Sr/ (Sr + Ti) atomic ratio vs. pulse ratio showing good Sr–Ti composition control for a wide range of compositions. Films have excellent conformality (inset in b).

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TiN

40

Two Theta (deg.)

45

TiN

Std. Comp.

(111) SrTiO3

30 35

(110) SrTiO3 TiN

40 45

TiN

Ti-rich (111) SrTiO3

30 35 40 TiN

SrTiO3 (Std. Comp.) K ~ 20 (amorph.)

K ~ 150 (cryst.)

(111) SrTiO3

45 100 300 500 700 900

Temperature (oC) Fig. 6. IS-XRD patterns of SrxTiyO3 films on TiN, for three different compositions, showing crystallization into the perovskite phase.

position further deviates from that of stoichiometric SrTiO3. Nevertheless, all films crystallize below 600 °C. A kink in the pattern is clearly noticeable for the Sr-rich film, indicating a change of lattice parameter at high temperatures. The high temperature lattice parameter for all films is similar and corresponds to that of bulk SrTiO3. The distortion of the lattice parameter at low temperatures for Sr-rich films suggests that a metastable structure may be initially formed upon crystallization, likely with incorporation of excess Sr into the STO grains, resulting in the expansion of the lattice parameter. At high temperatures, excess Sr may be released or redistributed, resulting in the shift towards bulk STO values. XRD patterns did not reveal the formation of Ruddlesden–Popper phases [18] with ordering of excess SrO planes. Electrical evaluation shows the dramatic change in properties of the STO films upon crystallization. Fig. 7a shows the EOT vs. thickness plots for ‘‘Std. Comp.” STO films (extracted using Pt-dot capacitors), comparing as-deposited films to films that received a postdeposition anneal in N2 (1 min) at 500, 550, 600 and 650 °C. The as-deposited films and films with 500 °C anneal have k-values of 20. This corresponds to amorphous STO. Films that received anneals at 550 °C and higher temperatures crystallized into the perovskite structure achieving k 150. The k-values indicated correspond to those extracted from the slope of the EOT vs. thickness plots. As observed in Fig. 7a, extrapolations to 0 physical thickness typically correspond to non-zero EOT values, in this case, 0.3– 0.4 nm. This may be attributed in part to interfacial layers between the electrodes and the dielectric. However, even for ideal interfaces, an EOT penalty (‘‘dead layer”) is expected, with local reduction of the k-value in the interface region [19]. As a consequence, effective k-values (obtained by simply dividing EOT by physical thickness) are typically smaller than those obtained from the slope of EOT vs. thickness plots, and decrease as the film thickness decreases. Since the roadmap for future DRAM nodes calls for aggressive EOT scaling (0.5–0.35 nm), interfacial penalties will become dominant and need to be minimized. Thus, selection of the electrode and optimization of the interface between electrode and high-k becomes crucial. Leakage characterization of the STO films showed a strong dependence on composition, with lower leakage observed for 7 nm Sr-rich films compared to 9–12 nm films with higher Ti content (Fig. 7b) [17]. Film thicknesses were extracted by TEM analy-

40

SrTiO3/ALD TiN

10-1 1.E-01

Sr-rich

TiNas dep. TiN 500 oC TiN 550 oC TiN 600 oC Ru 600 oC Pt 650oC

10 20 30 Thickness (nm)

100 b 1.E+00

(110) SrTiO3 TiN

8 7 6 5 4 3 2 1 0 0

Ti-rich, 600°C

10-2 1.E-02

Jg (A/cm2)

35

(110) SrTiO3

EOT (nm)

a

30

1.E-03 10-3 1.E-04 10-4

Std. Comp., 550°C EOT=0.69 nm

1.E-05 10-5 1.E-06 10-6

Sr-rich, 550°C EOT=0.49 nm

1.E-07 10-7 1.E-08 10-8

0

0.5 1.0 1.5 Applied Voltage (V)

2.0

Fig. 7. (a) EOT vs. thickness plots of ALD SrxTiyO3 films on TiN, Ru and Pt bottom electrodes (Pt-dot capacitors), for as-deposited STO films and STO films that received post-deposition anneals at 500, 550, 600 and 650 °C; (b) I–V curves (einjection from TiN) of crystallized ALD SrxTiyO3 thin films on ALD TiN.

sis, which also showed the Sr-rich and Std. Comp. films to be crystalline after the 550 °C anneal. The k-values of the crystalline STO films also depend on composition, with the highest value obtained for stoichiometric films (k 220) and k 75 obtained for Srrich films (Sr/(Sr + Ti) atomic ratio of 0.64). The temperature and voltage dependence of the leakage of Srrich films was characterized for films with several different thicknesses. The conduction mechanism was identified as electronic hopping between interacting trap sites [20]. In combination with photoconductivity measurements, the data is consistent with a band gap of 3.25 eV and a band of interacting trap sites at 0.7– 1.2 V below the conduction band edge. This was further supported by ab initio simulations using the local density approximation [20]. Macroscopic leakage measurements were also complemented by conductive atomic-force-microscope (CAFM) analysis, which showed conductance through the bulk of STO grains for Sr-rich films, in contrast to Ti-rich films which exhibited localized highconductance paths [17]. 3. High-k dielectrics for flash applications Significant effort is currently also dedicated to the study and development of high-k dielectrics and metal gates for non-volatile memory (NVM) applications [21,22]. Within the commodity memories, the NAND flash market has expanded significantly in recent years driven by applications in portable devices. One of the reasons for the success of NAND flash is its density integration potential, which allows fabrication of large memory arrays. NAND flash memories currently in the market use floating gate (FG) architectures. The wordline, typically implemented using n+polycrystalline-Si (poly-Si), runs over several floating gates. Silicon oxide–nitride–oxide (‘‘ONO”) stacks are used as inter- poly-Si

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CG. The Al2O3 film in this case has crystallized into the c-phase, with (1 1 1) texture, as confirmed by plan view TEM and XRD analysis, and exhibits good retention. As already mentioned, the density and position of traps in the IPD or BO dielectric have a crucial impact on the device retention properties. A new and powerful method for characterizing defect bands in dielectric materials, Trap Spectroscopy by Charge Injection and Sensing (TSCIS), was recently proposed [24]. This technique is quantitative and spectroscopic resulting in a trap density plot vs. energy and spatial position. Fig. 9 shows the trap density plots obtained by TSCIS, comparing amorphous to c-Al2O3 [24]. For the crystalline c-Al2O3, the defects are localized in a horizontal band between 1.7 and 2.0 eV below the conduction band edge. In contrast, the trap density spectrum of amorphous Al2O3 shows no distinct features. In the scanned range, traps are distributed evenly in both space and energy (including a significant density of shallow traps). In combination with the change in band gap and band offsets with crystallization, these observations explain the significant improvement in retention behavior with crystallization of the Al2O3. While, as initial implementation, Al2O3 may be adequate, materials with higher-k are required for future generations. For this reason, several dielectrics with k-value in the 12–30 range are being investigated. Ideally, the increase in k-value should be accomplished without a large penalty in band gap (band offset) reduction or trap density increase. Aluminates and scandates appear as candidates that may fulfill these requirements (Fig. 1). As example, considering the rare earth (RE) scandates (e.g. DyScO and GdScO), it is possible to increase considerably the k-value compared to that of Sc2O3 or the corresponding rare earth binary oxide (Fig. 10) [25], without a penalty in band gap or band offsets, which remain close to those of Sc2O3 (band gap 6 eV and conduction band offset respect to Si of 2.0 eV) for a wide compositional range. It is interesting to notice, that the RE scandates with k-values >20 shown in Fig. 10 (post-deposition anneal (PDA) of 800 °C) are amorphous, while the binary oxides, with lower k-values, are crystalline. Considering the aluminates such as HfAlO or REAlO, we note that their crystallization is also delayed with respect to that of the binary oxides by the addition of alloying elements. The band gaps (Eg) obtained for the amorphous aluminates (HfAlO or LaAlO), of 6 eV, while close to that of amorphous Al2O3 and maintained for a wide compositional range (see example in Fig. 11), are considerably lower than that of crystalline Al2O3. The con-

dielectric (IPD) [23], i.e. between the storage FG and the top control gate (CG). In the present implementation, the poly-Si CG wraps around the FG. The sidewall overlap contributes to the capacitance between the CG and the FG, which provides the necessary electrical coupling for operating the device. External voltages applied on the top gate (CG) induce a voltage drop over the tunnel dielectric, i.e. between the FG and the Si substrate, which allow carrier transport through the tunnel dielectric (program/erase) or just enough bias for sensing the charge stored on the FG (read out). Reduction of the feature size below 40 nm may, however, requires modifications of the FG cell architecture, due to lack of physical space between neighboring cells, which no longer allows wrapping of the CG over the FG. The resulting structures will be ‘‘planarized” and the loss of the coupling capacitance from the sidewalls leads to the degradation of the coupling factor. To address this problem, high-k dielectrics are being studied as candidates to replace ONO stacks as IPD in order to increase the gate coupling factor. In addition to FG architectures, significant work has been recently devoted to the development of charge trap (CT) flash cells. In this concept, the charge is stored in a ‘‘trapping layer” with a high density of deep traps, typically a nitride. High-k dielectrics are also studied for CT devices, as blocking oxides (BO) between the trap layer and the control gate. As examples, cross-sections of stacks being studied for FG and for CT devices are shown in Fig. 8. For both for applications, i.e. as IPD in FG or BO in CT devices, dielectrics with large band gaps and band offsets are needed, which practically limits the k-value of the materials to a moderate range (typically 9–20), as shown in Fig. 1. Typical charge retention specs for flash devices require IPD (or BO) with very low leakage. As a consequence, another important consideration for high-k dielectrics targeted for flash devices is to have very low trap densities. Al2O3, with a k-value of 9, has been studied as one of the main candidates to replace ONO as IPD in FG devices or as BO for charge trap memories [21,22]. Significantly improved device characteristics are obtained for crystalline Al2O3 compared to amorphous Al2O3. Upon crystallization, the band gap and band offsets of Al2O3 increase dramatically [4]. IS-XRD analysis of thin (12– 20 nm) Al2O3 films indicates crystallization into the c-Al2O3 phase typically at 850 °C. However, the crystallization of the films (and consequently device characteristics, such as retention), texture and microstructure were found to be strongly dependent on the deposition technique and parameters. Fig. 8a shows a TEM cross-section of the top portion of a FG device using Al2O3 as IPD and a TiN metal

a)

Poly-Si

TiN

Control Gate

TaN

Al2O3

5 nm

c)

b)

Poly-Si

Blocking Oxide (high-k)

DyScO Al2O3

Si3N4 SiO2

(100) Si

charge storage tunnel oxide

5 nm

Si

Fig. 8. TEM cross-sections of (a) top portion of a FG device using Al2O3 IPD and TiN CG, and (b) CT device with SiO2 tunnel oxide, Si3N4 trapping layer, DyScO/Al2O3 BO and TaN CG; (c) schematic of flash cell (charge storage layer is a nitride in CT devices and poly-Si in FG devices.)

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Trap density (eV-1 cm-3)

defect band

Distance from interface (nm)

Trap density (eV-1 cm-3)

Energy from Al 2 2O 3 3 band edge (eV)

b) Amorphous Al2O3

Distance from interface (nm) Fig. 9. Trap density plots vs. energy and spatial position for (a) crystalline c-Al2O3 and (b) amorphous Al2O3 films.

Dielectric Constant

30 25

amorphous 20 15

duction band offsets measured by internal photoemission (2.1 eV with respect to Si, corresponding to barriers for the valence band electrons, Ue, of 3.2 eV) also remain independent of composition and close to that of amorphous Al2O3. In contrast to the case of the RE scandates, the dielectric constants for amorphous HfAlO and LaAlO films vary monotonically (linearly) with composition, with values of 14 and 16 for LaAlO and HfAlO respectively at 1:1 atomic ratios (La:Al and Hf:Al, respectively). The crystallization temperature and phases observed depend on the composition, with lower crystallization temperatures typically observed at compositions close to the binary oxides. Hf-rich HfAlO films crystallize into predominantly cubic Hf(Al)O2 (Tcrsyt 800C at 70% Hf/(Hf + Al)), with lattice parameter shifts correlated to Al content up to 30% Al, suggesting incorporation of Al in solution in the cubic phase. For higher Al contents, the crystallization temperature increases and the presence of c-Al2O3 is detected (XRD and TEM analysis), clearly indicating phase separation in the films. The lattice parameter of the cubic Hf(Al)O2 returns towards that of pure HfO2 with increasing Al content or anneal temperature. Shallow traps associated with the presence of Hf result in poor retention characteristics for devices with HfAlO IPD [26]. In addition to the bulk properties of the dielectric, the interfacial properties are also important in determining the behavior of flash devices [27]. For this reason, the interaction of the high-k dielectrics with different layers (such as SiO2/poly-Si for FG devices), upon annealing, was also characterized in detail, both physically and electrically. LaAlO, binary RE oxides and the RE scandates have been found to form silicates when reacted with SiO2 layers in inert ambients, or with Si in an oxidizing ambient [28,29]. Even when moderate anneal temperatures are used (e.g. 800 °C), reaction with interfacial SiO2 is observed. As an example of the study of layer interactions, Fig. 12 shows Time-Of-Flight Secondary Ion Mass Spectrometry (TOFSIMS) depth profiles of a stack of DyScO/ Al2O3/SiO2/Si after different thermal treatments. Interdiffusion is already observed at 850 °C, and becomes more pronounced after annealing at 1000 °C, modifying the properties of all layers in the stack.

crystalline DyScO GdScO

10

800oC PDA

5 0

0.25

0.5

0.75

a 1

%RE in REScO Fig. 10. Dielectric constant vs. composition for DyScO and GdScO films.

18 nm DyScO/5 nm γγ-Al -Al2O3/1 nm SiO2/Si

Intensity (A.U.)

Energy from Al2O3 band edge (eV)

a) γ-Al2O3

1.E+05

105

Sc 1.E+04

104

1.E+03 3 10

2 1.E+02 10

Intensity (A.U.)

b

Dy

as dep. 850 oC 1000 oC

1.E+05 0

105

5000

10000

15000

20000

25000

30000

35000

Depth Al(A.U.)

1.E+04

104

103

1.E+03

Si

102

1.E+02

as dep. 850 oC 1000 oC

101

1.E+01

100

1.E+00

0

Fig. 11. Internal photoemission/photoconductivity spectra of LaAlO films.

5000

10000

15000

20000

25000

Depth (A.U.)

30000

35000

Fig. 12. TOFSIMS depth profiles showing the intermixing in a DyScO/Al2O3/SiO2/Si stack after annealing at 850 and 1000 °C.

J.A. Kittl et al. / Microelectronic Engineering 86 (2009) 1789–1795

4. Summary An overview of requirements and development work on high-k dielectrics for applications in flash cells and DRAM MIMCaps was presented, highlighting the main challenges faced. For DRAM MIMCaps, EOT scaling towards 0.3 nm requires dielectrics with k-values >50, while processing temperatures need to remain <650 °C. These conditions are used as first screening criteria. Due to the high aspect ratio of the DRAM MIMCaps, highly conformal ALD techniques are studied for film growth. SrTiO3 appears as one of the most promising candidates, while HfTiO4 and (Nb–Ta)2O5 may provide intermediate solutions. Dielectrics with k-values in the 9–30 range are investigated for flash applications as IPD in FG memories or BO in CT memories. For flash, achieving adequate band offsets as well as low trap densities are key criteria for selection of the dielectric. Al2O3 was presented as reference material, as well as examples from the evaluation of aluminates and rare earth scandates. References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10]

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