High Level Synthesis Design Methodologies for Rapid Prototyping Digital Control Systems

High Level Synthesis Design Methodologies for Rapid Prototyping Digital Control Systems First A. Imène MHADHBI*. Second B. Ahmed ACHBALLAH**, Third C. Slim BEN SAOUD*** 

* LSA EPT-INSAT, Center urbain nord, B.P. 676, 1080 Tunis Cedex, Tunisia; ( e-mail: [email protected]). ** LSA EPT-INSAT, Center urbain nord, B.P. 676, 1080 Tunis Cedex, Tunisia; (e-mail:[email protected]) *** LSA EPT-INSAT, Center urbain nord, B.P. 676, 1080 Tunis Cedex, Tunisia, (e-mail: [email protected]) Abstract: Embedded systems are becoming an important factor of the electronic industry growth due to the higher integration scale of Field Programmable Gate Array (FPGAs). Their designs require high level synthesis (HLS) methodologies to decrease their complexity and design time. In this paper, we discussed a case study of two approaches of HLS design processes approaches. The first one employs Model-Based Design (MBD) flow. The second one uses C-Based Design flow. Both designs were validated on two control drive applications: DC and AC motors. The results indicate the most efficient design methodology. Keywords: Design Methodology, High Level Synthesis, Model-Based Design, C-Based Design, Performance. 

1.

INTRODUCTION

The exponential advances of microelectronics and semiconductor technologies have enabled to increase the integration capacity level of digital circuits allowing the implementation of complex applications related to image processing (Sánchez et al., 2007), aerospace and industrial control systems (Naouar et al., 2007; Salem et al., 2010; Monmasson et al., 2007). In the control domain, an important research and significant improvements have been achieved. Researchers have increasingly developed new complex and sophisticated algorithms to increase their performances such as self-adaptative control (Li et al., 2008), neuronal control and fuzzy logic control (Zerikat et al., 2005). The implementation of such control algorithms is much easier on the latest generation of Digital Signal Processors (DSPs). However, they can no answer the new generation of control applications that require higher performance and more flexibility (Salem et al., 2010). The advantage of FPGAs (flexible architectures, lower-cost, faster processing speed) and the increasing complexity of control algorithms are conducting to a drastic change in the design methodologies. The design challenge, in this area, is how to increase the performance of control systems by a high abstraction of their implementation details in order to reduce complexity and minimize the design time without increasing cost and resources. HLS, the main object of this paper, allows the fast prototyping of complex algorithms on FPGAs. Its principal objective is to simplify complex algorithms by converting them to hardware (HW) description using HLS tools. These tools generate automatically HW synthesized code i.e. VHDL

or Verilog, from a high level language like C, C++, Matlab, etc... Various HLS approaches have been used to design embedded systems. In this paper, the MBD, using XSG (Xilinx Datasheets and Tutorials, 2011), and the C-Based Design, using CoDeveloper™ (Impulse Accelerate Technologies, 2010), approaches present potential solutions to implement real control applications. Our study provides a comparison between two HLS implementation approaches of DC and AC motors, in terms of flexibility and consumption resources based on the effect of the data type precision. The remainder of this paper is organized as follows. Section 2 presents the related works of this paper. Section 3 provides a brief description of the processes of DC and AC motors controllers processes. Section 4 details the MBD and the CBased Design HLS approaches and the data type precision effects on these HLS approaches. Section 5 shows and discusses the synthesis results obtained from the proposed design methodologies using different data type precision. Section 6 concludes the work and exposes perspectives. 2.

RELATED WORKS

The related works, pertaining to this paper, can be divided on two different partitions: The FPGA design methodology challenges and the effect of the data type precision on the FPGA area consumption. 2.1 FPGA design methodology challenges The control of industrial electrical systems has been the focus of important research and many significant improvements.

Reducing the migration time from the algorithm development language to the HW specification language is the objective of designers. Early works are focused on how to speed up design prototyping by an automation of the Register Transfer Level (RTL) generation process from the behavioural description level using commercial tools (Wang et al., 2011). Others are based on the reusability of the intellectual propriety (IP) blocks or cores, provided by the FPGA vendors or designers, to ensure efficient implementation of complex functions and reducing the development time (Kean et al., 2002). During the last decades, HLS design methodology has been a main subject for research. Its principal objective is to simplify the HW design of accelerators by describing applications at high abstraction levels and generating the corresponding low level implementations. Several researches, based on a comparison between the HLS approaches and the traditional design flow, were qualified benefits of adopting HLS methodology in terms of design time and resources consumption (Moreo et al., 2005; Sluiky et al., 2001). The Choice of the HLS approach and tool to design complex systems is a very hard step. It’s based on the compromise between three needs: 1) Reduce power and HW resources consumption. 2) Provide more flexibility and faster design time. 3) Support more data type precisions A comparison between HLS approaches will serve as basis for rapid prototyping of any kind of control algorithms for high performance and design flexibility. 2.2 Data type precision FPGA technology has been widely adopted to speed up computationally intensive applications (Verma et al., 2009). Unfortunately, the capability of running floating point applications on an FPGA is limited due to their size. Floating point HW offers a wide dynamic range and high computation precision, but it occupies large fractions of total chip area and energy (Kum K. et al., 2010). Its usage permits a huge precision compared to the fixed-point precision. Several designs require the use of fixed-point arithmetic in order to satisfy cost, flexibility, design time constraints and HW occupation required by these applications (Mailloux et al., 2007). In fact, the flexibility of fixed-point data precision, in the HLS design methodologies, ensures a good precision, performing design with an optimized FPGAs area consumption. This paper describes a case study comparing the two HLS approaches (C-Based Design and MBD) in terms of FPGAs resources consumption. We are interesting to minimize the word-Lenght data, as possible, to reduce the HW cost: That’s why the choice of the data precision (Fig. 1) presents an important step on our design flow.

Algorithm specification

Choose HLS approach

Choose Data Type Precision

Simulation

HDL code Generation

FPGAs Implementation

Fig. 1. Proposed design flow. In the next section, we introduce the concept of the two HLS methodologies. 3.

HLS APPROACHES

HLS approaches are often used to rapid prototyping embedded systems in order to reduce the cost implementation and increase its performances by abstracting the design level and automate the HW code generation (Achballah et al., 2010; Sharma et al., 2009). Different approaches are used to design embedded systems. In our study, the C-based design and the MBD approaches present potentials solutions to synthesis control applications due to their abstraction level. 3.1 C-Based Design This HLS approach consists on the automatic generation of synthesized HW code (VHDL or Verilog), ready to be implemented on FPGA, from a C/C++ language (Agarwal et al., 2009). Recent development of C-to-HDL compiler technology has minimized the gap between software developer’s experience-level and the expertise needed to produce HW applications. Many commercial and academic C-Based Design tools can be found in the literature. In this study, we chose the CoDeveloper™ tool. 3.2 MBD MBD emphasizes the use of models to increase the abstraction level and design complex systems. The design model used in the systems engineering, includes safety critical domains like aerospace, automotive, etc. One of the most potential tools used in this domain is XSG. The development using models can be easily compared to programming languages: It enables the modelling and the verification of each function separately. Following, we present a brief informal description of the case study of this paper: The control systems (DC and AC motors). 4.

DESIGN CASE STUDY: CONTROL SYSTEMS

Embedded control systems are widely used in industrial applications. Their design presents an interesting area of research. In this paper, two electric motor drives have been designed; A DC motor driven by Proportional Integral (PI)

controllers and a more complex controls systems: AC motor driven by a Filed-Oriented Control (FOC) command. 4.1 DC motor process The DC electrical real time motor is based on two proportional integrator controllers (PI) and an emulator process (Fig. 2). The control unit employs a speed reference entered by the user to compute adequate duty cycle (alpha) alimented the shopper to supplies voltage (Vh) to the emulator. The current machine (Im) and the speed machine (Wm) values present the current and the speed control feedback (Salem et al., 2010). Iréf

Wréf PI Speed Controller

alpha

PI Current Controller

The FOC components operate at different update rates; The PI current controllers run every 300µs while PI speed controllers run every 1.2ms. However, the AC emulator runs every 100µs. 5.

HLS DESIGN OF CONTROL SYSTEMS

The HLS design methodology tend to encapsulate general programming languages because they are more easily understandable by experts in the applicative field. They hide, also, the details implementation and allow the simulation and the verification processes. High level of abstraction enables to verify/validate solution before adding implementation details. In this paper, we choose the two tools: XSG (MBD approach) and CoDeveloper™ (C-Based design approach). 5.1 Design control systems using CoDeveloper™

Im

Wm

Vh DCE

Shopper

Wréf : Reference speed/ Iréf : referencecourant

Fig. 2. DC motor drive. The sample time of DC motor components is different: The PI current controller run every 20ms, the PI speed controller every 300µs and the DC emulator runs every 100µs. 4.2 AC motor process The choice of the FOC vector control is interesting for rapid prototyping systems. It presents an interesting challenge and a good test case of the design methodologies. The concept of the FOC method (Fig. 3) is based on transforming equations of the three-phase induction motor in order to allow the control for flux and torque (Salem et al., 2010). Inverter

Vs2

vs1

T-1

is1 Park/Clarck Transformation

is2

PI QCurrent Controller

isq

vsdref

Imre PI Speed Controlle r

PI DCurrent Controller

Speed_ref

Fig. 3. FOC command.

Defluxing

isd

vs1, vs2, vs3 Producer SW Process

Wm

Producer HW Process

Cem

Consumer SW Process

is1, is2, is3

isdref

femd

Consumer SW Process

Fig. 4. Input/output DC emulator streams interconnection. Flux Estimator

femq

vsd

Producer HW Process Omegam

isqref

vsqref

Producer SW Process

Im

T

iisd isq Theta, Thetav

vsq

The Development of DC and AC emulator using CoDeveloper™ is based on a Communicating Sequential Processes (CSP). Each process is presented as HW or a software process. The HW process will be translated to a HW description while the software process will serve as a simulation monitor (Fig. 4 and Fig. 5). Respecting the syntax ImpulseC, the two algorithms was written using the adequate duty cycle(alpha), the current machine (Im) and the speed machine (Wm) as a software process. However, the threephase voltage(vs1, vs2, vs3), the speed machine(Wm), electromagnetic torque (Cem) and three-phase current(is1, is2, is3) are presentes as a software process for the AC emulator. alpha

Inverter’s Control PWM Vs3

CoDeveloper™ is a commercialized by Impulse Accelerated Technologies in the CAD market (Achballah et al., 2010). It’s a C-to-HDL compiler provided by Impulse Accelerated Technology (IAT). ImpulseC code, the input language of CoDeveloper™, can be written and debugged in any ANSI standard C environment, using both fixed and floating point data point types (Impulse Accelerated Technologies, 2011).

Imre

Fig. 5. Input/output DC and AC emulator streams interconnection. 5.2 Design control systems using XSG XSG, provided by Xilinx, enables to design embedded systems for FPGAs using fixed-point data type. It generates a synthesized HW Description Language (HDL) or directly a

bitstream that can be implemented in the FPGA. Development of DC and AC motors, using XSG, is based on an algorithm’s specification written on a Matlab language using Mcode. The Fig. 6, Fig. 7, Fig. 8 and Fig. 9 illustrate the models of the DC and AC emulators and motors using Matlab/Simulink (version 2008a) and XSG (version 11.1).

The objective of this research focus on which of these HLS tools can integrate complex control systems with a limited embedded resources, based on different data type Prec (precision) illustrated in the Table. 2 and Table. 3. Table 1. DC/AC emulator data precision DC emulator Number Signdness Fraction length

AC emulator

Prec_1 32bit

Prec_2 20bit

Prec_1 32bit

Prec_2 31bit

1bit 10bit

1bit 10bit

1bit 19bit

1bit 17bit

Table 2. DC/AC motors data precision Fig. 6. DC emulator model.

DC motor Number Signdness Fraction length

Prec_1 32bit 1 bit 10 bit 6.

Fig. 7. AC emulator model.

Fig. 8. DC motor model.

Prec_2 20 bit 1 bit 10 bit

FOC Prec_1 32 bit 1 bit 16 bit

RESULTS

The HLS design methodologies should provide a way of assessing of control systems to validate its good functionality using different data precision. Implementing control systems using XSG models is easier then hand coding using CoDevelopeTM: The XSG blocks can be simulated separately and modified by adding or suppressing functionalities for each blocks. Although, using C-Based Design approach, based on a like-C program, allows a high degree of abstraction without increasing flexibility compared to the MBD approach, the time required to develop AC and DC motors using XSG is shorter compared to CoDeveloper™ tool. The main objective of this paper presents a comparison between the performances of the HW code generated by the two HLS tools in terms of HW resources consumption and data type precision on the designing of DC and AC motors. 6.1 Data type effect The minimization of the word-length precision allows good FPGAs resources consumption without effecting on the control systems. The superposition of the speed responses using the two data fixed-point precision is verified by the computing the difference between the two precisions for both DC and AC emulators’ responses. The error diagrams (Fig. 10 and Fig. 11) prove that the error curves do not exceed the 10% for the DC emulator using a duty cycle (alpha) fixed at (70%) and (18%) for the AC emulator.

Fig. 9. AC motor model.

The design and the implementation of the AC emulator and the FOC command algorithms present an interesting challenge. In fact, their complexities and their modularity provide a huge utilization of FPGA area comparing to the DC emulator and the DC motor. As mentioned on the Fig. 12 and the Fig. 13, the FPGA area consumption of the DC motor and the FOC command, confirm that: Developing complex algorithms using XSG minimize the FPGAs resources utilization comparing to CoDeveloper™. 35% 30% 25% 20%

Fig. 10. Error DC emulator speed curves.

15%

Slices

10%

LUTs

5%

IOBs

0% Prec_1 Prec_2 Prec_2

FP

DC Emulator XSG

Prec_1

DSP48Es

DCM Codeveloper

XSG

Fig. 12. Synthesis results for DC emulator and DC motor. 160% 140% 120% 100% 80%

Fig. 11. Error AC emulator speed curves.

Slices

60%

LUTs

40%

The Fig. 13 indicates that the number of DSP48Es is 153% using the floating-point precision comparing to 90%and 37% using the two fixed-point precisions. Excess of the embedded FPGA resources utilization, on the implementation of AC emulator, prove that the data precision allows a good FPGA area consumption without affecting on the control systems. 6.2 HW resources consumption After design verification, the HW codes generated are intended to be synthesized, using Integrated Software Environment (ISE) from Xilinx, in order to evaluate which of the HLS tools allows the most optimized code generation. The FPGA technology was allowed a quick implementation and verification which is the reason of the choice of the FPGA Virtex-5 technology, available in our research laboratory, as the target technology. It offer the best solution for addressing the needs of high-performance logic, highperformance DSP, high-performance embedded, hard/soft microprocessor, and connectivity capabilities. The first observation of synthesis results (Fig. 12 and Fig. 13), prove that using reduced bit-width can provide significant savings of the HW resources consumption for both DC and AC motors.

IOBs

20%

DSP48Es

0% prec_1 prec_2 prec_2

FP

ACE

prec_2 FOC

XSG

Codeveloper

XSG

Fig. 13. Synthesis results for AC emulator and the FOC command. Synthesis results prove that developer, using XSG, can mainly implement complex algorithms with a high level abstraction. The consumption of FPGAs resources, using XSG, is due to the role of XSG which is the generation of a synthesizable HW code ready to be implemented on FPGAs, besides, CoDeveloper™ which only focus, on the portability of the generated code and does not take architecture of the design into consideration. 7.

CONCLUSIONS

The high complexity of such modern embedded systems, the low cost and the strict time-to-market constraints in the electronics industry motivated the use of the HLS methodology approaches (the main subject of this research)

to rapid prototyping control drive applications and make use of the FPGA technology features. In this paper, we presented a case study examining and comparing the two HLS approaches: C-Based Design (Codeveloper™) and MBD (XSG) applied on two embedded control motors systems, such as DC and AC motors. Results demonstrate that HLS methodologies enable designers to implement advanced machine drive algorithm including complex computing such as AC motors, with good data precision and low FPGA area consumption. They show the efficiently and the performance of the MBD approach using XSG tool to prototype complex systems with a high level of abstraction and a low area consumption comparing to the CBased Design using Codeveloper™ design tool. REFERENCES Agarwal, A. (2009). Comparaison of high level design methodologies for arithmetic IPs: Bluespec and C-based synthesis. Master of Science in Electrical Engineering and Computer Science. Massachusetts Institute of technology. Achaballah, B. A., Othmen, B. S., and Saoud B. S. (2010). High Level Synthesis of Real Time Embedded Emulating System for Motor Controller. International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Hammamet, Tunisia, page 16. Salem, B. A. K., Othman, B. S., and Saoud, B. S. (2009). Field Programmable Gate Array -Based System-on-Chip for Real-Time Power Process Control. American Journal of Applied Sciences, volume (7), page 127-139. Wang, F., Chen, Y., and Takach, A. (2011). Variation-aware Task Allocation and Scheduling for MPSoC. IEEE Transactions on CAD (TCAD), volume (30), page 259307. Impulse Accelerated Technologies (2011) Available at: www.implsec.com. Kum, K., Sung, W. (2001). Combined Word-Length Optimization and High-Level Synthesis of Digital Signal. IEEE transactions on computer-aided design of integrated circuits and systems, volume (20), page 921930. Kean, T.O.M. (2002). Cryptographic rights management of FPGA intellectual property cores. FPGA Monterey, CA, USA, page 24–26. Li, C., Ban, H. and Shen, W. (2008). Self-adaptive control system of grain drying device, Drying Technology, volume (26), page 1351–1354. Mailloux, J. B., Simard, S. and Beguenane, R. (2007). FPGA implementation of induction motor vector control using Xilinx System Generator. 6th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing, Cairo, Egypt, page 29–31. Moreo, A.T., Lorent, P.N., Valles, F.S., Muro, J.S. and Andres, C.F. (2005). Experiences on developing computer vision HW algorithms using Xilinx System Generator, Microprocessors and Microsystems, volume (29), page 411–419.

Monmasson, E., Cirstea, M. N. (2007). FPGA Design Methodology for Industrial Control Systems—A Review, IEEE Transaction on Industrial Electronics, vol. (54), page 1824-1842. Naouar, M. W., Monmasson, E., Naassani A. A., SlamaBelkhodja I., and Patin, N. (2007). FPGA-Based Current Controllers for AC Machine Drives—A Review, IEEE transactions of industrial electronics, volume (54), page 1907 – 1925. Sánchez, A.M.G., Alvarez, G.R., Sánchez G.S., FCC and FCE BUAP. (2007). Architecture for filtering images using Xilinx System Generator, Int. J. Mathematics and Computers in Simulation, volume (1), page 101–107. Sluiky, V., Ziberkas, G., Damasevicius, R. and Majauskas, G. (2001). Two approaches for developing generic components in VHDL, Microelectronics Journal, volume (33), page 271–277. Sharma, S. and Chen, W. (2009). Using model-based design to accelerate FPGA development for automotive applications, SAE International Journal of Passenger Cars – Electronic and Electrical Systems, volume (2), page 150–158. Verma, A., Dhingra, S. and Soni, M.K. (2009). Design and synthesis of FPGA for speed control of induction motor, Int. J. Physical Science, volume (4), No.(11), page 645– 650. Xilinx Datasheets and tutorials (2011) Available at www.xilinx.com. Zerikat, M., Bendjebbar, M. and Benouzza, N. (2005). Dynamic fuzzy-neural network controller for induction motor drive, World Academy of Science, Engineering and Technology, volume (10), page 278–283.