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High output dynamic range exponential function synthesizer
Microelectronics Journal 63 (2017) 123–130
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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
High output dynamic range exponential function synthesizer Cosmin Radu Popa
MARK
Faculty of Electronics, Telecommunications and Information Technology, Bucharest, Romania
A R T I C L E I N F O
A B S T R A C T
Keywords: Exponential function Analog signal processing Low-voltage low-power circuits Approximation functions Variable changing Current-mode operation
The paper presents two original high-accuracy exponential function synthesizers with wide output dynamic ranges. The improved accuracies of the proposed computational structures are obtained using new superiororder approximation functions. In order to additionally improve the circuits' output dynamic ranges, an original method based on proper variable changing will be used and implemented. As a result of the new proposed design methods, the performances of the exponential structures are only slightly affected by technological errors. The best original proposed architecture of the exponential synthesizer has an output dynamic range of 100 dB, for an approximation error smaller than ± 1 dB. The exponential circuits are designed for implementing in 0.18 µm CMOS technology and they present a low-voltage low-power operation – the minimal supply voltage is about 0.7 V, while the power consumption is smaller than 2 μW. The chip area is about 4.5 µm2 for an implementation in 0.18 µm CMOS technology of the best proposed exponential circuit.
1. Introduction A very important function used in signal processing, finding a multitude of applications in VLSI designs, is represented by the exponential function [1–35]. The previously reported methods for generating the exponential function using CMOS circuits can be grouped in two classes. The first class of exponential function synthesizers uses the limited Taylor series expansion for obtaining the exponential function, having the main disadvantage of a relatively small output dynamic range (smaller than 30dB ) because of the limitations related to circuit complexity. Most of circuits [1–17] use the second-order approximation, only some of them [18,19] are based on the third-order approximation of the exponential function and present a smaller approximation error comparing with previous ones. Other exponential computational structures [21–32] use different forms of approximation functions for generating the exponential function. The relation between the circuits' accuracy and the complexity of their CMOS implementation is favorable to the exponential function synthesizers using approximation functions, comparing with the exponential circuits based on limited Taylor series expansions. However, the disadvantage of a relatively large approximation error still represents an important problem of this second class of exponential function synthesizers, as a result of their small order of approximation. The most used in literature exponential function approximation functions are presented in (1) [21–27,34] - output dynamic range smaller than 26dB , (2) [28–30,34] - output dynamic range of about 45 − 47dB (K and a being parameters), (3) [31,32,34] - output dynamic range smaller than 30dB (with a and b being parameters that can be controlled by the designer) or (4) [34], having an output dynamic range smaller
than 40dB . All of these previously reported exponential function synthesizers use second-order or third-order approximation functions, in order to reduce the silicon area of the circuit. The results is a relatively small output dynamic range of the exponential structures designed using these approximation functions, that drastically limits the area of applications for the developed exponential function synthesizers.
e1 (x ) =
1+x ≅ exp (2x ) 1−x
(1)
e2 (x ) =
K + (1 + ax )2 K + (1 − ax )2
(2)
e3 (x ) =
1 + ax 1 + bx
(3)
e4 (x ) =
1 + ax + cx 1 + bx
(4)
In this paper, it will be introduced and developed a new more accurately fourth-order approximation function, having the advantage of a reduced complexity and of a wide output dynamic range. The current-mode operation and the biasing in saturation of all MOS transistors that compose the proposed exponential function synthesizer are responsible for a very good frequency response of the circuit. The biasing in strong inversion (saturation region) of all MOS transistors is chosen in order to improve the frequency response of the developed exponential function synthesizer. The utilization of the new proposed fourth-order high-accuracy approximation function for generating the exponential function allows to use approximately the same chip area for its CMOS implementation,
http://dx.doi.org/10.1016/j.mejo.2017.03.013 Received 3 November 2015; Received in revised form 25 January 2017; Accepted 29 March 2017 0026-2692/ © 2017 Elsevier Ltd. All rights reserved.
Microelectronics Journal 63 (2017) 123–130
C.R. Popa
comparing with previously reported third-order exponential function synthesizers, based on classical method of approximation. As the original developed exponential function synthesizer uses a higher-order (fourth-order) of approximation, its accuracy and, additionally, its output dynamic range will be much better comparing with previous similar works.
The IA and IB currents are the input currents of the squaring circuit, while a represents a constant coefficient that depends on the particular implementation of the circuit. Using particular values of input currents: IA = IO + bIIN and IB = cIO , it is simple to generate, using a current squaring circuit with small complexity, an output current expressed as follows:
2. Theoretical analysis
IC = IO
c2 1 a 1 + b IIN I
(6)
O
The original proposed exponential function circuits generate the exponential function using new developed fourth-order approximation functions. As a result of the fourth-order approximation, the output dynamic ranges of the proposed circuits are strongly increased comparing with the previous reported similar circuits. In order to additionally increase the output dynamic range of the new designed circuits, an original variable changing will be used, allowing an important reduction of the effective range of the input variable. The new proposed approximation methods allow extremely simple implementations in CMOS technology, using only two, respectively four current-mode squaring circuits, their total complexity being comparable with the complexity of previously reported exponential circuits with only second-order approximation and much poorer performances.
In conclusion, new approximation functions will be obtained considering a finite number of primitive functions, having the general expressions derived from (6), 1/(1 + bk x ). The x variable is defined as the ratio between the input current and the reference current, x = IIN / IO . The number and the form of primitive functions that will represent the basis for synthesizing the approximation function is imposed by the necessity that its Taylor series must fulfilled the Taylor series of the exponential function. Evidently, the improving of the circuit accuracy can be made by increasing the number of primitive functions and, in consequence, the complexity of the exponential function synthesizer. Because the absolute value of a superior-order term from a Taylor series expansion strongly decreases when the order of approximation increases, the fourth-order term from the Taylor series expansion of a continuous function will be much smaller (in absolute value) than the constant, linear, second-order and third-order terms from the same expansions. The additional consideration of the fifth-order term produces only a very small increasing of the approximation accuracy, but strongly increases the complexity of the computational circuits that will implement the approximation function. In consequence, taking into account a convenient tradeoff between the accuracy of approximation using a limited Taylor series expansion and the complexity of the implementation in CMOS technology of the approximation function, an optimal choice that permits to obtain a very good accuracy and a very large dynamic output range of the exponential function synthesizer circuit, using a reasonable circuit complexity will be based on a fourthorder approximation of the exponential function. The original proposed general form of the approximation function (which is able to fourthorder approximate a multitude of continuous mathematical functions) will be synthesized using two primitive functions and two additional linear terms. having the following general expression:
2.1. Synthesis and implementation of the first approximation function In order to synthesize the general form of the approximation functions that will be used for generating the exponential function, some requirements must be fulfilled. The most important conditions that are imposed to the approximation function are related to its capability to simulate with a very good accuracy the exponential function, correlated to the need for an extended dynamic output range for the designed computational structure. These performances have to be obtained using a reasonable complexity of the exponential function synthesizer. Usually, the increasing of the accuracy of approximation produces an important increasing of the complexity for the circuits that implement in CMOS technology the approximation function. From this point of view, a tradeoff between the acceptable complexity of the exponential function synthesizer and its overall accuracy must be habitually made. The new proposed method of synthesis the approximation function has the advantage of presenting an extremely low approximation error, this performance being obtained using a reasonable circuit complexity. This is possible by exclusively using in the circuit implementation of currentmode squaring circuits and of current mirror circuits, having relatively small intrinsic complexities in CMOS technology. Additionally, the original expression of the approximation function further reduces the circuit complexity. The current-mode operation of the proposed exponential function synthesizers and the independence of their output signal on technological parameters and on temperature variations contribute to a supplementary increasing of the circuits’ accuracy, allowing to decrease the order of approximation, while maintaining, however, the accuracy of the computational structure. The necessity of the exclusively use in the implementation of the exponential function synthesizers of MOS transistors biased in saturation region is imposed by the requirements for a good frequency response of the proposed exponential circuits. In the same situation, the current-mode operation strongly improves the frequency response of the proposed circuits. The original proposed mathematical forms of the approximation function are synthesized starting from the general expression of the IC output current of a current squaring circuit (because the squaring function is the most convenient choice for implementing in CMOS technology):
IC =
IB2 aIA
⎛I ⎞ a1 a3 I + + a4 IN + a5 f1 ⎜ IN ⎟ = IIN ⎝ IO ⎠ 1 + a2 IIN IO 1 + I I O
O
(7)
The reason for choosing the previous general form of the approximation function is related to its facile CMOS implementation and to its complete definition using a number of five coefficients (a1 to a5). In order to obtain the values of these coefficients (in the particular case of approximating the exponential function), the identity between the first five terms from the Taylor series of the approximation function and, respectively, of the exponential function must be considered (constant term, linear term and second, third and fourth-order terms). Solving the system imposed by the previous identities, it results the following expression of the fourth-order approximation function:
⎛I ⎞ 26 1 1 1 7I 21 + − IN − f1 ⎜ IN ⎟ = ⎝ IO ⎠ 5 1 − 5IIN 128 1 + IIN 11IO 5 I 16I O
O
(8)
The comparison between f1 (x ) first approximation function and exp(x ) function is presented in Table 1, showing a wide decibel linear range of 33dB , for a deviation from the exponential characteristic of 1dB . A graphical comparison between f1 (x ) approximation function and exp(x ) function is presented in Fig. 1, illustrating a good fitting of f1 (x ) function with the exponential function. The original proposed exponential function synthesizer permits a facile reconfiguration, the generation of any continuous mathematical
(5) 124
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resulting:
Table 1 Comparison between f1 (x ) and exp(x ) functions. x
f1 (x) [dB]
exp (x) [dB]
ε [dB]
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.65
0.16 2.11 4.07 6.05 8.03 10.02 12.01 14.01 16.03 18.05 20.09 22.15 24.24 26.35 28.49 30.68 32.91 34.01
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 33
0.16 0.11 0.07 0.05 0.03 0.02 0.01 0.01 0.03 0.05 0.09 0.15 0.24 0.35 0.49 0.68 0.91 1.01
I = IA −
(10)
In order to generate the squaring term from the previous relation, all MOS transistors from Fig. 2 have to be biased in saturation region and, correlated with this condition, the supply voltage must be greater than the minimal value expressed by: (11)
VDDmin = 3VGS 4 − VT
Additionally, the potential in the drain of M5 transistor (imposed by the output circuit that uses IC current) must have a convenient value, that allows M5 and M8 transistors to be also biased in saturation region. The expression of the IC output current is:
IC = 2I + IB − 2IA =
IB2 8IA
(12)
M1–M7 MOS devices from Fig. 2 have an aspect ratio (W/L) =0.18 µm/0.5 µm, while M8 transistor has an aspect ratio (W/L) =0.36 µm/0.5 µm. The first squaring circuit presents the advantage of the independence of the output current on technological parameters and on temperature variations, this fact improving the circuit accuracy. The frequency response of the squaring circuit is improved as a consequence of the current-mode operation of the circuit. The symbolical representation of the first squaring circuit is presented in Fig. 3. The original proposed block diagram for implementing the first fourth-order exponential function synthesizer based on the new proposed approximation function f1 (x ), expressed by (8) is presented in Fig. 4. It is based on the first new approximation function expressed by (8) and on the first proposed realization of the squaring circuit, presented in Fig. 2. The output current of the first exponential function synthesizer can be expressed as follows:
Fig. 1. Graphical comparison between f1 (x ) and exp(x ) functions.
IOUT = IC 2 − IC1 −
function being possible using relation (7) by changing of the approximation function coefficients, in accordance with the Taylor series of each particular function. The core for implementing the exponential function synthesizer is represented by a first current-mode squaring circuit, having the proposed realization presented in Fig. 2. Noting with VGS (ID ) the gate-source voltage of a MOS transistor biased in saturation, at a drain current equal with ID , the translinear loop that establishes the operation of the squaring circuit can be expressed as follows:
2VGS (IA) = VGS (I ) + VGS (I + IB )
I2 IB + B 2 16IA
7 21 IIN − IO 11 5
(13)
Using the functional relation (11) for both squaring circuits from Fig. 4, the expression of the output current becomes:
⎛I ⎞ ⎛I ⎞ IOUT (IIN ) = IO f1 ⎜ IN ⎟ ≅ IO exp ⎜ IN ⎟ ⎝ IO ⎠ ⎝ IO ⎠
(14)
The CMOS implementation of the first exponential function synthesizer is presented in Fig. 5. The chip area of the proposed exponential function synthesizer, designed for implementing in CMOS 0.18μm technology, is about 3μm2 .
(9)
2.2. Synthesis and implementation of the second approximation function Starting from the first new proposed approximation function f1 (x ) (expressed by (8)), in order to increase the accuracy of the exponential function synthesis, a second original improved approximation function f2 (x ) will be developed. This second original approximation function f2 (x ) was obtained using the x − > x /4 variable changing and the particularity of the exponential function that exp 4 (x /4) = exp (x ). This original method will have the effect of fourth time reducing the effective range of variation for the input variable and, in consequence, of strongly increasing the output dynamic range of the exponential function synthesizer. Additionally, the full range of x input variable is IA IB
A B
SQ C
IC
Fig. 3. Symbolical representation of the first squaring circuit.
Fig. 2. Squaring circuit (first implementation).
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Table 2 Comparison between f2 (x ) and exp(x ) functions.
Fig. 4. Block diagram of the exponential function synthesizer based on f1 (x ) first approximation function.
split into two sub-ranges, each one corresponding to positive and, respectively, negative values of x . Each particular function ( f2a or f2b ) can better match the exponential function for its range of operation, supplementary increasing the output dynamic range of the exponential function synthesizer based on this original approximation function.
⎛ 26 1 1 1 f2a (x ) = ⎜⎜ − 5x 5 128 1 + 1 − ⎝ 64 ⎛ 26 1 1 1 f2b (x ) = ⎜⎜ − 5x 5 128 1 − 1 + ⎝ 64
x 4
⎞4 7x 21 ⎟ − − , x>0 44 5 ⎟⎠
(15)
x 4
⎞4 7x 21 ⎟ + − , x<0 44 5 ⎟⎠
(16)
The comparison between f2 (x ) approximation function and exp(x ) function is presented in Table 2, showing an extremely wide decibel linear range, greater than 100dB , for a deviation from the exponential characteristic of 1dB . A graphical comparison between f2 (x ) approximation function and exp(x ) function is presented in Fig. 6, illustrating a very good fitting of f2 (x ) function with the exponential function. The second new proposed CMOS current-mode squaring circuit is presented in Fig. 7. The IC current represents the output current of the circuit, IB - the input current and IA - an external applied reference current. The input and the output currents can be expressed as IB = I3 − I2 and IC = I2 + I3 − 2IO . The translinear loop containing M1÷M4 transistors has the following characteristic equation:
VGS1 + VGS 4 = VGS 2 + VGS 3
x
f2 (x) [dB]
exp (x) [dB]
ε [dB]
−5.8 −5 −4 −3 −2 −1 0 1 2 3 4 5 5.8
−51.36 −43.93 −34.90 −26.09 −17.40 −8.79 0.27 8.79 17.40 26.09 34.90 43.93 51.36
−50.41 −43.45 −34.77 −26.07 −17.38 −8.69 0 8.69 17.38 26.07 34.77 43.45 50.41
−1.05 −0.48 −0.13 −0.02 −0.02 −0.10 0.27 0.10 0.02 0.02 0.13 0.48 1.05
Fig. 6. Graphical comparison between f2 (x ) and exp(x ) functions.
to be neglectible the second-order effects that affect the MOS transistor operation, the circuit presented in Fig. 7 will generate an output current proportional with the square of the input current and independent on technological parameters and on temperature variations:
IC =
(17)
IB2 8IA
(18)
The quasi-independence on technological errors of the circuit operation was obtained as a consequence of the design method that
Imposing a biasing in saturation of MOS transistors and supposing
Fig. 5. CMOS implementation of the first exponential function synthesizer.
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IOUT 1 =
IO2 26 5 IO − 5IIN 64
(20)
IO2 1 128 IO + IIN 4
(21)
and:
IOUT 2 =
resulting:
IOUT 3 = IOUT 1 − IOUT 2 −
7IIN 21IO − 44 5
(22)
equivalent with:
⎛ 26 1 1 1 − IOUT 3 = IO ⎜⎜ 5x 5 128 1 + 1 − ⎝ 64
x 4
−
⎞ 7x 21 ⎟ − 44 5 ⎟⎠
(23)
The IOUT 4 current can be expressed as follows:
IOUT 4 =
Fig. 7. Squaring circuit (second implementation).
(24)
resulting:
has been used, based on a translinear loop containing two positive and two negative gate-source voltage of MOS transistors biased in saturation region. An important consequence of this particularity is represented by a quasi-independence of the circuit behavior on temperature variations. In order to generate the squaring term from the previous relation, all MOS transistors from Fig. 2 have to be biased in saturation region and, correlated with this condition, the supply voltage must be greater than the minimal value expressed by:
VDDmin = 3VGS1 − VT
2 IOUT 3 IO
IOUT =
2 IOUT I4 3 4 = OUT IO IO3
(25)
So, the output current will approximate the exponential function, using the more accurate f2a (x ) approximation function:
⎛ 26 1 1 1 IOUT (x ) = IO ⎜⎜ − 5x 128 1 + ⎝ 5 1 − 64
(19)
x 4
−
⎞4 7x 21 ⎟ − 44 5 ⎟⎠
(26)
In conclusion, the output current will be proportional with the exponential function, having as input variable the ratio between the input and the reference current:
Additionally, the potential in the drain of M2 transistor (imposed by the output circuit that uses IC current) must have a convenient value, that allows M2 and M3 transistors to be also biased in saturation region. Aspect ratios of all MOS transistors from Fig. 7 are (W/L) =0.18 µm/0.5 µm. The symbolical representation of the second squaring circuit is also presented in Fig. 3. The block diagram of the second exponential function synthesizer, based on f2a (x ) approximation function, is presented in Fig. 8. The chip area of the proposed exponential function synthesizer, designed for implementing in CMOS 0.18μm technology, is about 4.5μm2 . For implementing f2b (x ) function, useful for negative input variables x , the same block diagram must be used. The “SQ” blocks from Fig. 8 have the concrete implementations presented in Fig. 7. The expressions of IOUT1 and IOUT 2 currents are:
⎛I ⎞ ⎛I ⎞ IOUT (IIN ) = IO f2a ⎜ IN ⎟ ≅ IO exp ⎜ IN ⎟ ⎝ IO ⎠ ⎝ IO ⎠
(27)
2.3. Errors introduced by second-order effects The errors introduced in the operation of the squaring circuits from Figs. 2 and 7 are: the mismatches, channel effect modulation, body effect and mobility degradation. Taking into account the channel effect modulation, the gate-source voltage of a MOS transistor biased in saturation region can be expressed as follows:
VGS = VT +
2ID K (1 + λVDS )
(28)
Considering, additionally, the mismatches for VT and K parameters and taking into account the previous relations, it results that the expressions of squaring circuits’ output currents will be affected by a small additional error, ε1, that could be minimized using commoncentroid configurations for particular constitutive transistors of squaring structures:
IC =
IB2 + ε1 8IA
(29)
In order to minimize this error using the common-centroid technique, the aspect ratios (W/L) of all MOS devices must be changed by increasing Ws and Ls, while maintaining their ratios. Practically, a tradeoff between accuracy and complexity must be made, depending on each design requirements. For the squaring circuit presented in Fig. 2, ε1 error is smaller than 0.1%, while the same error for the squaring circuit proposed in Fig. 7 is smaller than 0.13%. The body effect errors can be evaluated considering the general
Fig. 8. Block diagram of the exponential function synthesizer. based on second f2a (x ) approximation function.
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dependence of the threshold voltage on the bulk-source voltage:
VT = VTO + γ ( Φ − VBS −
Φ)
(30)
VTO is the threshold voltage for VBS = 0 , γ is a technological parameter and Φ represents the Fermi potential. Considering, additionally, the mobility degradation effect, the gate-source voltage for a MOS transistor biased in saturation is expressed by: VGS = VT +
2ID θ + G ID K K
(31)
Taking into account the body effect and the mobility degradation, the output currents of the squaring circuits presented in Fig. 2 and in Fig. 7 will be affected by an additional error ε2 , depending on γ , Φ , K and θG model parameters and also on the circuit biasing currents:
IC =
IB2 + ε2 8IA
Fig. 10. Simulation of the IC (IA, IB ) squaring circuit dependence for IA = 0.1μA.
(32)
For the squaring circuit presented in Fig. 2, ε2 error is smaller than 0.12%, while the same error for the squaring circuit proposed in Fig. 7 is smaller than 0.15%. 3. Simulations Fig. 11. Simulation of the IOUT (IIN ) dependence for the exponential circuit presented in Fig. 5.
The operation of the functional squaring core from Fig. 2 is evaluated using actual simulation. The simulation of the IC (IB ) dependence expressed by (12) for IA = 0.1μA and a range of variation for IB current between −0.1μA and 0.1μA is presented in Fig. 9. The simulated error for implementing the squaring function (10) using the original proposed squaring core from Fig. 2 is 0.35%. The simulation is based on 0.18μm CMOS process, the supply voltage being equal with the minimal supply voltage, accepted by the proposed squaring circuit, VDD = 0.6V . The current consumption is smaller than 0.5μA for the full implementation of the new proposed squaring circuit. The operation of the functional squaring core from Fig. 7 is evaluated using actual simulation. The simulation of the IC (IB ) dependence expressed by (18) for IA = 0.1μA and a range of variation for IB current between −0.1μA and 0.1μA is presented in Fig. 9. The simulated error for implementing the squaring function (16) using the original proposed squaring core from Fig. 7 is 0.45%. The simulation is based on 0.18μm CMOS process, the supply voltage being equal with the minimal supply voltage, accepted by the proposed squaring circuit, VDD = 0.7V . The current consumption is smaller than 0.6μA for the full implementation of the new proposed squaring circuit (Fig. 10). The operation of the exponential circuit presented in Fig. 5, based on the new f1 (x ) approximation function, is evaluated using the simulation presented in Fig. 11. It shows the IOUT output current exponential dependence on the IIN input current. The IO reference current is 0.1μA, while the range of variation for the IIN input current is chosen between 0 and 0.4μA. The maximal simulated error for implementing the exponential function using the original proposed circuit is 0.8%. The simulation is based on 0.18μm CMOS process, the supply voltage being equal with the minimal supply voltage, accepted by the proposed squaring circuit, VDD = 0.7V .
A comparison between the previously reported exponential circuits and the second original proposed exponential structure is presented in Table 3. The new proposed approximation function allows an important increasing of the exponential circuit accuracy, associated with an increasing of the output dynamic range with at least 50dB (comparing with other previously reported exponential circuits). The power consumption smaller than 2μW recommends the proposed computational structures for low-power applications. The circuits are designed for a low voltage operation (a supply voltage of 0.7V ), this feature being obtained using specific design techniques. As a result of original design methods applied in synthesizing the architectures of the proposed exponential structures, the estimated performances are relatively stable with respect to process variations and with temperature drifts. The new specific expressions of the developed approximation functions, and also the original proposed implementation of the constitutive squaring blocks contribute to an important decreasing of the circuit silicon area comparing with other previously reported implementations of exponential circuits, having poorer performances. The effect of process and mismatch variations could be evaluated using Monte Carlo simulation results. 4. Conclusions There were presented two original high-accuracy exponential function synthesizers with wide output dynamic ranges. The improved accuracies of the proposed computational structures were obtained using new superior-order approximation functions. In order to additionally improve the circuits' output dynamic ranges, an original method based on proper variable changing was used and implemented. As a result of the new proposed design methods, the performances of the exponential structures were only slightly affected by technological errors. The best original proposed architecture of the exponential synthesizer has an output dynamic range of 100 dB, for an approximation error smaller than ± 1 dB. The exponential circuits are designed for implementing in 0.18 µm CMOS technology and they present a lowvoltage low-power operation - the minimal supply voltage is about 0.7 V, while the power consumption is smaller than 2 μW. The chip area is about 4.5 µm2 for an implementation in 0.18 µm CMOS technology of the best proposed exponential circuit. The new exponential function synthesizers have the possibility of
Fig. 9. Simulation of the IC (IA, IB ) squaring circuit dependence for IA = 0.1 μA .
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Table 3 Comparison between the previously reported exponential circuits and the second original proposed exponential structure. Reference/ parameter
Dynamic range [dB]
Error [dB]
Supply voltage [V]
Power consumption [mW]
Technology [μm]
Dependence on technology
Method of approximation
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] This work (Fig. 8)
25 35 16 20 20 15 20 12 17 15 26 20 14 17 15 20 12.8 45 46 47 20 45 100
± 0.5 ± 0.5 1 ± 0.5 ± 0.5 ± 0.5 ± 0.5 5 0.5 ± 0.5 0.5% 0.5 1 ± 0.5 ± 0.5 ± 0.5 5% ±1 ± 0.5 ± 0.5
1.25 1.25 1.5 3 1.25 1.25 3 1
0.1 0.3
0.25 0.25 0.5
0.2 0.015 0.9 0.0035 0.3 0.8 24.8 0.0064 12.5
0.25 0.25 1.2 0.35 0.09 0.35 0.35 0.25 0.5 0.18 0.5 0.5 2 0.18 0.25 0.13 0.09 0.5 0.18
Yes No Yes Yes No Yes Yes No No Yes Yes No Yes No yes Yes Yes Yes No Yes Yes No No
Taylor 2-nd order Taylor 2-nd order Taylor 2-nd order Taylor 2-nd order Taylor 2-nd order Taylor 2-nd order Taylor 2-nd order Taylor 2-nd order Taylor 2-nd order Taylor 2-nd order Approximation function (1) Approximation function (1) Approximation function (1) Approximation function (1) Approximation function (1) Approximation function (1) Approximation function (1) Approximation function (3) Approximation function (3) Approximation function (3) Approximation function (4) Approximation function (4) New approximation function (15), (16)
±1
± 1.5 1.5 0.9 3.3 0.8 ± 1.5 1.5 3 1.8 1.5 1.2 1.2 ± 1.5 0.7
0.4
7.56 0.8 3.6 0.72 1.2 0.002
converter using composite NMOS transistors, Electron. Lett. 36 (1) (2000) 8–10. [11] A. El Mourabit, M.H. Sbaa, CMOS exponential V-V converter with large DC operating range, Electron. Lett. 44 (15) (2008) 901–902. [12] S. Vlassis, CMOS current-mode pseudo-exponential function circuit, Electron. Lett. 37 (8) (2001) 471–472. [13] C.H. Kao, W.P. Lin, C.S. Hsieh, Low-voltage low-power current mode exponential circuit, Circuits Devices Syst. IEE Proc. (2005) 633–635. [14] Popa Cosmin, CMOS current-mode high-precision exponential circuit with improved frequency response, in: Proceedings of the IEEE-TTTC International Conference on Automation, Quality and Testing, Robotics AQTR 2004 (THETA 14), Cluj-Napoca, Romania, 2004, pp. 279–284. [15] Cosmin Popa, CMOS current-mode pseudo-exponential circuit with superior-order approximation, in: Proceedings of the IEEE Conference on Microelectronics, Electronics and Electronic Technologies, MIPRO, Croatia, 2005, pp. 95–98. [16] Popa Cosmin, High accuracy exponential function generator for analog signal processing, in: Proceedings of the 2005 NSTI Bio Nano Conference, Anaheim, California. [17] Popa Cosmin, Improved accuracy pseudo-exponential function generator with applications in analog signal processing, IEEE Trans. Very Large Scale Integr. Syst. 16 (3) (2008) 318–321. [18] Popa Cosmin, Improved accuracy pseudo-exponential with applications in analog signal processing, in: Proceedings of the International Conference on "Computer as a Tool, EUROCON, Belgrade, Serbia and Montenegro, 2005, pp. 1594–1597. [19] CMOS Pseudo-Exponential Circuit Based on A New Average Potential Principle, Popa, C., The 8th International Workshop on Symbolic Methods and Applications to Circuit Design, SMACD 2004, Poland. [20] CMOS Current-Mode Pseudo-Exponential Circuits with Superior-Order Approximation, Popa, C., IEEE-EURASIP Workshop on, Nonlinear Signal and Image Processing, Italy, 2003. [21] M.M. Green, S. Joshi, A 1.5 V CMOS VGA based on pseudo-differential structures, in: Proceedings of the ISCAS 2000 Geneva, The 2000 IEEE International Symposium on Circuits and Systems, vol. 4, 2000, pp. 461–464. [22] C.H. Kao, C.C. Tseng, C.S. Hsieh, Low-voltage exponential function converter, Circuits Devices Syst. IEE Proc. 152 (5) (2005) 485–487. [23] Po-Chiun Huang, Li-Yu Chiou, Chorng-Kuang Wang, A 3.3-V CMOS wideband exponential control variable-gain-amplifier, Circuits Syst. 1 (1998) 285–288. [24] G. Raikos, S. Vlassis, 0.8 V bulk-driven variable gain amplifier, Electron. Circuits Syst. (ICECS) (2010) 347–350. [25] Weihsing Liu, Shen-Iuan Liu, CMOS exponential function generator, Electron. Lett. 39 (1) (2003) 1–2. [26] Weihsing Liu, Shen-Iuan Liu, Shui-Ken Wei, CMOS current-mode divider and its applications, IEEE Trans. Circuits Syst. II: Express Briefs 52 (3) (2005) 145–148. [27] A. Motamed, C. Hwang, M. Ismail, CMOS exponential current-to-voltage converter, Electron. Lett. 33 (12) (1997) 998–1000. [28] Cheong Won Ryu, Choon Sik Cho, J.W. Lee, Jaeheung Kim, A low power 45 dB dynamic-range variable gain mixer in 0.18 µm CMOS, Microw. Symp. Dig. (2009) 585–588. [29] Duong Quoc-Hoang, T.K. Nguyen, Lee Sang-Gug, CMOS exponential current-tovoltage circuit based on newly proposed approximation method, Circuits Syst. 2 (2004). [30] Xin Cheng, Haigang Yang, Tongqiang Gao, Fei Liu, A 47-dB linear CMOS variable
generating a multitude of continuous mathematical functions changing the coefficients of the approximation function. The function synthesizer circuit that can be obtained has the advantage of increased modularity and controllability and of reduced design costs for each function. Because all the relations that are related to the generation of the exponential function do not depend on technological parameters (in a first-order approximation), it is expected that temperature stability of the circuit to be excellent. The current-mode operation of the proposed exponential function synthesizer and the operation in saturation of all MOS transistors strongly increased the bandwidth of the circuit. The developed techniques for improving the exponential circuit accuracy additionally improves the circuit THD. Acknowledgement This work is supported by Research Project PN-III-P4-ID-PCE- 20160300 UEFISCSI. References [1] Quoc-Hoang Duong, Trung-Kien Nguyen, Sang-Gug Lee, All CMOS exponential function generator with tunable input and output range, in: Proceedings of the 2003 IEEE 46th Midwest Symposium on Circuits and Systems, vol. 1, 2003, pp. 249–252. [2] Quoc-Hoang Duong, Sang-Gug Lee, A 35 dB-linear exponential function generator for VGA and AGC applications, in: Proceedings of the ASP-DAC 2004, Design Automation Conference, 2004, Asia and South Pacific, 2004, pp. 304–309. [3] M. Kumngern, J. Chanwutitum, K. Dejhan, Simple CMOS current-mode exponential function generator circuit, Electr. Eng./Electron. Comput. Telecommun. Inf. Technol. 2 (2008) (2008) 709–712. [4] Chi-Hung Lin, T.C. Pimenta, M. Ismail, A low-voltage CMOS exponential function circuit for AGC applications, Integr. Circuit Des. (1998) 195–198. [5] Q.-H. Duong, T.-K. Nguyen, S.-G. Lee, Low-voltage low-power high dB-Linear CMOS exponential function generator using highly-linear V-I converter, Low. Power Electron. Des. (2003) 349–352. [6] Quoc-Hoang Duong, Hoang-Nam Duong, Trung-Kien Nguyen, Sang-Gug Lee, All CMOS current-mode exponential function generator, Adv. Commun. Technol. 1 (2004) (2004) 528–531. [7] Chi-Hung Lin, T. Pimenta, M. Ismail, Universal exponential function implementation using highly-linear CMOS V-I converters for dB-linear (AGC) applications, Circuits Syst. (1998) 360–363. [8] C.-H. Kao, W.-P. Lin, C.-S. Hsieh, Low-voltage low-power current mode exponential circuit, Circuits Devices Syst. IEE Proc. (2005) 633–635. [9] V. Kalenteridis, S. Vlassis, S. Siskos, A CMOS linear-in-dB VGA based on exponential current generator, Des. Technol. Integr. Syst. Nanoscale Era (DTIS) (2011) 1–4. [10] Weihsing Liu, Cheng-Chieh Chang, Shen-Iuan Liu, Realisation of exponential V-I
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[33] S. Ethier, M. Sawan, Exponential current pulse generation for efficient very highimpedance multisite stimulation, IEEE Trans. Biomed. Circuits Syst. 5 (1) (2011) 30–38. [34] C. Popa, Synthesis of Computational Structures for Analog Signal Processing, Springer Publishing House, New York, 2011. [35] C. Popa, Superior-order Curvature-Correction Techniques for Voltage References, Springer Publishing House, New York, 2009.
gain amplifier using current squaring technique, Circuits Syst. (APCCAS) (2010) 76–79. [31] L.W. Isworo, H. Ochi, C. Muto, A low-voltage, low-power, wide gain-range VGA design using gm=ID method, Electr. Eng./Electron. Comput. Telecommun. Inf. Technol. (ECTI-CON) (2010) 392–396. [32] K.M. Abdelfattah, A.M. Soliman, Variable gain amplifiers based on a new approximation method to realize the exponential function, IEEE Trans. Circuits Syst. I: Fundam. Theory Appl. 49 (9) (2002) 1348–1354.
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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
High output dynamic range exponential function synthesizer Cosmin Radu Popa
MARK
Faculty of Electronics, Telecommunications and Information Technology, Bucharest, Romania
A R T I C L E I N F O
A B S T R A C T
Keywords: Exponential function Analog signal processing Low-voltage low-power circuits Approximation functions Variable changing Current-mode operation
The paper presents two original high-accuracy exponential function synthesizers with wide output dynamic ranges. The improved accuracies of the proposed computational structures are obtained using new superiororder approximation functions. In order to additionally improve the circuits' output dynamic ranges, an original method based on proper variable changing will be used and implemented. As a result of the new proposed design methods, the performances of the exponential structures are only slightly affected by technological errors. The best original proposed architecture of the exponential synthesizer has an output dynamic range of 100 dB, for an approximation error smaller than ± 1 dB. The exponential circuits are designed for implementing in 0.18 µm CMOS technology and they present a low-voltage low-power operation – the minimal supply voltage is about 0.7 V, while the power consumption is smaller than 2 μW. The chip area is about 4.5 µm2 for an implementation in 0.18 µm CMOS technology of the best proposed exponential circuit.
1. Introduction A very important function used in signal processing, finding a multitude of applications in VLSI designs, is represented by the exponential function [1–35]. The previously reported methods for generating the exponential function using CMOS circuits can be grouped in two classes. The first class of exponential function synthesizers uses the limited Taylor series expansion for obtaining the exponential function, having the main disadvantage of a relatively small output dynamic range (smaller than 30dB ) because of the limitations related to circuit complexity. Most of circuits [1–17] use the second-order approximation, only some of them [18,19] are based on the third-order approximation of the exponential function and present a smaller approximation error comparing with previous ones. Other exponential computational structures [21–32] use different forms of approximation functions for generating the exponential function. The relation between the circuits' accuracy and the complexity of their CMOS implementation is favorable to the exponential function synthesizers using approximation functions, comparing with the exponential circuits based on limited Taylor series expansions. However, the disadvantage of a relatively large approximation error still represents an important problem of this second class of exponential function synthesizers, as a result of their small order of approximation. The most used in literature exponential function approximation functions are presented in (1) [21–27,34] - output dynamic range smaller than 26dB , (2) [28–30,34] - output dynamic range of about 45 − 47dB (K and a being parameters), (3) [31,32,34] - output dynamic range smaller than 30dB (with a and b being parameters that can be controlled by the designer) or (4) [34], having an output dynamic range smaller
than 40dB . All of these previously reported exponential function synthesizers use second-order or third-order approximation functions, in order to reduce the silicon area of the circuit. The results is a relatively small output dynamic range of the exponential structures designed using these approximation functions, that drastically limits the area of applications for the developed exponential function synthesizers.
e1 (x ) =
1+x ≅ exp (2x ) 1−x
(1)
e2 (x ) =
K + (1 + ax )2 K + (1 − ax )2
(2)
e3 (x ) =
1 + ax 1 + bx
(3)
e4 (x ) =
1 + ax + cx 1 + bx
(4)
In this paper, it will be introduced and developed a new more accurately fourth-order approximation function, having the advantage of a reduced complexity and of a wide output dynamic range. The current-mode operation and the biasing in saturation of all MOS transistors that compose the proposed exponential function synthesizer are responsible for a very good frequency response of the circuit. The biasing in strong inversion (saturation region) of all MOS transistors is chosen in order to improve the frequency response of the developed exponential function synthesizer. The utilization of the new proposed fourth-order high-accuracy approximation function for generating the exponential function allows to use approximately the same chip area for its CMOS implementation,
http://dx.doi.org/10.1016/j.mejo.2017.03.013 Received 3 November 2015; Received in revised form 25 January 2017; Accepted 29 March 2017 0026-2692/ © 2017 Elsevier Ltd. All rights reserved.
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comparing with previously reported third-order exponential function synthesizers, based on classical method of approximation. As the original developed exponential function synthesizer uses a higher-order (fourth-order) of approximation, its accuracy and, additionally, its output dynamic range will be much better comparing with previous similar works.
The IA and IB currents are the input currents of the squaring circuit, while a represents a constant coefficient that depends on the particular implementation of the circuit. Using particular values of input currents: IA = IO + bIIN and IB = cIO , it is simple to generate, using a current squaring circuit with small complexity, an output current expressed as follows:
2. Theoretical analysis
IC = IO
c2 1 a 1 + b IIN I
(6)
O
The original proposed exponential function circuits generate the exponential function using new developed fourth-order approximation functions. As a result of the fourth-order approximation, the output dynamic ranges of the proposed circuits are strongly increased comparing with the previous reported similar circuits. In order to additionally increase the output dynamic range of the new designed circuits, an original variable changing will be used, allowing an important reduction of the effective range of the input variable. The new proposed approximation methods allow extremely simple implementations in CMOS technology, using only two, respectively four current-mode squaring circuits, their total complexity being comparable with the complexity of previously reported exponential circuits with only second-order approximation and much poorer performances.
In conclusion, new approximation functions will be obtained considering a finite number of primitive functions, having the general expressions derived from (6), 1/(1 + bk x ). The x variable is defined as the ratio between the input current and the reference current, x = IIN / IO . The number and the form of primitive functions that will represent the basis for synthesizing the approximation function is imposed by the necessity that its Taylor series must fulfilled the Taylor series of the exponential function. Evidently, the improving of the circuit accuracy can be made by increasing the number of primitive functions and, in consequence, the complexity of the exponential function synthesizer. Because the absolute value of a superior-order term from a Taylor series expansion strongly decreases when the order of approximation increases, the fourth-order term from the Taylor series expansion of a continuous function will be much smaller (in absolute value) than the constant, linear, second-order and third-order terms from the same expansions. The additional consideration of the fifth-order term produces only a very small increasing of the approximation accuracy, but strongly increases the complexity of the computational circuits that will implement the approximation function. In consequence, taking into account a convenient tradeoff between the accuracy of approximation using a limited Taylor series expansion and the complexity of the implementation in CMOS technology of the approximation function, an optimal choice that permits to obtain a very good accuracy and a very large dynamic output range of the exponential function synthesizer circuit, using a reasonable circuit complexity will be based on a fourthorder approximation of the exponential function. The original proposed general form of the approximation function (which is able to fourthorder approximate a multitude of continuous mathematical functions) will be synthesized using two primitive functions and two additional linear terms. having the following general expression:
2.1. Synthesis and implementation of the first approximation function In order to synthesize the general form of the approximation functions that will be used for generating the exponential function, some requirements must be fulfilled. The most important conditions that are imposed to the approximation function are related to its capability to simulate with a very good accuracy the exponential function, correlated to the need for an extended dynamic output range for the designed computational structure. These performances have to be obtained using a reasonable complexity of the exponential function synthesizer. Usually, the increasing of the accuracy of approximation produces an important increasing of the complexity for the circuits that implement in CMOS technology the approximation function. From this point of view, a tradeoff between the acceptable complexity of the exponential function synthesizer and its overall accuracy must be habitually made. The new proposed method of synthesis the approximation function has the advantage of presenting an extremely low approximation error, this performance being obtained using a reasonable circuit complexity. This is possible by exclusively using in the circuit implementation of currentmode squaring circuits and of current mirror circuits, having relatively small intrinsic complexities in CMOS technology. Additionally, the original expression of the approximation function further reduces the circuit complexity. The current-mode operation of the proposed exponential function synthesizers and the independence of their output signal on technological parameters and on temperature variations contribute to a supplementary increasing of the circuits’ accuracy, allowing to decrease the order of approximation, while maintaining, however, the accuracy of the computational structure. The necessity of the exclusively use in the implementation of the exponential function synthesizers of MOS transistors biased in saturation region is imposed by the requirements for a good frequency response of the proposed exponential circuits. In the same situation, the current-mode operation strongly improves the frequency response of the proposed circuits. The original proposed mathematical forms of the approximation function are synthesized starting from the general expression of the IC output current of a current squaring circuit (because the squaring function is the most convenient choice for implementing in CMOS technology):
IC =
IB2 aIA
⎛I ⎞ a1 a3 I + + a4 IN + a5 f1 ⎜ IN ⎟ = IIN ⎝ IO ⎠ 1 + a2 IIN IO 1 + I I O
O
(7)
The reason for choosing the previous general form of the approximation function is related to its facile CMOS implementation and to its complete definition using a number of five coefficients (a1 to a5). In order to obtain the values of these coefficients (in the particular case of approximating the exponential function), the identity between the first five terms from the Taylor series of the approximation function and, respectively, of the exponential function must be considered (constant term, linear term and second, third and fourth-order terms). Solving the system imposed by the previous identities, it results the following expression of the fourth-order approximation function:
⎛I ⎞ 26 1 1 1 7I 21 + − IN − f1 ⎜ IN ⎟ = ⎝ IO ⎠ 5 1 − 5IIN 128 1 + IIN 11IO 5 I 16I O
O
(8)
The comparison between f1 (x ) first approximation function and exp(x ) function is presented in Table 1, showing a wide decibel linear range of 33dB , for a deviation from the exponential characteristic of 1dB . A graphical comparison between f1 (x ) approximation function and exp(x ) function is presented in Fig. 1, illustrating a good fitting of f1 (x ) function with the exponential function. The original proposed exponential function synthesizer permits a facile reconfiguration, the generation of any continuous mathematical
(5) 124
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resulting:
Table 1 Comparison between f1 (x ) and exp(x ) functions. x
f1 (x) [dB]
exp (x) [dB]
ε [dB]
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.65
0.16 2.11 4.07 6.05 8.03 10.02 12.01 14.01 16.03 18.05 20.09 22.15 24.24 26.35 28.49 30.68 32.91 34.01
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 33
0.16 0.11 0.07 0.05 0.03 0.02 0.01 0.01 0.03 0.05 0.09 0.15 0.24 0.35 0.49 0.68 0.91 1.01
I = IA −
(10)
In order to generate the squaring term from the previous relation, all MOS transistors from Fig. 2 have to be biased in saturation region and, correlated with this condition, the supply voltage must be greater than the minimal value expressed by: (11)
VDDmin = 3VGS 4 − VT
Additionally, the potential in the drain of M5 transistor (imposed by the output circuit that uses IC current) must have a convenient value, that allows M5 and M8 transistors to be also biased in saturation region. The expression of the IC output current is:
IC = 2I + IB − 2IA =
IB2 8IA
(12)
M1–M7 MOS devices from Fig. 2 have an aspect ratio (W/L) =0.18 µm/0.5 µm, while M8 transistor has an aspect ratio (W/L) =0.36 µm/0.5 µm. The first squaring circuit presents the advantage of the independence of the output current on technological parameters and on temperature variations, this fact improving the circuit accuracy. The frequency response of the squaring circuit is improved as a consequence of the current-mode operation of the circuit. The symbolical representation of the first squaring circuit is presented in Fig. 3. The original proposed block diagram for implementing the first fourth-order exponential function synthesizer based on the new proposed approximation function f1 (x ), expressed by (8) is presented in Fig. 4. It is based on the first new approximation function expressed by (8) and on the first proposed realization of the squaring circuit, presented in Fig. 2. The output current of the first exponential function synthesizer can be expressed as follows:
Fig. 1. Graphical comparison between f1 (x ) and exp(x ) functions.
IOUT = IC 2 − IC1 −
function being possible using relation (7) by changing of the approximation function coefficients, in accordance with the Taylor series of each particular function. The core for implementing the exponential function synthesizer is represented by a first current-mode squaring circuit, having the proposed realization presented in Fig. 2. Noting with VGS (ID ) the gate-source voltage of a MOS transistor biased in saturation, at a drain current equal with ID , the translinear loop that establishes the operation of the squaring circuit can be expressed as follows:
2VGS (IA) = VGS (I ) + VGS (I + IB )
I2 IB + B 2 16IA
7 21 IIN − IO 11 5
(13)
Using the functional relation (11) for both squaring circuits from Fig. 4, the expression of the output current becomes:
⎛I ⎞ ⎛I ⎞ IOUT (IIN ) = IO f1 ⎜ IN ⎟ ≅ IO exp ⎜ IN ⎟ ⎝ IO ⎠ ⎝ IO ⎠
(14)
The CMOS implementation of the first exponential function synthesizer is presented in Fig. 5. The chip area of the proposed exponential function synthesizer, designed for implementing in CMOS 0.18μm technology, is about 3μm2 .
(9)
2.2. Synthesis and implementation of the second approximation function Starting from the first new proposed approximation function f1 (x ) (expressed by (8)), in order to increase the accuracy of the exponential function synthesis, a second original improved approximation function f2 (x ) will be developed. This second original approximation function f2 (x ) was obtained using the x − > x /4 variable changing and the particularity of the exponential function that exp 4 (x /4) = exp (x ). This original method will have the effect of fourth time reducing the effective range of variation for the input variable and, in consequence, of strongly increasing the output dynamic range of the exponential function synthesizer. Additionally, the full range of x input variable is IA IB
A B
SQ C
IC
Fig. 3. Symbolical representation of the first squaring circuit.
Fig. 2. Squaring circuit (first implementation).
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Table 2 Comparison between f2 (x ) and exp(x ) functions.
Fig. 4. Block diagram of the exponential function synthesizer based on f1 (x ) first approximation function.
split into two sub-ranges, each one corresponding to positive and, respectively, negative values of x . Each particular function ( f2a or f2b ) can better match the exponential function for its range of operation, supplementary increasing the output dynamic range of the exponential function synthesizer based on this original approximation function.
⎛ 26 1 1 1 f2a (x ) = ⎜⎜ − 5x 5 128 1 + 1 − ⎝ 64 ⎛ 26 1 1 1 f2b (x ) = ⎜⎜ − 5x 5 128 1 − 1 + ⎝ 64
x 4
⎞4 7x 21 ⎟ − − , x>0 44 5 ⎟⎠
(15)
x 4
⎞4 7x 21 ⎟ + − , x<0 44 5 ⎟⎠
(16)
The comparison between f2 (x ) approximation function and exp(x ) function is presented in Table 2, showing an extremely wide decibel linear range, greater than 100dB , for a deviation from the exponential characteristic of 1dB . A graphical comparison between f2 (x ) approximation function and exp(x ) function is presented in Fig. 6, illustrating a very good fitting of f2 (x ) function with the exponential function. The second new proposed CMOS current-mode squaring circuit is presented in Fig. 7. The IC current represents the output current of the circuit, IB - the input current and IA - an external applied reference current. The input and the output currents can be expressed as IB = I3 − I2 and IC = I2 + I3 − 2IO . The translinear loop containing M1÷M4 transistors has the following characteristic equation:
VGS1 + VGS 4 = VGS 2 + VGS 3
x
f2 (x) [dB]
exp (x) [dB]
ε [dB]
−5.8 −5 −4 −3 −2 −1 0 1 2 3 4 5 5.8
−51.36 −43.93 −34.90 −26.09 −17.40 −8.79 0.27 8.79 17.40 26.09 34.90 43.93 51.36
−50.41 −43.45 −34.77 −26.07 −17.38 −8.69 0 8.69 17.38 26.07 34.77 43.45 50.41
−1.05 −0.48 −0.13 −0.02 −0.02 −0.10 0.27 0.10 0.02 0.02 0.13 0.48 1.05
Fig. 6. Graphical comparison between f2 (x ) and exp(x ) functions.
to be neglectible the second-order effects that affect the MOS transistor operation, the circuit presented in Fig. 7 will generate an output current proportional with the square of the input current and independent on technological parameters and on temperature variations:
IC =
(17)
IB2 8IA
(18)
The quasi-independence on technological errors of the circuit operation was obtained as a consequence of the design method that
Imposing a biasing in saturation of MOS transistors and supposing
Fig. 5. CMOS implementation of the first exponential function synthesizer.
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IOUT 1 =
IO2 26 5 IO − 5IIN 64
(20)
IO2 1 128 IO + IIN 4
(21)
and:
IOUT 2 =
resulting:
IOUT 3 = IOUT 1 − IOUT 2 −
7IIN 21IO − 44 5
(22)
equivalent with:
⎛ 26 1 1 1 − IOUT 3 = IO ⎜⎜ 5x 5 128 1 + 1 − ⎝ 64
x 4
−
⎞ 7x 21 ⎟ − 44 5 ⎟⎠
(23)
The IOUT 4 current can be expressed as follows:
IOUT 4 =
Fig. 7. Squaring circuit (second implementation).
(24)
resulting:
has been used, based on a translinear loop containing two positive and two negative gate-source voltage of MOS transistors biased in saturation region. An important consequence of this particularity is represented by a quasi-independence of the circuit behavior on temperature variations. In order to generate the squaring term from the previous relation, all MOS transistors from Fig. 2 have to be biased in saturation region and, correlated with this condition, the supply voltage must be greater than the minimal value expressed by:
VDDmin = 3VGS1 − VT
2 IOUT 3 IO
IOUT =
2 IOUT I4 3 4 = OUT IO IO3
(25)
So, the output current will approximate the exponential function, using the more accurate f2a (x ) approximation function:
⎛ 26 1 1 1 IOUT (x ) = IO ⎜⎜ − 5x 128 1 + ⎝ 5 1 − 64
(19)
x 4
−
⎞4 7x 21 ⎟ − 44 5 ⎟⎠
(26)
In conclusion, the output current will be proportional with the exponential function, having as input variable the ratio between the input and the reference current:
Additionally, the potential in the drain of M2 transistor (imposed by the output circuit that uses IC current) must have a convenient value, that allows M2 and M3 transistors to be also biased in saturation region. Aspect ratios of all MOS transistors from Fig. 7 are (W/L) =0.18 µm/0.5 µm. The symbolical representation of the second squaring circuit is also presented in Fig. 3. The block diagram of the second exponential function synthesizer, based on f2a (x ) approximation function, is presented in Fig. 8. The chip area of the proposed exponential function synthesizer, designed for implementing in CMOS 0.18μm technology, is about 4.5μm2 . For implementing f2b (x ) function, useful for negative input variables x , the same block diagram must be used. The “SQ” blocks from Fig. 8 have the concrete implementations presented in Fig. 7. The expressions of IOUT1 and IOUT 2 currents are:
⎛I ⎞ ⎛I ⎞ IOUT (IIN ) = IO f2a ⎜ IN ⎟ ≅ IO exp ⎜ IN ⎟ ⎝ IO ⎠ ⎝ IO ⎠
(27)
2.3. Errors introduced by second-order effects The errors introduced in the operation of the squaring circuits from Figs. 2 and 7 are: the mismatches, channel effect modulation, body effect and mobility degradation. Taking into account the channel effect modulation, the gate-source voltage of a MOS transistor biased in saturation region can be expressed as follows:
VGS = VT +
2ID K (1 + λVDS )
(28)
Considering, additionally, the mismatches for VT and K parameters and taking into account the previous relations, it results that the expressions of squaring circuits’ output currents will be affected by a small additional error, ε1, that could be minimized using commoncentroid configurations for particular constitutive transistors of squaring structures:
IC =
IB2 + ε1 8IA
(29)
In order to minimize this error using the common-centroid technique, the aspect ratios (W/L) of all MOS devices must be changed by increasing Ws and Ls, while maintaining their ratios. Practically, a tradeoff between accuracy and complexity must be made, depending on each design requirements. For the squaring circuit presented in Fig. 2, ε1 error is smaller than 0.1%, while the same error for the squaring circuit proposed in Fig. 7 is smaller than 0.13%. The body effect errors can be evaluated considering the general
Fig. 8. Block diagram of the exponential function synthesizer. based on second f2a (x ) approximation function.
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dependence of the threshold voltage on the bulk-source voltage:
VT = VTO + γ ( Φ − VBS −
Φ)
(30)
VTO is the threshold voltage for VBS = 0 , γ is a technological parameter and Φ represents the Fermi potential. Considering, additionally, the mobility degradation effect, the gate-source voltage for a MOS transistor biased in saturation is expressed by: VGS = VT +
2ID θ + G ID K K
(31)
Taking into account the body effect and the mobility degradation, the output currents of the squaring circuits presented in Fig. 2 and in Fig. 7 will be affected by an additional error ε2 , depending on γ , Φ , K and θG model parameters and also on the circuit biasing currents:
IC =
IB2 + ε2 8IA
Fig. 10. Simulation of the IC (IA, IB ) squaring circuit dependence for IA = 0.1μA.
(32)
For the squaring circuit presented in Fig. 2, ε2 error is smaller than 0.12%, while the same error for the squaring circuit proposed in Fig. 7 is smaller than 0.15%. 3. Simulations Fig. 11. Simulation of the IOUT (IIN ) dependence for the exponential circuit presented in Fig. 5.
The operation of the functional squaring core from Fig. 2 is evaluated using actual simulation. The simulation of the IC (IB ) dependence expressed by (12) for IA = 0.1μA and a range of variation for IB current between −0.1μA and 0.1μA is presented in Fig. 9. The simulated error for implementing the squaring function (10) using the original proposed squaring core from Fig. 2 is 0.35%. The simulation is based on 0.18μm CMOS process, the supply voltage being equal with the minimal supply voltage, accepted by the proposed squaring circuit, VDD = 0.6V . The current consumption is smaller than 0.5μA for the full implementation of the new proposed squaring circuit. The operation of the functional squaring core from Fig. 7 is evaluated using actual simulation. The simulation of the IC (IB ) dependence expressed by (18) for IA = 0.1μA and a range of variation for IB current between −0.1μA and 0.1μA is presented in Fig. 9. The simulated error for implementing the squaring function (16) using the original proposed squaring core from Fig. 7 is 0.45%. The simulation is based on 0.18μm CMOS process, the supply voltage being equal with the minimal supply voltage, accepted by the proposed squaring circuit, VDD = 0.7V . The current consumption is smaller than 0.6μA for the full implementation of the new proposed squaring circuit (Fig. 10). The operation of the exponential circuit presented in Fig. 5, based on the new f1 (x ) approximation function, is evaluated using the simulation presented in Fig. 11. It shows the IOUT output current exponential dependence on the IIN input current. The IO reference current is 0.1μA, while the range of variation for the IIN input current is chosen between 0 and 0.4μA. The maximal simulated error for implementing the exponential function using the original proposed circuit is 0.8%. The simulation is based on 0.18μm CMOS process, the supply voltage being equal with the minimal supply voltage, accepted by the proposed squaring circuit, VDD = 0.7V .
A comparison between the previously reported exponential circuits and the second original proposed exponential structure is presented in Table 3. The new proposed approximation function allows an important increasing of the exponential circuit accuracy, associated with an increasing of the output dynamic range with at least 50dB (comparing with other previously reported exponential circuits). The power consumption smaller than 2μW recommends the proposed computational structures for low-power applications. The circuits are designed for a low voltage operation (a supply voltage of 0.7V ), this feature being obtained using specific design techniques. As a result of original design methods applied in synthesizing the architectures of the proposed exponential structures, the estimated performances are relatively stable with respect to process variations and with temperature drifts. The new specific expressions of the developed approximation functions, and also the original proposed implementation of the constitutive squaring blocks contribute to an important decreasing of the circuit silicon area comparing with other previously reported implementations of exponential circuits, having poorer performances. The effect of process and mismatch variations could be evaluated using Monte Carlo simulation results. 4. Conclusions There were presented two original high-accuracy exponential function synthesizers with wide output dynamic ranges. The improved accuracies of the proposed computational structures were obtained using new superior-order approximation functions. In order to additionally improve the circuits' output dynamic ranges, an original method based on proper variable changing was used and implemented. As a result of the new proposed design methods, the performances of the exponential structures were only slightly affected by technological errors. The best original proposed architecture of the exponential synthesizer has an output dynamic range of 100 dB, for an approximation error smaller than ± 1 dB. The exponential circuits are designed for implementing in 0.18 µm CMOS technology and they present a lowvoltage low-power operation - the minimal supply voltage is about 0.7 V, while the power consumption is smaller than 2 μW. The chip area is about 4.5 µm2 for an implementation in 0.18 µm CMOS technology of the best proposed exponential circuit. The new exponential function synthesizers have the possibility of
Fig. 9. Simulation of the IC (IA, IB ) squaring circuit dependence for IA = 0.1 μA .
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Table 3 Comparison between the previously reported exponential circuits and the second original proposed exponential structure. Reference/ parameter
Dynamic range [dB]
Error [dB]
Supply voltage [V]
Power consumption [mW]
Technology [μm]
Dependence on technology
Method of approximation
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] This work (Fig. 8)
25 35 16 20 20 15 20 12 17 15 26 20 14 17 15 20 12.8 45 46 47 20 45 100
± 0.5 ± 0.5 1 ± 0.5 ± 0.5 ± 0.5 ± 0.5 5 0.5 ± 0.5 0.5% 0.5 1 ± 0.5 ± 0.5 ± 0.5 5% ±1 ± 0.5 ± 0.5
1.25 1.25 1.5 3 1.25 1.25 3 1
0.1 0.3
0.25 0.25 0.5
0.2 0.015 0.9 0.0035 0.3 0.8 24.8 0.0064 12.5
0.25 0.25 1.2 0.35 0.09 0.35 0.35 0.25 0.5 0.18 0.5 0.5 2 0.18 0.25 0.13 0.09 0.5 0.18
Yes No Yes Yes No Yes Yes No No Yes Yes No Yes No yes Yes Yes Yes No Yes Yes No No
Taylor 2-nd order Taylor 2-nd order Taylor 2-nd order Taylor 2-nd order Taylor 2-nd order Taylor 2-nd order Taylor 2-nd order Taylor 2-nd order Taylor 2-nd order Taylor 2-nd order Approximation function (1) Approximation function (1) Approximation function (1) Approximation function (1) Approximation function (1) Approximation function (1) Approximation function (1) Approximation function (3) Approximation function (3) Approximation function (3) Approximation function (4) Approximation function (4) New approximation function (15), (16)
±1
± 1.5 1.5 0.9 3.3 0.8 ± 1.5 1.5 3 1.8 1.5 1.2 1.2 ± 1.5 0.7
0.4
7.56 0.8 3.6 0.72 1.2 0.002
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