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GaAs PHEMTs using an optimised manufacturing process for Ka-band applications
Microelectronic Engineering 113 (2014) 11–19
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High power density AlGaAs/InGaAs/GaAs PHEMTs using an optimised manufacturing process for Ka-band applications Sung-Jin Cho, Cong Wang, Nam-Young Kim ⇑ RFIC Research Center, Kwangwoon University, 447-1 Wolgye-dong, Nowon-Ku, Seoul, Republic of Korea
a r t i c l e
i n f o
Article history: Received 5 March 2012 Received in revised form 29 April 2013 Accepted 1 July 2013 Available online 11 July 2013 Keywords: AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistors (PHEMT) Passivation Gate recess e-Beam lithography Breakdown voltage Output power
a b s t r a c t In this study, a novel manufacturing process for a 0.1 lm T-gate is investigated for producing a high output power performance for the Ka-band frequencies using high-quality AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistors (PHEMTs) on semi-insulated (SI) GaAs substrates. The gate manufacturing process is the most important process due to its intimate relationship with the DC and RF performance of the device. To improve the gate performances of PHEMT devices, we investigated various materials and processing approaches involving a wide gate recess, double exposure by e-beam lithography, and low-damage double-gate passivation methods based on plasma-enhanced chemical vapour deposition (PECVD). To reduce the sensitivity to current collapse effects, we investigate the relationship between the electrical characteristics of the PHEMTs and top and bottom gate-supported passivation films. To improve the ohmic contact performance, we test an AuGe/Ni/Au (200/30/120 nm) ohmic contact metallisation scheme using the rapid thermal annealing (RTA) process at temperatures ranging from 450 °C 30 s. A PHEMT with a gate length of 0.1 lm, exhibiting a maximum drain current density of 680 mA/mm, a peak transconductance of 500 mS/mm, a unity-gain cut-off frequency (fT) of 56 GHz, and a maximum frequency of oscillation (fMAX) of 84 GHz, is demonstrated using this novel manufacturing process; the Ka-band power performance includes an output power density of 2.4 W/mm and a power-added efficiency (PAE) of 44.6%. Ó 2013 Elsevier B.V. All rights reserved.
1. Introduction Due to their excellent high-frequency operation, high efficiency, high power, and low-noise performance, AlGaAs/InGaAs/GaAs PHEMTs are emerging as promising candidates for radio frequency (RF) components, such as low-noise amplifiers or power amplifiers for the next-generation of commercial wireless communication systems [1–4]. In particular, in the case of extremely high frequencies, GaAs-based PHEMTs have attracted a great deal of interest as active components. For optimised high-frequency operation, highquality gate fabrication, reduced parasitic gate resistance (Rg), and high power performance are the most important issues to determine the performance of PHEMTs. Low Rg can be obtained at high frequencies, and high value of fT and fmax can be obtained. To reduce the gate resistance, T-shaped gates with a small gate length and large cross-sectional area are required [5–7]. T-gate fabrication can be based on electron beam lithography with multiple resist layers [8,9]. The gate length (Lg), and the thickness of the passivation layer are the major factors affecting the gate capacitance (Cgs), which is a key parameter in determining the RF performance
⇑ Corresponding author. Tel.: +82 29405071; fax: +82 29425235. E-mail addresses: [email protected], [email protected] (N.-Y. Kim). 0167-9317/$ - see front matter Ó 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.mee.2013.07.001
in the high-frequency range. The T-gate head is a function of the reduction of Rg. However, at the same time, the T-gate head is a function of the increase in Cgs [10–12]. Likewise, to increase the output power, the high drain current density, high breakdown voltage, and knee voltage are required. These relationships can be shown in a simple equation:
Pout ¼
IDS;max ðV break V knee Þ 8
ð1Þ
where IDS,max is the maximum drain current from DC measurements and Vbreak and Vknee are the breakdown and knee voltages, respectively [13]. To obtain high power, there are three key parameters, as shown in Eq. (1): a high drain current density, high breakdown voltage, and low knee voltage. In spite of its high-frequency performance, unfortunately, GaAs PHEMTs have a high drain current density and a high breakdown voltage performance compared with GaN HEMT structures due to the different epi material characteristics and structures. Moreover, the large gate leakage current and current dispersion that are generated due to the surface states remain the most significant obstacles to high-frequency operation in AlGaAs/InGaAs/GaAs PHEMTs. It is noted that the current collapse condition can be considerably improved by surface passivation methods [14].
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2. Experimental procedure
Fig. 1. A cross-sectional schematic diagram of an AlGaAs/InGaAs/GaAs PHEMT.
To increase output power using the GaAs epi structure, in this work, we employed a SI-GaAs substrate-based AlGaAs/InGaAs/ GaAs PHEMT fabrication process, which is highly competitive in terms of the device performance and cost. To improve the device characteristics, several optimised processes are presented. First, an optimised AlGaAs/InGaAs/GaAs epi-structure using a changeable AlGaAs barrier thickness and Al composition is proposed [15]. Second, to mitigate the current collapse problem and increase Cgs, a double-gate-supported passivation scheme (Si3N4/Si3N4; SiO2/SiO2; SiO2/Si3N4; Si3N4/SiO2) is first proposed for AlGaAs/InGaAs/GaAs PHEMTs [16]. In addition, a damage-free dry/wet-etching method is proposed that removes the undesirable passivation layers. Passivation films provide effective improvements that mitigate the current collapse phenomenon. However, the suppression of the current collapse phenomenon in high-frequency and high-power operations cannot be achieved using only the passivation process. An advanced 0.1 lm gate manufacturing process with a doubleexposure method using electron beam lithography and a wide gate recess process increases the drain-to-source breakdown voltage, and more stable operation can be achieved in the high-frequency range.
AlGaAs/InGaAs/GaAs-structured epitaxy materials are grown by metal organic chemical vapour deposition (MOCVD) on a 6-in. SIGaAs substrate, which consists of the following layers: a 3000 Å GaAs, 2150 Å Al0.22GaAs/GaAs buffer, silicon delta first doping of 1.5 1012 cm2, 40 Å Al0.22GaAs spacer, 110 Å In0.22GaAs channel, 30 Å Al0.22GaAs spacer, silicon delta second doping of 5 1012 cm2, 180 Å Al0.22GaAs barrier, 230 Å GaAs cap layer, silicon delta final doping of 6 1012 cm2, and 70 Å In0.22GaAs cap layer. The proposed process starts with mesa isolation, after which the AuGe/Ni/Au (200/30/120 nm) source and drain ohmic metal is deposited by an e-beam evaporator. After the ohmic metal lift-off process, the samples are sequentially annealed under an N2 flow using the rapid thermal annealing (RTA) process at temperatures ranging from 450 °C 30 s. After the RTA processing, the specific contact resistances (qc) are measured by the transfer length method (TLM); the square (100 100 lm) contacts are separated by 2, 4, 8, 16, and 32 lm. The circular TLM data indicated a qc of below 105 Ohm cm2 with a sheet resistance of approximately 400 Ohm/sq. After ohmic processing, wide double-recessed etching is conducted. A gate recess surface passivation layer composed of Si3N4 or SiO2 is then deposited by PECVD to a thickness of 100 nm. After the deposition of Si3N4 or SiO2, a 0.1 lm gate foot pattern is realised by double-exposed e-beam lithography. After the developing process, inductively coupled plasma (ICP) dry etching is performed to selectively remove the Si3N4 or SiO2. After that, a Ni/Au (40/ 400 nm) T-gate with a length of 0.1 lm was formed between the source and drain ohmic contacts. The passivation process was performed after all of the aforementioned steps, followed by the formation of vias to open the metal contacts. A cross-sectional schematic diagram of an AlGaAs/InGaAs/GaAs PHEMT on a SI-GaAs substrate is shown in Fig. 1. 2.1. Wide gate double recess process method Due to the creation of a depletion region, the flow of current from source to drain is blocked and, eventually, only a small amount of current flows compared with the supplied voltage. This implies that the breakdown voltage of the device is not good, which can be solved by the wide double-recessed process [17]. Through the use of a wide recess with gate recess, the area of the channel covered by external air can be decreased by establishing
Fig. 2. Flow chart of the double-exposure e-beam lithography method.
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Fig. 3. FIB picture of a 0.1 lm T-gate AlGaAs/InGaAs/GaAs PHEMT.
Fig. 4. FIB picture of the fabricated PHEMT with a 8 (100 0.1) lm2 gate periphery.
contact with the depletion region. A 70 Å thick In0.22GaAs layer with a 130 Å GaAs epi-layer is etched by ICP dry etching for the formation of the wide recessed structure and a 200 Å thick GaAs epilayer is subsequently etched by ICP dry etching for the formation of the recessed gate structure. The width of the wide recess is 5 lm, and that of the gate recess is 1 lm.
2.2. Realisation of a 0.1 lm gate process using the double-exposure ebeam lithography method The parasitic resistance can be reduced by minimising the value of the ohmic resistance and reducing the gate length. Additionally, a narrow distance between the gate and drain (source) can also reduce the parasitic resistance, so they should be arrayed closely when using an advanced exposure technique such as e-beam lithography. In the case of a simple rectangular metal gate, the shorter the gate length, the more the parasitic resistance can be increased. Therefore, a T-gate is often used to reduce the gate parasitic resistance, especially in the form of multiple fingers because in this way, the unit length of the gate can be reduced. To make T-shaped gate, single and double-exposure methods are used.
Fig. 5. (a) I–V characteristics with varying gate biases, (b) transconductance characteristics, and (c) breakdown voltage characteristics for wide gate recessed and non-recessed PHEMTs.
The double-exposure technique is better than the single-exposure technique because the second exposure has a forward scattering and decreases the electrons [18]. As a result, the double-exposure technique leads to good uniformity after development and a clear T-shaped structure. Fig. 2 shows a flow chart of a novel 0.1 lm gate fabricated by JBX6000FS/E e-beam lithography. An accelerating voltage of 50 kV, probe beam current of 1 nA, and beam resolution of 50 nm were used for the e-beam lithography. We investigated the use of a double-exposure technique on special ZEP-PMGIPMMA trilayer photoresists, which have excellent metal lift-off characteristics.
2.3. Low-damage double gate supported passivation method using plasma-enhanced chemical vapour deposition Silicon nitride and silicon dioxide dielectric materials are widely used in the manufacturing processes of various compound
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SiO2 for the second gate passivation (D), 100 nm SiO2 for the first passivation and 100 nm Si3N4 for the second gate passivation, (E) 100 nm Si3N4 for the second passivation without the first gate passivation, and (F) 100 nm SiO2 for the second passivation without the first passivation. All of the experiments are referenced to the single passivation layer case. Before Si3N4 deposition, the conditions used for PECVD are important because the RF power, chamber temperature, and pressure significantly affect the damage to the ohmic and epi-layer. The deposition of Si3N4 and SiO2 that is 50% tensile and 50% compressive is performed in an OERLIKON VL-LA-PECVD system. Different He gas flow ratios, chamber pressures of 900 and 1200 mTorr, chamber temperatures of 150 and 250 °C, an RF frequency of 13.56 MHz, and RF powers of 60 and 100 W are used for the PECVD-deposited Si3N4 and SiO2, respectively. The DC I–V characteristics are measured at VDS = 0–15 V and VGS = 1 to 5 V for all of the samples. However, we note that the top Si3N4 layer of sample (D) is broken, owing to the interaction between the different types of stresses of the inner thin films, and therefore, this structure cannot be considered. 3. Results and discussion
Fig. 6. (a) I–V characteristics with varying gate biases and (b) transconductance characteristics after single and double-exposure e-beam lithography.
semiconductor devices and circuits. These processes include the device passivation of integrated passive devices (IPDs) [19], metal-oxide-semiconductor field-effect transistors (MOSFETs) [20] and hetero-junction bipolar transistors (HBTs) [21], masking layers, dielectric layers for metal–insulator–metal (MIM) capacitors, and wafer-level final passivation to protect the circuit against mechanical scratches. The effects of Si3N4 passivation are reported to improve the DC and RF properties in AlGaAs/InGaAs/GaAs-based PHEMTs [22]. Without passivation, the exposed surface of the GaAs epilayer can be damaged by oxidation, moisture, and other forms of pollution. After the double-recessed process, a 100 nm thick layer of Si3N4 is deposited on the GaAs epilayer by PECVD. Subsequently, after the final development of the PMMA photoresist, which is used to make the T-gate high footprint dose via e-beam lithography, Si3N4 is first etched by ICP etching. To avoid the damage to the n-AlGaAs gate contact epitaxy layer caused by dry plasma etching, the Si3N4 is etched out using a dry/wet etching method. First, 80 nm of the Si3N4 is dry-etched by an ICP etching system, and then the remaining 20 nm is wet-etched by a 1:6 buffered oxide etch (BOE) solution. Because the BOE is very sensitive to the pattern size, film quality, and environmental conditions, a dummy wafer is needed during the overall dry/wet etching process. The focused ion beam (FIB) images of the cross-sectional 0.1 lm T-gate with an AlGaAs/InGaAs/GaAs PHEMT are shown in Fig. 3. The pillar of the T-gate is surrounded by the Si3N4 first passivation layer to help reduce the gate contact resistance. After the deposition of the Ni/Au (40/400 nm) gate by an e-beam evaporator, 100 nm thick Si3N4 second dielectric layers are deposited on top of the gate. An analysis of the top and bottom gate passivation was conducted for six cases: (A) 100 nm Si3N4 for the first passivation and 100 nm Si3N4 for the second gate passivation, (B) 100 nm SiO2 for the first passivation and 100 nm SiO2 for the second gate passivation, (C) 100 nm Si3N4 for the first passivation and 100 nm
A SI-GaAs substrate with high-quality MOCVD-deposited epilayers and a novel fabrication technology consisting of double gate recessing, double exposure of e-beam lithography, a double passivation process, and an AuGe/Ni/Au-based ohmic contact process are employed to realise high-performance AlGaAs/InGaAs/GaAs PHEMTs. Fig. 4 shows a FIB image of a fabricated 100 lm 8-finger freestanding PHEMT with a gate length of 0.1 lm, drain–gate spacing of 2 lm, and gate–source spacing of 1 lm. Fig. 5 shows the I–V characteristics, transconductance, and breakdown voltage of the
Fig. 7. (a) I–V characteristics with varying gate biases and (b) transconductance characteristics of single and double passivation.
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Table 1 DC properties of Si3N4 or SiO2 single and double passivation on AlGaAs/InGaAs/GaAs PHEMTs.
IDS,max (mA/ mm) gm,max (mS/ mm) Vth (V) Vknee (V) Ith (uA/ mm) Vbreak (V)
Si3N4/ Si3N4
SiO2/ SiO2
Si3N4/ SiO2
Si3N4
SiO2
620
510
590
425
343
At VGS = +1 V
400
310
338
300
270
At VDS = 10 V
4.5 5.3 0.44
3.9 5.1 0.52
4.1 5.1 0.6
3.7 5.5 18.2
5 5 31.9
34
45
42
22
29
At VGS = +1 V At VGS = +1 V At VGS = 5 V, at VDS = 10 V At VGS = 5 V
Fig. 8. (a) I–V characteristics with varying gate biases and (b) transconductance characteristics of Si3N4/Si3N4; SiO2/SiO2; Si3N4/SiO2 double passivation. Fig. 10. The measured short current gain and maximum stable gain versus frequency of an 8 (100 0.1) lm2 gate periphery on an AlGaAs/InGaAs/GaAs PHEMT.
Table 2 Summary of the published GaAs PHEMTs with a description of the DC and RF performance.
Fig. 9. Breakdown voltage (Vbreak) characteristics of Si3N4/Si3N4, SiO2/SiO2, Si3N4/ SiO2 double passivation and Si3N4, SiO2 single scheme passivation at 5 V pinch off gate voltage.
wide double-recessed and non-recessed processes. The DC characteristics of the devices are measured at room temperature using a Keithley 4200-SCS/F semiconductor parameter analyser. The DC I– V characteristics are measured at VDS = 0–15 V and VGS = 1 to 5 V for all of the samples. The gate bias is kept below +1 V due to the unacceptably high forward gate current. The wide gate doublerecessed structure exhibits better saturation and pitch-off characteristics than the non-recessed structure. The recessed and non-recessed devices yielded maximum saturation current densities (IDS,max) of 620 and 480 mA/mm, respectively, indicating that the former showed a 29% increase relative to that of the non-recessed structure. Similarly, the peak extrinsic transconductance (gm,max) increased from 138 mS/mm for the device without
References
Frequency (GHz)
Gate length (lm)
IDS,max (mA/ mm)
gm,max (mS/ mm)
Power density (W/mm)
PAE
[23] [24] [25] [26] [27] This work
30 2.14 35 2 35 30
0.3 0.3 0.3 0.3 0.15 0.1
500 355 550 650 670 680
300 180 350 200 470 500
0.65 2.1 0.8 1.6 0.86 2.4
45 61 40 68 44 51
any recess to 200 mS/mm for the device with the wide gate recess. The breakdown voltage (Vbreak) is measured for the devices with the wide gate double recess and without any recess when the pinch-off gate bias was 5 V. These devices yielded breakdown voltages of 45 and 36 mA/mm, respectively, indicating that the former showed a 25% increase relative to that of the latter. Fig. 6 shows the I–V characteristics and transconductance of the devices fabricated by the double and single exposure process. The devices fabricated by the double-exposure e-beam lithography process exhibit better saturation and pitch-off characteristics than those fabricated by the single-exposure process. The devices fabricated by the double- and single-exposure processes yielded IDS,max of 680 and 620 mA/mm, respectively, indicating that the former showed a 13% increase relative to that of the latter. Similarly, the gm,max increased from 390 mS/mm for the device fabricated by
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Fig. 11. The measured short current gain and maximum stable gain versus frequency of an 8 (100 0.1) lm2 gate periphery.
the single-exposure process to 500 mS/mm for the double-exposure process. The typical I–V output and transfer characteristics of the double passivation, (A) and (C), and single passivation, (E) and (F), are shown in Fig. 7. The gate bias was kept below +1 V due to the unacceptably high forward gate current. Samples (A) and (C) exhibit
better drain current saturation and pitch-off characteristics than samples (E) and (F). Samples (A), (C), (E), and (F) yielded IDS,max values of 620, 510, 425, and 343 mA/mm, respectively. The double passivation devices show 46 and 49% increases relative to those of the single passivation ones. Similarly, their gm,max are 407, 310, 300, and 275 mS/mm, which indicates that the double passivation devices showed 36% and 15% increases relative to those of the single passivation ones. In contrast, to compare the devices with the Si3N4 and SiO2 double passivation layers, the three samples (A), (B), and (C) are studied, and the results are shown in Fig. 8. They yielded IDS,max values of 620, 510, and 590 mA/mm; the devices with the Si3N4 double passivation show 30% increases relative to those with the SiO2 double passivation. Similarly, gm,max values of 407, 310, and 338 mS/mm were measured; the Si3N4 double passivation devices show 28% increases relative to those of the SiO2 double passivation ones. Threshold voltages (Vth) of 4.5, 4.1, and 3.9 V are observed for samples (A), (B), and (C), respectively. This increase is mainly due to the larger separation between the gate and the two-dimensional electron gas (2DEG) channel. The passivation with Si3N4 has a relatively higher influence on the DC and transfer characteristics than the passivation with SiO2, which can be explained by the higher density of the SiO2/AlGaAs/InGaAs/GaAs interface state than the Si3N4/AlGaAs/InGaAs/GaAs interface state, and the lower deposition temperature of SiO2 compared with Si3N4. Fig. 9 shows the breakdown voltage (Vbreak) which are measured at the double and single passivation when the
Fig. 12. The novel AlGaAs/InGaAs/GaAs PHEMT fabrication process flow.
S.-J. Cho et al. / Microelectronic Engineering 113 (2014) 11–19
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power gain of approximately 6.1 dB and an output power of 27 dBm. At an input power of 25 dBm, the maximum output power density of 2.4 W/mm with a PAE of 44.6% and a power gain of 3.6 dB are obtained without any cooling of the chuck. Table 2 shows the GaAs PHEMTs fabricated by the proposed manufacturing process compared with previous works. The optimised fabrication methods show the best drain current and output power density obtained for GaAs PHEMTs on GaAs substrates with a 0.1 lm gate length. The good DC and RF performance associated with the high output power is attributed to the optimised device fabrication process and good material quality in high-frequency operations. 4. Summary of the reproducible full manufacturing process
Fig. 13. FIB picture of a source-to-source air bridge.
Fig. 12 shows a summary of the full manufacturing process of the AlGaAs/InGaAs/GaAs PHEMTs. AlGaAs/InGaAs/GaAs structured epitaxy materials are grown by MOCVD on a 6-in. SI-GaAs substrate. The proposed process starts with mesa isolation. The mesa isolation remains in place until the buffer layer is removed by ICP etching (Step 1). After mesa isolation, the AuGe/Ni/Au (200/ 30/120 nm) source and drain ohmic metal is deposited by an ebeam evaporator. After the ohmic metal lift-off, the samples are sequentially annealed under an N2 flow using the RTA process at 450 °C for 30 s (Step 2). After ohmic processing, wide double-recessed etching is conducted by GaAs ICP etching (Step 3). Next, a
Fig. 14. FIB picture of a 40 lm diameter source via-hole. Fig. 15. The fabricated AlGaAs/InGaAs/GaAs PHEMT with TFR and a MIM capacitor.
pinch-off gate bias is at 5 V. The double passivation fully blocked the leakage current as well as enhanced the drain to the source breakdown voltage. Table 1 shows the summary of DC properties of Si3N4 or SiO2 single and double passivated on AlGaAs/InGaAs/ GaAs PHEMTs. The small-signal RF performance is characterised using Sparameter measurements within the frequency range of 100 MHz–100 GHz. Fig. 10 shows the short-circuit current gain |h21| and the maximum stable gain (MSG) for the device with a 8 (100 0.1) lm2 gate periphery. The fT and fMAX values are determined by |h21| and the MSG, respectively. The extrinsic fT and fMAX values are 56 GHz and 84 GHz at VDS = 10 V and VGS = 3 V, respectively. Large-signal measurements are performed using a load–pull system at 30 GHz. The device is biased at a drain bias of 30 V. The measured input power (Pin) versus output power (Pout) responses of the device are illustrated in Fig. 11, which demonstrate a peak power added efficiency (PAE) of 50.5% at 21 dBm Pin with a
Fig. 16. The reproducible characteristics of the output power and gain between the previous and the optimised PHEMT manufacturing processes.
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Fig. 17. (a) The final fabricated device on a 6 in. SI-GaAs substrate, which includes (b) MIM capacitors, (c) thin film resistors, (d) spiral inductors, and (e) 0.1 lm GaAs PHEMTs.
gate recess surface passivation layer composed of Si3N4 or SiO2 is deposited by PECVD to a thickness of 100 nm. After the deposition of Si3N4 or SiO2, a 0.1 lm gate foot pattern is realised by doubleexposure electron beam lithography. After the developing process, ICP dry etching is conducted to selectively remove the Si3N4 or SiO2 (Step 4). After that, a 40/400 nm-thick Ni/Au T-gate metal layer is then formed by e-beam evaporation (Step 5), followed by a postgate N2 annealing process. Next, to realise the second gate passivation, a Si3N4 or SiO2 layer with a thickness of 100 nm is deposited by PECVD, and then ICP etching is performed to remove the undesired layer of Si3N4 or SiO2 (Step 6), followed by the e-beam evaporation of a 80 nm thick NiCr thin film resistor (TFR) and 20/ 300 nm thick Ti/Au interconnection metallisation, which are used to connect all of the gates and drains together with the resultant pads (Step 7). Next, an insulator consisting of 200 nm thick Si3N4 was deposited for the MIM capacitors (Step 8), and a 20/80 nm thick Ti/Au seed metal layer was deposited by metal sputtering for the metal plating process. The air-bridge photo process is then performed prior to the Au (3 lm) air-bridge metal definition and plating process, which connects the sources together with the pads. After the electroplating process, the air-bridge mask is stripped, the ICP metal etching of the Ti/Au seed metal is performed, as shown in Fig. 13 (Step 9), and all of the devices are passivated with Si3N4 to a thickness of 100 nm to protect the components from oxidation and moisture (Step 10). Finally, the backside process involving a 40 lm diameter via-hole (Fig. 14) is processed, and a Ti/Au seed metal layer with 3 lm Au plating is deposited for source grounding (Fig. 15) (Step 11). By using advanced fabrication techniques such as e-beam lithography, double passivation, and via process methods, an enhanced DC and RF performance reliability is achieved, and a cost-effective high-yield process is developed. Fig. 16 shows the reproducible process improvement of the target parameters with error bars in comparison with the previous and optimised process. The error bar is reduced to within 3.2% after optimising the fabrication process. Fig. 17 shows the final fabricated structure on a 6-in. GaAs wafer; the structure includes spiral inductors, MIM capacitors, and NiCr thin film resistors based on the proposed process. More than 5000 components are fabricated at a time to realise a monolithic microwave integrated circuit (MMIC) concept of a power amplifier; the MMIC process has a cost advantage compared with wire-bonding-based matching circuits.
5. Conclusions To achieve the required performance improvement for high power applications in RF and microwave systems, we proposed
optimised solutions. First, an optimised AlGaAs/InGaAs/GaAs epistructure using a changeable AlGaAs barrier thickness and Al composition is proposed. Second, the use of an advanced 0.1 lm gate manufacturing process with a double-exposure method using electron beam lithography and a wide gate recess process increase the drain-to-source breakdown voltage. More stable operation can be achieved in the high-frequency range. Third, a double-gate supported passivation scheme (Si3N4/Si3N4; SiO2/SiO2; SiO2/Si3N4; Si3N4/SiO2) is proposed first for AlGaAs/InGaAs/GaAs PHEMTs, which enhances the DC and RF characteristics of AlGaAs/InGaAs/ GaAs PHEMTs on SI-GaAs substrates. Based on the optimised fabrication, excellent DC and RF performances are achieved for a gate length of 0.1 lm. A maximum output power density of 2.4 W/ mm is achieved at 30 GHz, with an associated gain of 6.1 dB and a PAE of 44.6%. Thus, this manufacturing process is the optimal solution for fabricating AlGaAs/InGaAs/GaAs PHEMTs in Ka-band high-power applications that require cost efficiency and high performance. Acknowledgements This research was supported by a National Research Foundation of Korea (NRF) Grant funded by the Korea government (MEST) (No. 2012-0009224). This work was also supported by a Research Grant from Kwangwoon University in 2013. References [1] N.I. Carmeron, S. Murad, H. McLelland, A. Asenov, M.R.S. Taylor, M.C. Holland, S.P. Beaumount, Electron. Lett. 32 (1996) 770. [2] J. Goel, K.L. Tan, D.I. Stones, R.W. Chan, D.C. Streit, S. Peratoner, J. Schellenberg, IEEE Microw. Theory Tech. Symp. Digest 2 (1992) 587. [3] K.L. Tan, R.M. Dia, D.C. Streit, L.K. Shaw, A.C. Han, M.D. Sholley, P.H. Liu, T.Q. Trinh, T. Lin, H.C. Yen, IEEE Electron Device Lett. 12 (1991) 23. [4] X. Cao, E. Boyd, H. Mclelland, S. Thoms, M. Holland, C. Stanley, I. Thayne, in: 11th European Gallium Arsenide and Other Compound Semiconductors Application Symp., 2003, p. 13. [5] K. Shinohara, Y. Yamashita, A. Endoh, K. Hikosaka, T. Matsui, S. Hiyamizu, IEEE Electron Device Lett. 11 (2001) 507. [6] X. Li, K. Elgaid, H. McLelland, I.G. Thayne, Microelectron. Eng. 57 (2001) 633. [7] D. Moran, E. Boyd, H. McLelland, K. Elgaid, Microelectron. Eng. 67 (2003) 769. [8] P.M. Frijlink, A. Collet, J. Bellaiche, M. Iost, M.J. Verheijen, H.R.J.R. van Helleputte, W.G.J. Moors, F.C.M.J.M. van Delft, Microelectron. Eng. 35 (1997) 313. [9] H.S. Kim, B.O. Lim, S.C. Kim, S.D. Lee, D.H. Shin, J.K. Rhee, Microelectron. Eng. 63 (2002) 417. [10] B.P. Gila, G.T. Thaler, A.H. Onstine, M. Hlad, A. Gerger, Solid State Elec. 50 (2006) 6. [11] J.Y. Shiu, V. Desmaris, N. Rorsman, K. Kumakura, T. Makimoto, Semicond. Sci. Technol. 22 (2007) 7. [12] N. Shigekawa, S. Sugitani, IEICE Elec. Express 6 (2009) 14. [13] J.W. Lee, V. Kumar, I. Adesida, Jpn. J. Appl. Phys. 45 (2006) 13. [14] D.M. Gill, B.C. Kane, S.P. Svensson, D.W. Tu, P.N. Uppal, N.E. Byer, IEEE Electron Device Lett. 17 (1996) 328.
S.-J. Cho et al. / Microelectronic Engineering 113 (2014) 11–19 [15] M. Daoudi, I. Dhifallah, A. Ouerghi, R. Chtourou, Superlattice Microst. 51 (2012) 497. [16] S.J. Cho, C. Wang, N.Y. Kim, Thin Solid Films 520 (2012) 4455. [17] R. Grundbacher, I. Adesida, Y.C. Kao, A.A. Ketterson, J. Vac. Sci. Technol. 15 (1997) 49. [18] S.C. Kim, B.O. Lim, H.S. Lee, D.H. Shin, S.K. Kim, H.C. Park, J.K. Rhee, Mater. Sci. Semicond. Process. 7 (2004) 7. [19] C. Wang, W.S. Lee, F. Zhang, N.Y. Kim, Int. J. Adv. Manuf. Technol. 52 (2010) 1011. [20] I. Harrison, W. Clayton, W. Jeffs, Phys. Stat. Solidi (A) 188 (2001) 275. [21] C. Wang, N.Y. Kim, Microw. Opt. Tech. Lett. 53 (2011) 789. [22] J.H. Oh, M. Han, Y.H. Baek, S.W. Moon, J.K. Rhee, S.D. Kim, Semicond. Sci. Technol. 24 (2009) 025027.
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[23] H. Amasuga, A. Inoue, S. Goto, T. Kunii, Y. Yamamoto, T. Oku, T. Ishikawa, in: IEEE MTT-S Int’l Microw. Symposium, 2007, p. 821. [24] B.M. Green, E. Lan, P. Li, O. Hartin, C.A. Gaw, M. CdeBaca, E.M. Johnson, L.S. Klingbeil, P. Fisher, J. Kim, D. Maurer, B. Knappenberger, M. Miller, C.E. Weitzel, IEEE MTT-S Digest 2 (2004) 817. [25] H. Amasuga, S. Goto, T. Shiga, M. Totsuka, T. Kunii, T. Oku, T. Ishikawa, Y. Matsuda, in: IEEE MTT-S Int’l Microw. Symposium, 2005, p. 831. [26] W. Marsetz, A. Hulsmann, K. Kohler, M. Demmler, M. Schlechtweg, Electron. Lett. 35 (1999) 748. [27] M.Y. Kao, S. Nayak, R. Hajji, S.E. Hillyard, A.A. Ketterson, in: IEEE MTT-S Int’l Microw. Symposium, 2006, p. 129.
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High power density AlGaAs/InGaAs/GaAs PHEMTs using an optimised manufacturing process for Ka-band applications Sung-Jin Cho, Cong Wang, Nam-Young Kim ⇑ RFIC Research Center, Kwangwoon University, 447-1 Wolgye-dong, Nowon-Ku, Seoul, Republic of Korea
a r t i c l e
i n f o
Article history: Received 5 March 2012 Received in revised form 29 April 2013 Accepted 1 July 2013 Available online 11 July 2013 Keywords: AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistors (PHEMT) Passivation Gate recess e-Beam lithography Breakdown voltage Output power
a b s t r a c t In this study, a novel manufacturing process for a 0.1 lm T-gate is investigated for producing a high output power performance for the Ka-band frequencies using high-quality AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistors (PHEMTs) on semi-insulated (SI) GaAs substrates. The gate manufacturing process is the most important process due to its intimate relationship with the DC and RF performance of the device. To improve the gate performances of PHEMT devices, we investigated various materials and processing approaches involving a wide gate recess, double exposure by e-beam lithography, and low-damage double-gate passivation methods based on plasma-enhanced chemical vapour deposition (PECVD). To reduce the sensitivity to current collapse effects, we investigate the relationship between the electrical characteristics of the PHEMTs and top and bottom gate-supported passivation films. To improve the ohmic contact performance, we test an AuGe/Ni/Au (200/30/120 nm) ohmic contact metallisation scheme using the rapid thermal annealing (RTA) process at temperatures ranging from 450 °C 30 s. A PHEMT with a gate length of 0.1 lm, exhibiting a maximum drain current density of 680 mA/mm, a peak transconductance of 500 mS/mm, a unity-gain cut-off frequency (fT) of 56 GHz, and a maximum frequency of oscillation (fMAX) of 84 GHz, is demonstrated using this novel manufacturing process; the Ka-band power performance includes an output power density of 2.4 W/mm and a power-added efficiency (PAE) of 44.6%. Ó 2013 Elsevier B.V. All rights reserved.
1. Introduction Due to their excellent high-frequency operation, high efficiency, high power, and low-noise performance, AlGaAs/InGaAs/GaAs PHEMTs are emerging as promising candidates for radio frequency (RF) components, such as low-noise amplifiers or power amplifiers for the next-generation of commercial wireless communication systems [1–4]. In particular, in the case of extremely high frequencies, GaAs-based PHEMTs have attracted a great deal of interest as active components. For optimised high-frequency operation, highquality gate fabrication, reduced parasitic gate resistance (Rg), and high power performance are the most important issues to determine the performance of PHEMTs. Low Rg can be obtained at high frequencies, and high value of fT and fmax can be obtained. To reduce the gate resistance, T-shaped gates with a small gate length and large cross-sectional area are required [5–7]. T-gate fabrication can be based on electron beam lithography with multiple resist layers [8,9]. The gate length (Lg), and the thickness of the passivation layer are the major factors affecting the gate capacitance (Cgs), which is a key parameter in determining the RF performance
⇑ Corresponding author. Tel.: +82 29405071; fax: +82 29425235. E-mail addresses: [email protected], [email protected] (N.-Y. Kim). 0167-9317/$ - see front matter Ó 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.mee.2013.07.001
in the high-frequency range. The T-gate head is a function of the reduction of Rg. However, at the same time, the T-gate head is a function of the increase in Cgs [10–12]. Likewise, to increase the output power, the high drain current density, high breakdown voltage, and knee voltage are required. These relationships can be shown in a simple equation:
Pout ¼
IDS;max ðV break V knee Þ 8
ð1Þ
where IDS,max is the maximum drain current from DC measurements and Vbreak and Vknee are the breakdown and knee voltages, respectively [13]. To obtain high power, there are three key parameters, as shown in Eq. (1): a high drain current density, high breakdown voltage, and low knee voltage. In spite of its high-frequency performance, unfortunately, GaAs PHEMTs have a high drain current density and a high breakdown voltage performance compared with GaN HEMT structures due to the different epi material characteristics and structures. Moreover, the large gate leakage current and current dispersion that are generated due to the surface states remain the most significant obstacles to high-frequency operation in AlGaAs/InGaAs/GaAs PHEMTs. It is noted that the current collapse condition can be considerably improved by surface passivation methods [14].
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2. Experimental procedure
Fig. 1. A cross-sectional schematic diagram of an AlGaAs/InGaAs/GaAs PHEMT.
To increase output power using the GaAs epi structure, in this work, we employed a SI-GaAs substrate-based AlGaAs/InGaAs/ GaAs PHEMT fabrication process, which is highly competitive in terms of the device performance and cost. To improve the device characteristics, several optimised processes are presented. First, an optimised AlGaAs/InGaAs/GaAs epi-structure using a changeable AlGaAs barrier thickness and Al composition is proposed [15]. Second, to mitigate the current collapse problem and increase Cgs, a double-gate-supported passivation scheme (Si3N4/Si3N4; SiO2/SiO2; SiO2/Si3N4; Si3N4/SiO2) is first proposed for AlGaAs/InGaAs/GaAs PHEMTs [16]. In addition, a damage-free dry/wet-etching method is proposed that removes the undesirable passivation layers. Passivation films provide effective improvements that mitigate the current collapse phenomenon. However, the suppression of the current collapse phenomenon in high-frequency and high-power operations cannot be achieved using only the passivation process. An advanced 0.1 lm gate manufacturing process with a doubleexposure method using electron beam lithography and a wide gate recess process increases the drain-to-source breakdown voltage, and more stable operation can be achieved in the high-frequency range.
AlGaAs/InGaAs/GaAs-structured epitaxy materials are grown by metal organic chemical vapour deposition (MOCVD) on a 6-in. SIGaAs substrate, which consists of the following layers: a 3000 Å GaAs, 2150 Å Al0.22GaAs/GaAs buffer, silicon delta first doping of 1.5 1012 cm2, 40 Å Al0.22GaAs spacer, 110 Å In0.22GaAs channel, 30 Å Al0.22GaAs spacer, silicon delta second doping of 5 1012 cm2, 180 Å Al0.22GaAs barrier, 230 Å GaAs cap layer, silicon delta final doping of 6 1012 cm2, and 70 Å In0.22GaAs cap layer. The proposed process starts with mesa isolation, after which the AuGe/Ni/Au (200/30/120 nm) source and drain ohmic metal is deposited by an e-beam evaporator. After the ohmic metal lift-off process, the samples are sequentially annealed under an N2 flow using the rapid thermal annealing (RTA) process at temperatures ranging from 450 °C 30 s. After the RTA processing, the specific contact resistances (qc) are measured by the transfer length method (TLM); the square (100 100 lm) contacts are separated by 2, 4, 8, 16, and 32 lm. The circular TLM data indicated a qc of below 105 Ohm cm2 with a sheet resistance of approximately 400 Ohm/sq. After ohmic processing, wide double-recessed etching is conducted. A gate recess surface passivation layer composed of Si3N4 or SiO2 is then deposited by PECVD to a thickness of 100 nm. After the deposition of Si3N4 or SiO2, a 0.1 lm gate foot pattern is realised by double-exposed e-beam lithography. After the developing process, inductively coupled plasma (ICP) dry etching is performed to selectively remove the Si3N4 or SiO2. After that, a Ni/Au (40/ 400 nm) T-gate with a length of 0.1 lm was formed between the source and drain ohmic contacts. The passivation process was performed after all of the aforementioned steps, followed by the formation of vias to open the metal contacts. A cross-sectional schematic diagram of an AlGaAs/InGaAs/GaAs PHEMT on a SI-GaAs substrate is shown in Fig. 1. 2.1. Wide gate double recess process method Due to the creation of a depletion region, the flow of current from source to drain is blocked and, eventually, only a small amount of current flows compared with the supplied voltage. This implies that the breakdown voltage of the device is not good, which can be solved by the wide double-recessed process [17]. Through the use of a wide recess with gate recess, the area of the channel covered by external air can be decreased by establishing
Fig. 2. Flow chart of the double-exposure e-beam lithography method.
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Fig. 3. FIB picture of a 0.1 lm T-gate AlGaAs/InGaAs/GaAs PHEMT.
Fig. 4. FIB picture of the fabricated PHEMT with a 8 (100 0.1) lm2 gate periphery.
contact with the depletion region. A 70 Å thick In0.22GaAs layer with a 130 Å GaAs epi-layer is etched by ICP dry etching for the formation of the wide recessed structure and a 200 Å thick GaAs epilayer is subsequently etched by ICP dry etching for the formation of the recessed gate structure. The width of the wide recess is 5 lm, and that of the gate recess is 1 lm.
2.2. Realisation of a 0.1 lm gate process using the double-exposure ebeam lithography method The parasitic resistance can be reduced by minimising the value of the ohmic resistance and reducing the gate length. Additionally, a narrow distance between the gate and drain (source) can also reduce the parasitic resistance, so they should be arrayed closely when using an advanced exposure technique such as e-beam lithography. In the case of a simple rectangular metal gate, the shorter the gate length, the more the parasitic resistance can be increased. Therefore, a T-gate is often used to reduce the gate parasitic resistance, especially in the form of multiple fingers because in this way, the unit length of the gate can be reduced. To make T-shaped gate, single and double-exposure methods are used.
Fig. 5. (a) I–V characteristics with varying gate biases, (b) transconductance characteristics, and (c) breakdown voltage characteristics for wide gate recessed and non-recessed PHEMTs.
The double-exposure technique is better than the single-exposure technique because the second exposure has a forward scattering and decreases the electrons [18]. As a result, the double-exposure technique leads to good uniformity after development and a clear T-shaped structure. Fig. 2 shows a flow chart of a novel 0.1 lm gate fabricated by JBX6000FS/E e-beam lithography. An accelerating voltage of 50 kV, probe beam current of 1 nA, and beam resolution of 50 nm were used for the e-beam lithography. We investigated the use of a double-exposure technique on special ZEP-PMGIPMMA trilayer photoresists, which have excellent metal lift-off characteristics.
2.3. Low-damage double gate supported passivation method using plasma-enhanced chemical vapour deposition Silicon nitride and silicon dioxide dielectric materials are widely used in the manufacturing processes of various compound
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SiO2 for the second gate passivation (D), 100 nm SiO2 for the first passivation and 100 nm Si3N4 for the second gate passivation, (E) 100 nm Si3N4 for the second passivation without the first gate passivation, and (F) 100 nm SiO2 for the second passivation without the first passivation. All of the experiments are referenced to the single passivation layer case. Before Si3N4 deposition, the conditions used for PECVD are important because the RF power, chamber temperature, and pressure significantly affect the damage to the ohmic and epi-layer. The deposition of Si3N4 and SiO2 that is 50% tensile and 50% compressive is performed in an OERLIKON VL-LA-PECVD system. Different He gas flow ratios, chamber pressures of 900 and 1200 mTorr, chamber temperatures of 150 and 250 °C, an RF frequency of 13.56 MHz, and RF powers of 60 and 100 W are used for the PECVD-deposited Si3N4 and SiO2, respectively. The DC I–V characteristics are measured at VDS = 0–15 V and VGS = 1 to 5 V for all of the samples. However, we note that the top Si3N4 layer of sample (D) is broken, owing to the interaction between the different types of stresses of the inner thin films, and therefore, this structure cannot be considered. 3. Results and discussion
Fig. 6. (a) I–V characteristics with varying gate biases and (b) transconductance characteristics after single and double-exposure e-beam lithography.
semiconductor devices and circuits. These processes include the device passivation of integrated passive devices (IPDs) [19], metal-oxide-semiconductor field-effect transistors (MOSFETs) [20] and hetero-junction bipolar transistors (HBTs) [21], masking layers, dielectric layers for metal–insulator–metal (MIM) capacitors, and wafer-level final passivation to protect the circuit against mechanical scratches. The effects of Si3N4 passivation are reported to improve the DC and RF properties in AlGaAs/InGaAs/GaAs-based PHEMTs [22]. Without passivation, the exposed surface of the GaAs epilayer can be damaged by oxidation, moisture, and other forms of pollution. After the double-recessed process, a 100 nm thick layer of Si3N4 is deposited on the GaAs epilayer by PECVD. Subsequently, after the final development of the PMMA photoresist, which is used to make the T-gate high footprint dose via e-beam lithography, Si3N4 is first etched by ICP etching. To avoid the damage to the n-AlGaAs gate contact epitaxy layer caused by dry plasma etching, the Si3N4 is etched out using a dry/wet etching method. First, 80 nm of the Si3N4 is dry-etched by an ICP etching system, and then the remaining 20 nm is wet-etched by a 1:6 buffered oxide etch (BOE) solution. Because the BOE is very sensitive to the pattern size, film quality, and environmental conditions, a dummy wafer is needed during the overall dry/wet etching process. The focused ion beam (FIB) images of the cross-sectional 0.1 lm T-gate with an AlGaAs/InGaAs/GaAs PHEMT are shown in Fig. 3. The pillar of the T-gate is surrounded by the Si3N4 first passivation layer to help reduce the gate contact resistance. After the deposition of the Ni/Au (40/400 nm) gate by an e-beam evaporator, 100 nm thick Si3N4 second dielectric layers are deposited on top of the gate. An analysis of the top and bottom gate passivation was conducted for six cases: (A) 100 nm Si3N4 for the first passivation and 100 nm Si3N4 for the second gate passivation, (B) 100 nm SiO2 for the first passivation and 100 nm SiO2 for the second gate passivation, (C) 100 nm Si3N4 for the first passivation and 100 nm
A SI-GaAs substrate with high-quality MOCVD-deposited epilayers and a novel fabrication technology consisting of double gate recessing, double exposure of e-beam lithography, a double passivation process, and an AuGe/Ni/Au-based ohmic contact process are employed to realise high-performance AlGaAs/InGaAs/GaAs PHEMTs. Fig. 4 shows a FIB image of a fabricated 100 lm 8-finger freestanding PHEMT with a gate length of 0.1 lm, drain–gate spacing of 2 lm, and gate–source spacing of 1 lm. Fig. 5 shows the I–V characteristics, transconductance, and breakdown voltage of the
Fig. 7. (a) I–V characteristics with varying gate biases and (b) transconductance characteristics of single and double passivation.
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Table 1 DC properties of Si3N4 or SiO2 single and double passivation on AlGaAs/InGaAs/GaAs PHEMTs.
IDS,max (mA/ mm) gm,max (mS/ mm) Vth (V) Vknee (V) Ith (uA/ mm) Vbreak (V)
Si3N4/ Si3N4
SiO2/ SiO2
Si3N4/ SiO2
Si3N4
SiO2
620
510
590
425
343
At VGS = +1 V
400
310
338
300
270
At VDS = 10 V
4.5 5.3 0.44
3.9 5.1 0.52
4.1 5.1 0.6
3.7 5.5 18.2
5 5 31.9
34
45
42
22
29
At VGS = +1 V At VGS = +1 V At VGS = 5 V, at VDS = 10 V At VGS = 5 V
Fig. 8. (a) I–V characteristics with varying gate biases and (b) transconductance characteristics of Si3N4/Si3N4; SiO2/SiO2; Si3N4/SiO2 double passivation. Fig. 10. The measured short current gain and maximum stable gain versus frequency of an 8 (100 0.1) lm2 gate periphery on an AlGaAs/InGaAs/GaAs PHEMT.
Table 2 Summary of the published GaAs PHEMTs with a description of the DC and RF performance.
Fig. 9. Breakdown voltage (Vbreak) characteristics of Si3N4/Si3N4, SiO2/SiO2, Si3N4/ SiO2 double passivation and Si3N4, SiO2 single scheme passivation at 5 V pinch off gate voltage.
wide double-recessed and non-recessed processes. The DC characteristics of the devices are measured at room temperature using a Keithley 4200-SCS/F semiconductor parameter analyser. The DC I– V characteristics are measured at VDS = 0–15 V and VGS = 1 to 5 V for all of the samples. The gate bias is kept below +1 V due to the unacceptably high forward gate current. The wide gate doublerecessed structure exhibits better saturation and pitch-off characteristics than the non-recessed structure. The recessed and non-recessed devices yielded maximum saturation current densities (IDS,max) of 620 and 480 mA/mm, respectively, indicating that the former showed a 29% increase relative to that of the non-recessed structure. Similarly, the peak extrinsic transconductance (gm,max) increased from 138 mS/mm for the device without
References
Frequency (GHz)
Gate length (lm)
IDS,max (mA/ mm)
gm,max (mS/ mm)
Power density (W/mm)
PAE
[23] [24] [25] [26] [27] This work
30 2.14 35 2 35 30
0.3 0.3 0.3 0.3 0.15 0.1
500 355 550 650 670 680
300 180 350 200 470 500
0.65 2.1 0.8 1.6 0.86 2.4
45 61 40 68 44 51
any recess to 200 mS/mm for the device with the wide gate recess. The breakdown voltage (Vbreak) is measured for the devices with the wide gate double recess and without any recess when the pinch-off gate bias was 5 V. These devices yielded breakdown voltages of 45 and 36 mA/mm, respectively, indicating that the former showed a 25% increase relative to that of the latter. Fig. 6 shows the I–V characteristics and transconductance of the devices fabricated by the double and single exposure process. The devices fabricated by the double-exposure e-beam lithography process exhibit better saturation and pitch-off characteristics than those fabricated by the single-exposure process. The devices fabricated by the double- and single-exposure processes yielded IDS,max of 680 and 620 mA/mm, respectively, indicating that the former showed a 13% increase relative to that of the latter. Similarly, the gm,max increased from 390 mS/mm for the device fabricated by
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Fig. 11. The measured short current gain and maximum stable gain versus frequency of an 8 (100 0.1) lm2 gate periphery.
the single-exposure process to 500 mS/mm for the double-exposure process. The typical I–V output and transfer characteristics of the double passivation, (A) and (C), and single passivation, (E) and (F), are shown in Fig. 7. The gate bias was kept below +1 V due to the unacceptably high forward gate current. Samples (A) and (C) exhibit
better drain current saturation and pitch-off characteristics than samples (E) and (F). Samples (A), (C), (E), and (F) yielded IDS,max values of 620, 510, 425, and 343 mA/mm, respectively. The double passivation devices show 46 and 49% increases relative to those of the single passivation ones. Similarly, their gm,max are 407, 310, 300, and 275 mS/mm, which indicates that the double passivation devices showed 36% and 15% increases relative to those of the single passivation ones. In contrast, to compare the devices with the Si3N4 and SiO2 double passivation layers, the three samples (A), (B), and (C) are studied, and the results are shown in Fig. 8. They yielded IDS,max values of 620, 510, and 590 mA/mm; the devices with the Si3N4 double passivation show 30% increases relative to those with the SiO2 double passivation. Similarly, gm,max values of 407, 310, and 338 mS/mm were measured; the Si3N4 double passivation devices show 28% increases relative to those of the SiO2 double passivation ones. Threshold voltages (Vth) of 4.5, 4.1, and 3.9 V are observed for samples (A), (B), and (C), respectively. This increase is mainly due to the larger separation between the gate and the two-dimensional electron gas (2DEG) channel. The passivation with Si3N4 has a relatively higher influence on the DC and transfer characteristics than the passivation with SiO2, which can be explained by the higher density of the SiO2/AlGaAs/InGaAs/GaAs interface state than the Si3N4/AlGaAs/InGaAs/GaAs interface state, and the lower deposition temperature of SiO2 compared with Si3N4. Fig. 9 shows the breakdown voltage (Vbreak) which are measured at the double and single passivation when the
Fig. 12. The novel AlGaAs/InGaAs/GaAs PHEMT fabrication process flow.
S.-J. Cho et al. / Microelectronic Engineering 113 (2014) 11–19
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power gain of approximately 6.1 dB and an output power of 27 dBm. At an input power of 25 dBm, the maximum output power density of 2.4 W/mm with a PAE of 44.6% and a power gain of 3.6 dB are obtained without any cooling of the chuck. Table 2 shows the GaAs PHEMTs fabricated by the proposed manufacturing process compared with previous works. The optimised fabrication methods show the best drain current and output power density obtained for GaAs PHEMTs on GaAs substrates with a 0.1 lm gate length. The good DC and RF performance associated with the high output power is attributed to the optimised device fabrication process and good material quality in high-frequency operations. 4. Summary of the reproducible full manufacturing process
Fig. 13. FIB picture of a source-to-source air bridge.
Fig. 12 shows a summary of the full manufacturing process of the AlGaAs/InGaAs/GaAs PHEMTs. AlGaAs/InGaAs/GaAs structured epitaxy materials are grown by MOCVD on a 6-in. SI-GaAs substrate. The proposed process starts with mesa isolation. The mesa isolation remains in place until the buffer layer is removed by ICP etching (Step 1). After mesa isolation, the AuGe/Ni/Au (200/ 30/120 nm) source and drain ohmic metal is deposited by an ebeam evaporator. After the ohmic metal lift-off, the samples are sequentially annealed under an N2 flow using the RTA process at 450 °C for 30 s (Step 2). After ohmic processing, wide double-recessed etching is conducted by GaAs ICP etching (Step 3). Next, a
Fig. 14. FIB picture of a 40 lm diameter source via-hole. Fig. 15. The fabricated AlGaAs/InGaAs/GaAs PHEMT with TFR and a MIM capacitor.
pinch-off gate bias is at 5 V. The double passivation fully blocked the leakage current as well as enhanced the drain to the source breakdown voltage. Table 1 shows the summary of DC properties of Si3N4 or SiO2 single and double passivated on AlGaAs/InGaAs/ GaAs PHEMTs. The small-signal RF performance is characterised using Sparameter measurements within the frequency range of 100 MHz–100 GHz. Fig. 10 shows the short-circuit current gain |h21| and the maximum stable gain (MSG) for the device with a 8 (100 0.1) lm2 gate periphery. The fT and fMAX values are determined by |h21| and the MSG, respectively. The extrinsic fT and fMAX values are 56 GHz and 84 GHz at VDS = 10 V and VGS = 3 V, respectively. Large-signal measurements are performed using a load–pull system at 30 GHz. The device is biased at a drain bias of 30 V. The measured input power (Pin) versus output power (Pout) responses of the device are illustrated in Fig. 11, which demonstrate a peak power added efficiency (PAE) of 50.5% at 21 dBm Pin with a
Fig. 16. The reproducible characteristics of the output power and gain between the previous and the optimised PHEMT manufacturing processes.
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Fig. 17. (a) The final fabricated device on a 6 in. SI-GaAs substrate, which includes (b) MIM capacitors, (c) thin film resistors, (d) spiral inductors, and (e) 0.1 lm GaAs PHEMTs.
gate recess surface passivation layer composed of Si3N4 or SiO2 is deposited by PECVD to a thickness of 100 nm. After the deposition of Si3N4 or SiO2, a 0.1 lm gate foot pattern is realised by doubleexposure electron beam lithography. After the developing process, ICP dry etching is conducted to selectively remove the Si3N4 or SiO2 (Step 4). After that, a 40/400 nm-thick Ni/Au T-gate metal layer is then formed by e-beam evaporation (Step 5), followed by a postgate N2 annealing process. Next, to realise the second gate passivation, a Si3N4 or SiO2 layer with a thickness of 100 nm is deposited by PECVD, and then ICP etching is performed to remove the undesired layer of Si3N4 or SiO2 (Step 6), followed by the e-beam evaporation of a 80 nm thick NiCr thin film resistor (TFR) and 20/ 300 nm thick Ti/Au interconnection metallisation, which are used to connect all of the gates and drains together with the resultant pads (Step 7). Next, an insulator consisting of 200 nm thick Si3N4 was deposited for the MIM capacitors (Step 8), and a 20/80 nm thick Ti/Au seed metal layer was deposited by metal sputtering for the metal plating process. The air-bridge photo process is then performed prior to the Au (3 lm) air-bridge metal definition and plating process, which connects the sources together with the pads. After the electroplating process, the air-bridge mask is stripped, the ICP metal etching of the Ti/Au seed metal is performed, as shown in Fig. 13 (Step 9), and all of the devices are passivated with Si3N4 to a thickness of 100 nm to protect the components from oxidation and moisture (Step 10). Finally, the backside process involving a 40 lm diameter via-hole (Fig. 14) is processed, and a Ti/Au seed metal layer with 3 lm Au plating is deposited for source grounding (Fig. 15) (Step 11). By using advanced fabrication techniques such as e-beam lithography, double passivation, and via process methods, an enhanced DC and RF performance reliability is achieved, and a cost-effective high-yield process is developed. Fig. 16 shows the reproducible process improvement of the target parameters with error bars in comparison with the previous and optimised process. The error bar is reduced to within 3.2% after optimising the fabrication process. Fig. 17 shows the final fabricated structure on a 6-in. GaAs wafer; the structure includes spiral inductors, MIM capacitors, and NiCr thin film resistors based on the proposed process. More than 5000 components are fabricated at a time to realise a monolithic microwave integrated circuit (MMIC) concept of a power amplifier; the MMIC process has a cost advantage compared with wire-bonding-based matching circuits.
5. Conclusions To achieve the required performance improvement for high power applications in RF and microwave systems, we proposed
optimised solutions. First, an optimised AlGaAs/InGaAs/GaAs epistructure using a changeable AlGaAs barrier thickness and Al composition is proposed. Second, the use of an advanced 0.1 lm gate manufacturing process with a double-exposure method using electron beam lithography and a wide gate recess process increase the drain-to-source breakdown voltage. More stable operation can be achieved in the high-frequency range. Third, a double-gate supported passivation scheme (Si3N4/Si3N4; SiO2/SiO2; SiO2/Si3N4; Si3N4/SiO2) is proposed first for AlGaAs/InGaAs/GaAs PHEMTs, which enhances the DC and RF characteristics of AlGaAs/InGaAs/ GaAs PHEMTs on SI-GaAs substrates. Based on the optimised fabrication, excellent DC and RF performances are achieved for a gate length of 0.1 lm. A maximum output power density of 2.4 W/ mm is achieved at 30 GHz, with an associated gain of 6.1 dB and a PAE of 44.6%. Thus, this manufacturing process is the optimal solution for fabricating AlGaAs/InGaAs/GaAs PHEMTs in Ka-band high-power applications that require cost efficiency and high performance. Acknowledgements This research was supported by a National Research Foundation of Korea (NRF) Grant funded by the Korea government (MEST) (No. 2012-0009224). This work was also supported by a Research Grant from Kwangwoon University in 2013. References [1] N.I. Carmeron, S. Murad, H. McLelland, A. Asenov, M.R.S. Taylor, M.C. Holland, S.P. Beaumount, Electron. Lett. 32 (1996) 770. [2] J. Goel, K.L. Tan, D.I. Stones, R.W. Chan, D.C. Streit, S. Peratoner, J. Schellenberg, IEEE Microw. Theory Tech. Symp. Digest 2 (1992) 587. [3] K.L. Tan, R.M. Dia, D.C. Streit, L.K. Shaw, A.C. Han, M.D. Sholley, P.H. Liu, T.Q. Trinh, T. Lin, H.C. Yen, IEEE Electron Device Lett. 12 (1991) 23. [4] X. Cao, E. Boyd, H. Mclelland, S. Thoms, M. Holland, C. Stanley, I. Thayne, in: 11th European Gallium Arsenide and Other Compound Semiconductors Application Symp., 2003, p. 13. [5] K. Shinohara, Y. Yamashita, A. Endoh, K. Hikosaka, T. Matsui, S. Hiyamizu, IEEE Electron Device Lett. 11 (2001) 507. [6] X. Li, K. Elgaid, H. McLelland, I.G. Thayne, Microelectron. Eng. 57 (2001) 633. [7] D. Moran, E. Boyd, H. McLelland, K. Elgaid, Microelectron. Eng. 67 (2003) 769. [8] P.M. Frijlink, A. Collet, J. Bellaiche, M. Iost, M.J. Verheijen, H.R.J.R. van Helleputte, W.G.J. Moors, F.C.M.J.M. van Delft, Microelectron. Eng. 35 (1997) 313. [9] H.S. Kim, B.O. Lim, S.C. Kim, S.D. Lee, D.H. Shin, J.K. Rhee, Microelectron. Eng. 63 (2002) 417. [10] B.P. Gila, G.T. Thaler, A.H. Onstine, M. Hlad, A. Gerger, Solid State Elec. 50 (2006) 6. [11] J.Y. Shiu, V. Desmaris, N. Rorsman, K. Kumakura, T. Makimoto, Semicond. Sci. Technol. 22 (2007) 7. [12] N. Shigekawa, S. Sugitani, IEICE Elec. Express 6 (2009) 14. [13] J.W. Lee, V. Kumar, I. Adesida, Jpn. J. Appl. Phys. 45 (2006) 13. [14] D.M. Gill, B.C. Kane, S.P. Svensson, D.W. Tu, P.N. Uppal, N.E. Byer, IEEE Electron Device Lett. 17 (1996) 328.
S.-J. Cho et al. / Microelectronic Engineering 113 (2014) 11–19 [15] M. Daoudi, I. Dhifallah, A. Ouerghi, R. Chtourou, Superlattice Microst. 51 (2012) 497. [16] S.J. Cho, C. Wang, N.Y. Kim, Thin Solid Films 520 (2012) 4455. [17] R. Grundbacher, I. Adesida, Y.C. Kao, A.A. Ketterson, J. Vac. Sci. Technol. 15 (1997) 49. [18] S.C. Kim, B.O. Lim, H.S. Lee, D.H. Shin, S.K. Kim, H.C. Park, J.K. Rhee, Mater. Sci. Semicond. Process. 7 (2004) 7. [19] C. Wang, W.S. Lee, F. Zhang, N.Y. Kim, Int. J. Adv. Manuf. Technol. 52 (2010) 1011. [20] I. Harrison, W. Clayton, W. Jeffs, Phys. Stat. Solidi (A) 188 (2001) 275. [21] C. Wang, N.Y. Kim, Microw. Opt. Tech. Lett. 53 (2011) 789. [22] J.H. Oh, M. Han, Y.H. Baek, S.W. Moon, J.K. Rhee, S.D. Kim, Semicond. Sci. Technol. 24 (2009) 025027.
19
[23] H. Amasuga, A. Inoue, S. Goto, T. Kunii, Y. Yamamoto, T. Oku, T. Ishikawa, in: IEEE MTT-S Int’l Microw. Symposium, 2007, p. 821. [24] B.M. Green, E. Lan, P. Li, O. Hartin, C.A. Gaw, M. CdeBaca, E.M. Johnson, L.S. Klingbeil, P. Fisher, J. Kim, D. Maurer, B. Knappenberger, M. Miller, C.E. Weitzel, IEEE MTT-S Digest 2 (2004) 817. [25] H. Amasuga, S. Goto, T. Shiga, M. Totsuka, T. Kunii, T. Oku, T. Ishikawa, Y. Matsuda, in: IEEE MTT-S Int’l Microw. Symposium, 2005, p. 831. [26] W. Marsetz, A. Hulsmann, K. Kohler, M. Demmler, M. Schlechtweg, Electron. Lett. 35 (1999) 748. [27] M.Y. Kao, S. Nayak, R. Hajji, S.E. Hillyard, A.A. Ketterson, in: IEEE MTT-S Int’l Microw. Symposium, 2006, p. 129.