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High-precision optical lithography for gate process using an antireflective undercoating and local exposure dose control
Microelectronic Elsevier
Engineering
21 (1993) 47-50 47
HIGH-PRECISIONOPTICALLlTHOGRAPHY FORGATE PROCESS USING AN ANTIREFLECTIVEUNDERCOATINGANDLOCAL EXPOSURE DOSE CONTROL YOSHIAKIMIMURAand
SHINJI AOYAMA
N’IT LSI Laboratories 3-l Morinosato-Wakamiya,
Atsugi-shi.
Kanagawa 243-01, Japan
A high-precision optical lithography for gate fabrication has been developed. The main factors that degrade gate length accuracy are interference effects on the resist film and etching nonuniformity caused by the poly-Si etcher. To reduce the interference effect, we developed a new resist process that makes it possible to employ the developer-soluble antireflective undercoating SWK. Using SWK results in remarkable CD controllability and pattern accuracy. To compensate etching nonuniformity, we developed the Local Exposure dose Control (LEC) method, in which the exposure dose is corrected according to the CD distribution after etching. These two techniques are applied to a 0.5-fi m- gate fabrication process for ASIC Size variation within + 30 nm is obtained after etching LSIs using a g-line stepper. uniformity of on all the wafers. This process leads to a large improvement in the MOSFETthreshold voltages. 1. INTRODUCTION The accuracy to which the threshold voltage of MOSFETscan be controlled is an important factor in fabricating high performance LSIs, and it is directly related to how closely the lengths of their gates can be controlled. The major factor preventing CD controllability in gate fabrication processes is local variation of interference effects in the resist film used in optical lithography [l]. This effect can be reduced conventionally by using a dyed resist, but the benefits are limited. A better technique is to use a developer-soluble antireflective undercoating [2,3]. This reduces the interference effects sufficiently and is a simple procedure However, it is difficult to achieve comparable to a single resist process. reproducible results using this technique. In this paper, we first investigate how this problem can be solved by improving the material properties and process conditions. Another factor which degrades the gate length accuracy is etching nonuniformity within a wafer caused by the gate etcher. To solve this problem, we developed the LEC (Local Exposure dose Control) method. These two techniques were combined in a 0.5-n m gate process for an ASIC LSI to confirm their performance. 2. SWKPROCESS We used SWK (Tokyo Ohka, Standing Wave Killer) [3] as an antireflective undercoating. In Fig.1 and Table 1, the basic performance of the SWKprocess (TSMR: 1.18 ,u m. Tokyo Ohka / SW 0.20 ,u q) made of triazine derivatives with dye is compared with that of conventional (TSMR-V3: 1.18~ m) and a dyed (TSMR-CRH3: 1.18~ m, Tokyo Ohka) resist processes. These results were obtained on bare Si substrates using a g-line stepper (NA: 0.54). The SWKprocess results in a linewidth variation of only 20 nm instead of the 80 nm for conventional processes, and thus gives to better focus
0167-9317/93/$06.00
0 1993 - Elsevier Science Publishers
B.V.
All rights reserved.
Y. Mimura, S. Aoyama
48
Table 1
Basic characteristics
of typical
Max. refl. and min. refl. at near g-line in wavelength (X)+1 12- 4 SWKprocess 41 - 15 Conv. resist 3O- 8 Dyed resist Resist process
resist processes
Focus latitude (D m)*Z 0.5~ m line/space 1.4 1.2 1.2
0.5~ m isolated line 2.4 1.8 2.0
on Si substrates Exposure latitude 0.5~ m line/space 4.2 3.8 3.0
(%)r3’
0.5,~ m isolated line 3.0 2.2 2.4
ll: The reflections is measured after exposure(ZJ/cm=) in g-line. The resist thickness is 1.18~m. 82: FOCUS latitude is defined as the focus range for linewidth deviation within 50 nm. lQ: Exposure latitude is defined as the exposure range for llnewidth deviation wlthin 10 nm.
and exposure
latitudes,
as shown in Table
1.
In general, the substrate on which the gate patterns are laid has a step formed by ACTIVE/LOGOS topography that results in SWK layers of different thicknesses. When the thick SWK layer on the ACTIVE area dissolves away in the developer, the thin layer on the LOCOS area results in an undercut beneath the resist layer. Resist/SWK patterns with excessive undercutting are prone to peel away from the extension of the SWK layer to the edge of a resist pattern substrate. Conversely, degrades the gate length accuracy after etching. It is therefore important to control the dissolution rate to be no extension of SWK layer and to minimize the undercut. Our gate process has a 150-nm ACTIVE/LOGOS step. When we chose the conditions for producing the 50-nm undercut in the LOCOS area shown in Fig. 2, we obtained a zero undercut in the ACTIVE area. For this purpose SWKcomposition was optimized for the dissolution rate of approximately 80 rim/s at moderate baking temperature of around 160 “C.
0.50
,“+CONV.RESIST
0.40$0.46F 0.440.42z + 0.40-l
0.9
1 .o 1.1 1.2 RESIST THICKNESS (pm)
1.3
Fig. 1 Linewidth variation of a O.5- b m line/ space Pattern on bare Si due to variation in the resist thickness.
Fig. 2 Cross-sectional view of a 0.5-p m line/space pattern. of TSMR-V3, 1.18~ m /SWK, 0.2.~ m with a 50-run undercut in the SWKlayer.
Table 2 compares the improved SWKprocess with the conventional and dyed resist ones when these processes are applied to a 0.5- p m gate-array LSI. The maximum difference in the linewidth depends on the shape of the ACTIVE area. Reduction of this difference is extremely important to the improvement of LSI performance. The maximum difference with the SWKprocess was only 16 nm. which is approximately l/4 that of the other processes. Moreover, the SWKprocess resulted in absolutely no pattern notching on the ACTIVE/LOGOS topography as shown in Fig. 3. It is concluded that pattern accuracy can be significantly improved by using the SWK process to reduce reflections from the substrate.
High-precision optical lithography
49
Table2 Linewidth variations in the gateprocessfor fabrication of a 0.5-/rm gate-array LSI. Resist Max. difference process inlinewidth due to shapeof ACTIVEarea(nm) 16 SWKprocess 65 Conv.resist Dyed resist
Max.difference in linewidth formedon ACTIVE andLOCOS (nm) 6 107
59
Deviation in linewidth on g-inchwafer 30 (run) 17 58
Patternnotching generatedon the ACTIVWLOCOS topography
none considerable
48
48
less
3. LOCAL EXPOSURE DOSE CONTROL (LEC) The etcher used in the gate processes causes nonuniformity to the extent that CD loss at the center of the 6” wafer was from 40 to 50 nm larger than at the surrounding area, as shown in Fig. 4(a). In addition, the resist pattern width tends to be smaller at the center of the wafer. The gate length distribution after etching is superimposed by these two CD error distributions as shown in Fig. 4(b). After development and etching, these distributions were highly reproducible because of the single-wafer processing. Therefore, these CD distributions should be corrected beforehand during the resist pattern formation step. The LEC method was developed to allow the local exposure dose to be corrected for each exposure field based on the CD distribution that was measured after etching. A dose variation of +3% results in a linewidth variation of -10 nm, as shown in Table 1. The CD distribution after gate etching was markedly improved when the LEC method was used, as shown in Fig. 4(c). 4.
GATE LENGTIIACCURACYAND THRESHOLD VOLTAGE VARIATIONOF MOSFEl’s
Figure 5 shows how the spread in the linewidths of the resist/SWK patterns varies between lots. The average linewidth was kept within + 10 nm of the target width, and all the values were within + 30 nm of the target. Figure 6 shows typical histograms of the gate length after gate etching with and without the LEC method. LEC reduced substantially the deviation to 0.029 ~1m (3 0 ). Figure 7 shows the relationship between the threshold voltage variation, A Vth (3 u 1, and the gate length variation, A Lg (30 ), of n-MOSFETs with a nominal 0.55-,u m gate length on an ASIC LSI. The approximately linear relationship implies that the accuracy of the gate length is directly related to the deviation of the threshold voltage. These results also show that the combination of the two newly developed techniques, SWK and LEC, can greatly improve threshold voltage control.
(b) Fig. 3 SEMphotographs of 0.5-B m gate resist patterns formed on ACTIVE/LOGOStopography with a 0.15-p m step: (a) SWKprocess, notch free, (bl conventional resist Process, conspicuous notching.
(a)
[CONVEX]
(bl [CONCAVE]
(c)
Fig. 4 Example of CD distributions within a 6-inch wafer. Each contour line represents a 5-nm difference, (al CD loss distribution of poly-Si etcher, and gate length distributions after poly-Si etching (b) without LEC and (cl
withLEC.
50
Y. Mimura, S. Aoyama
01
02 03 04 05
06
07 06
LOT NUMBER
Typicallot-to-lotdeviationof the resist pattern from target linewidthin gate fabricationof a 0.5-.umrule gate-arrayLSI.
Fig.
5
r
0.53
0.55
0.57
0.59
GATE LENGTH Lg (pm)
GATE LENGTH Lg (pm)
WITH LEC
WITHOUT LEC
Fig.6 Typicalhistogrumsof the gate length afterpoly-Sietching (a)with LEC and (b)without LEC.
100
s
E c
>’
t
n-MOSFET Lg= 0.55pm Vth= 0.6V
80 -
60-
; 40WITHOUT LEC
;s:200
*’
’
COMBINED SWK+LEC
20
I 80
Fig.7 Gate length deviation(3~). ALg vs. n-MOSFET thresholdvoltage deviation (3~ ), AVth withina g-inchwafer.
100
30 OF ALg (nm) 5.SuMMARY We have developed two techniques for an accurate gate formation process. One is the use of the developer-soluble antireflective undercoating SWK for reducing interference effects in the resist film.The other is LEC, an exposure dose control method for correcting etching nonuniformity. These techniques were applied to a 0.5-.Um rule ASIC LSI process, and a gate length accuracy of less than f30 nm and a MOSFET threshold voltage variation of less than k30 mV were obtained. This is a SWK for g-line marked improvement over conventional processes. We used lithography, but it can also be used for i-line lithography by changing the dye in the SWK. LEC is also a widely applicable linewidth correction technique for step-and-repeat lithography systems. ACKNOWLEDGEMENTS The authors would like to thank Dr. H. Arai, Dr. K. Harada and Dr. K. Imai for their helpful advice, Mr. T. Takeda for analysis of the CD distribution,Mr. M. Sekimoto, Mr. S. Somatani and Mr. K. Kubota for providing experimental data, and Ms. H. Sumida and Ms. Y. Yamada for their useful assistance. REFERENCES
[l] D. W. Widmann and H. Binder, IEEE Trans., ED-22(7).(1975)467 [2]T. Brewer, R. Carlson and J. Arnold, J. Appl. Photo. Eng., 7(6)(1981)184 [3] W. Ishii,K. Hashimoto, N. Itoh, H. Yamazaki, A. Yokota and H. Nakane, Proc. SPIE, 631 (1986)295
Engineering
21 (1993) 47-50 47
HIGH-PRECISIONOPTICALLlTHOGRAPHY FORGATE PROCESS USING AN ANTIREFLECTIVEUNDERCOATINGANDLOCAL EXPOSURE DOSE CONTROL YOSHIAKIMIMURAand
SHINJI AOYAMA
N’IT LSI Laboratories 3-l Morinosato-Wakamiya,
Atsugi-shi.
Kanagawa 243-01, Japan
A high-precision optical lithography for gate fabrication has been developed. The main factors that degrade gate length accuracy are interference effects on the resist film and etching nonuniformity caused by the poly-Si etcher. To reduce the interference effect, we developed a new resist process that makes it possible to employ the developer-soluble antireflective undercoating SWK. Using SWK results in remarkable CD controllability and pattern accuracy. To compensate etching nonuniformity, we developed the Local Exposure dose Control (LEC) method, in which the exposure dose is corrected according to the CD distribution after etching. These two techniques are applied to a 0.5-fi m- gate fabrication process for ASIC Size variation within + 30 nm is obtained after etching LSIs using a g-line stepper. uniformity of on all the wafers. This process leads to a large improvement in the MOSFETthreshold voltages. 1. INTRODUCTION The accuracy to which the threshold voltage of MOSFETscan be controlled is an important factor in fabricating high performance LSIs, and it is directly related to how closely the lengths of their gates can be controlled. The major factor preventing CD controllability in gate fabrication processes is local variation of interference effects in the resist film used in optical lithography [l]. This effect can be reduced conventionally by using a dyed resist, but the benefits are limited. A better technique is to use a developer-soluble antireflective undercoating [2,3]. This reduces the interference effects sufficiently and is a simple procedure However, it is difficult to achieve comparable to a single resist process. reproducible results using this technique. In this paper, we first investigate how this problem can be solved by improving the material properties and process conditions. Another factor which degrades the gate length accuracy is etching nonuniformity within a wafer caused by the gate etcher. To solve this problem, we developed the LEC (Local Exposure dose Control) method. These two techniques were combined in a 0.5-n m gate process for an ASIC LSI to confirm their performance. 2. SWKPROCESS We used SWK (Tokyo Ohka, Standing Wave Killer) [3] as an antireflective undercoating. In Fig.1 and Table 1, the basic performance of the SWKprocess (TSMR: 1.18 ,u m. Tokyo Ohka / SW 0.20 ,u q) made of triazine derivatives with dye is compared with that of conventional (TSMR-V3: 1.18~ m) and a dyed (TSMR-CRH3: 1.18~ m, Tokyo Ohka) resist processes. These results were obtained on bare Si substrates using a g-line stepper (NA: 0.54). The SWKprocess results in a linewidth variation of only 20 nm instead of the 80 nm for conventional processes, and thus gives to better focus
0167-9317/93/$06.00
0 1993 - Elsevier Science Publishers
B.V.
All rights reserved.
Y. Mimura, S. Aoyama
48
Table 1
Basic characteristics
of typical
Max. refl. and min. refl. at near g-line in wavelength (X)+1 12- 4 SWKprocess 41 - 15 Conv. resist 3O- 8 Dyed resist Resist process
resist processes
Focus latitude (D m)*Z 0.5~ m line/space 1.4 1.2 1.2
0.5~ m isolated line 2.4 1.8 2.0
on Si substrates Exposure latitude 0.5~ m line/space 4.2 3.8 3.0
(%)r3’
0.5,~ m isolated line 3.0 2.2 2.4
ll: The reflections is measured after exposure(ZJ/cm=) in g-line. The resist thickness is 1.18~m. 82: FOCUS latitude is defined as the focus range for linewidth deviation within 50 nm. lQ: Exposure latitude is defined as the exposure range for llnewidth deviation wlthin 10 nm.
and exposure
latitudes,
as shown in Table
1.
In general, the substrate on which the gate patterns are laid has a step formed by ACTIVE/LOGOS topography that results in SWK layers of different thicknesses. When the thick SWK layer on the ACTIVE area dissolves away in the developer, the thin layer on the LOCOS area results in an undercut beneath the resist layer. Resist/SWK patterns with excessive undercutting are prone to peel away from the extension of the SWK layer to the edge of a resist pattern substrate. Conversely, degrades the gate length accuracy after etching. It is therefore important to control the dissolution rate to be no extension of SWK layer and to minimize the undercut. Our gate process has a 150-nm ACTIVE/LOGOS step. When we chose the conditions for producing the 50-nm undercut in the LOCOS area shown in Fig. 2, we obtained a zero undercut in the ACTIVE area. For this purpose SWKcomposition was optimized for the dissolution rate of approximately 80 rim/s at moderate baking temperature of around 160 “C.
0.50
,“+CONV.RESIST
0.40$0.46F 0.440.42z + 0.40-l
0.9
1 .o 1.1 1.2 RESIST THICKNESS (pm)
1.3
Fig. 1 Linewidth variation of a O.5- b m line/ space Pattern on bare Si due to variation in the resist thickness.
Fig. 2 Cross-sectional view of a 0.5-p m line/space pattern. of TSMR-V3, 1.18~ m /SWK, 0.2.~ m with a 50-run undercut in the SWKlayer.
Table 2 compares the improved SWKprocess with the conventional and dyed resist ones when these processes are applied to a 0.5- p m gate-array LSI. The maximum difference in the linewidth depends on the shape of the ACTIVE area. Reduction of this difference is extremely important to the improvement of LSI performance. The maximum difference with the SWKprocess was only 16 nm. which is approximately l/4 that of the other processes. Moreover, the SWKprocess resulted in absolutely no pattern notching on the ACTIVE/LOGOS topography as shown in Fig. 3. It is concluded that pattern accuracy can be significantly improved by using the SWK process to reduce reflections from the substrate.
High-precision optical lithography
49
Table2 Linewidth variations in the gateprocessfor fabrication of a 0.5-/rm gate-array LSI. Resist Max. difference process inlinewidth due to shapeof ACTIVEarea(nm) 16 SWKprocess 65 Conv.resist Dyed resist
Max.difference in linewidth formedon ACTIVE andLOCOS (nm) 6 107
59
Deviation in linewidth on g-inchwafer 30 (run) 17 58
Patternnotching generatedon the ACTIVWLOCOS topography
none considerable
48
48
less
3. LOCAL EXPOSURE DOSE CONTROL (LEC) The etcher used in the gate processes causes nonuniformity to the extent that CD loss at the center of the 6” wafer was from 40 to 50 nm larger than at the surrounding area, as shown in Fig. 4(a). In addition, the resist pattern width tends to be smaller at the center of the wafer. The gate length distribution after etching is superimposed by these two CD error distributions as shown in Fig. 4(b). After development and etching, these distributions were highly reproducible because of the single-wafer processing. Therefore, these CD distributions should be corrected beforehand during the resist pattern formation step. The LEC method was developed to allow the local exposure dose to be corrected for each exposure field based on the CD distribution that was measured after etching. A dose variation of +3% results in a linewidth variation of -10 nm, as shown in Table 1. The CD distribution after gate etching was markedly improved when the LEC method was used, as shown in Fig. 4(c). 4.
GATE LENGTIIACCURACYAND THRESHOLD VOLTAGE VARIATIONOF MOSFEl’s
Figure 5 shows how the spread in the linewidths of the resist/SWK patterns varies between lots. The average linewidth was kept within + 10 nm of the target width, and all the values were within + 30 nm of the target. Figure 6 shows typical histograms of the gate length after gate etching with and without the LEC method. LEC reduced substantially the deviation to 0.029 ~1m (3 0 ). Figure 7 shows the relationship between the threshold voltage variation, A Vth (3 u 1, and the gate length variation, A Lg (30 ), of n-MOSFETs with a nominal 0.55-,u m gate length on an ASIC LSI. The approximately linear relationship implies that the accuracy of the gate length is directly related to the deviation of the threshold voltage. These results also show that the combination of the two newly developed techniques, SWK and LEC, can greatly improve threshold voltage control.
(b) Fig. 3 SEMphotographs of 0.5-B m gate resist patterns formed on ACTIVE/LOGOStopography with a 0.15-p m step: (a) SWKprocess, notch free, (bl conventional resist Process, conspicuous notching.
(a)
[CONVEX]
(bl [CONCAVE]
(c)
Fig. 4 Example of CD distributions within a 6-inch wafer. Each contour line represents a 5-nm difference, (al CD loss distribution of poly-Si etcher, and gate length distributions after poly-Si etching (b) without LEC and (cl
withLEC.
50
Y. Mimura, S. Aoyama
01
02 03 04 05
06
07 06
LOT NUMBER
Typicallot-to-lotdeviationof the resist pattern from target linewidthin gate fabricationof a 0.5-.umrule gate-arrayLSI.
Fig.
5
r
0.53
0.55
0.57
0.59
GATE LENGTH Lg (pm)
GATE LENGTH Lg (pm)
WITH LEC
WITHOUT LEC
Fig.6 Typicalhistogrumsof the gate length afterpoly-Sietching (a)with LEC and (b)without LEC.
100
s
E c
>’
t
n-MOSFET Lg= 0.55pm Vth= 0.6V
80 -
60-
; 40WITHOUT LEC
;s:200
*’
’
COMBINED SWK+LEC
20
I 80
Fig.7 Gate length deviation(3~). ALg vs. n-MOSFET thresholdvoltage deviation (3~ ), AVth withina g-inchwafer.
100
30 OF ALg (nm) 5.SuMMARY We have developed two techniques for an accurate gate formation process. One is the use of the developer-soluble antireflective undercoating SWK for reducing interference effects in the resist film.The other is LEC, an exposure dose control method for correcting etching nonuniformity. These techniques were applied to a 0.5-.Um rule ASIC LSI process, and a gate length accuracy of less than f30 nm and a MOSFET threshold voltage variation of less than k30 mV were obtained. This is a SWK for g-line marked improvement over conventional processes. We used lithography, but it can also be used for i-line lithography by changing the dye in the SWK. LEC is also a widely applicable linewidth correction technique for step-and-repeat lithography systems. ACKNOWLEDGEMENTS The authors would like to thank Dr. H. Arai, Dr. K. Harada and Dr. K. Imai for their helpful advice, Mr. T. Takeda for analysis of the CD distribution,Mr. M. Sekimoto, Mr. S. Somatani and Mr. K. Kubota for providing experimental data, and Ms. H. Sumida and Ms. Y. Yamada for their useful assistance. REFERENCES
[l] D. W. Widmann and H. Binder, IEEE Trans., ED-22(7).(1975)467 [2]T. Brewer, R. Carlson and J. Arnold, J. Appl. Photo. Eng., 7(6)(1981)184 [3] W. Ishii,K. Hashimoto, N. Itoh, H. Yamazaki, A. Yokota and H. Nakane, Proc. SPIE, 631 (1986)295