High short-circuit current density CdTe solar cells using all-electrodeposited semiconductors

Thin Solid Films 556 (2014) 529–534

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High short-circuit current density CdTe solar cells using all-electrodeposited semiconductors O.K. Echendu ⁎, F. Fauzi, A.R. Weerasinghe, I.M. Dharmadasa Electronic Materials and Sensors Group, Materials and Engineering Research Institute, Sheffield Hallam University, Sheffield S1 1WB, United Kingdom

a r t i c l e

i n f o

Article history: Received 10 December 2012 Received in revised form 10 October 2013 Accepted 28 January 2014 Available online 6 February 2014 Keywords: n-CdTe n–n heterojunction p–n junction Solar cell Schottky barrier Electrodeposition

a b s t r a c t CdS/CdTe and ZnS/CdTe n–n heterojunction solar cells have been fabricated using all-electrodeposited semiconductors. The best devices show remarkable high short-circuit current densities of 38.5 mAcm−2 and 47.8 mAcm−2, open-circuit voltages of 630 mV and 646 mV and conversion efficiencies of 8.0% and 12.0% respectively. The major strength of these device structures lies in the combination of n–n heterojunction with a large Schottky barrier at the n-CdTe/metal back contact which provides the required band bending for the separation of photo-generated charge carriers. This is in addition to the use of a high quality n-type CdTe absorber layer with high electron mobility. The potential barrier heights estimated for these devices from the current– voltage characteristics exceed 1.09 eV and 1.13 eV for CdS/CdTe and ZnS/CdTe cells respectively. The diode rectification factors of both devices are in excess of four orders of magnitude with reverse saturation current densities of 1.0 × 10−7 Acm−2 and 4.0 × 10−7 Acm−2 respectively. These all-electrodeposited solar cell device structures are currently being studied and developed as an alternative to the well-known p–n junction structures which utilise chemical bath-deposited CdS. The preliminary material growth, device fabrication and assessment results are presented in this paper. © 2014 Elsevier B.V. All rights reserved.

1. Introduction CdTe has been identified as a viable candidate for efficient photovoltaic application due to its high optical absorption coefficient and suitable direct bandgap [1]. For this application, p-type CdTe is commonly used together with its n-CdS counterpart as the window material. As a result, the conventional CdS/CdTe solar cell is usually a p–n junction device. In fabricating high efficiency n-CdS/p-CdTe solar cells, CdS is usually grown with the chemical bath deposition technique [2], close space sublimation (CSS) technique [3], sputtering [4] or electrodeposition [5], while CdTe is grown using CSS [3] and electrodeposition (ED) [2,5,6]. CdTe can be grown to be n-type or p-type without extrinsic doping, simply by changing the composition [7,8]. However, p-CdTe is required in order to make a CdS/CdTe p–n junction solar cell. It is also possible to convert n-CdTe to p-CdTe by carrying out the all-important CdCl2 treatment and annealing at (400–500) °C for (15–20) min in order to improve cell efficiency [6,9]. The p–n junction CdS/CdTe-based solar cells reached a record efficiency of 16.5% in 2001 [10]. Since this time,

⁎ Corresponding author at:Electronis Materials and Sensors Group, Materrials and Engineering Research Institute, Sheffield Hallam University, Sheffield S1 1WB, United Kingdom.Tel.: +44 114 225 6910; fax: +44 114 225 6930. E-mail address: [email protected] (O.K. Echendu). 0040-6090/$ – see front matter © 2014 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.tsf.2014.01.071

the improvement in the efficiency of CdTe-based thin film solar cells has been stagnant. However, First Solar in United States recently reported a higher efficiency of 18.7% in early 2013 [11]. In order to break this slow progress and stagnation, proper understanding of the physics of these devices and application of different ideas in their fabrication are necessary. Some of these ideas include: use of alternative window materials other than CdS; using buffer layers; implementing different device structures other than the simple p–n junction structure and device processing steps as well as using alternative back contacts. In this paper, we report the application of a combination of n–n heterojunction and Schottky barrier junction in the fabrication of n-CdS/n-CdTe/Au and n-ZnS/n-CdTe/Au solar cells using fluorinedoped tin oxide (FTO) on glass as the substrate. The ED technique is used to deposit the CdS, ZnS and CdTe layers. The use of n-ZnS is also aimed at replacing CdS as a window material. Aqueous solutions and 2-electrode system are used in this work to reduce cost and simplify the deposition system. The use of n-CdTe instead of the regularly used p-CdTe in the fabrication of CdTe-based solar cells is emphasised. Larger Schottky barriers (ϕb) are obtained with n-CdTe than with p-CdTe due to Fermi level pinning at the metal/n-CdTe interfaces [12,13]. These large barrier heights coupled with n–n heterojunction and optimum doping densities are capable of creating a wide depletion region with a strong built-in electric field. When photo-generated electron–hole pairs are created in the depletion region by incident photons, these charge carriers are easily separated by the strong electric field which also imposes high drift velocity on these charge carriers. This effectively results in high photo-current deliverable by these devices as is observed

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in the devices in this paper. Photo-generated current density J, in a solar cell consists of contributions from both photo-generated electrons and holes. The concentrations of these charge carriers are equal in the solar cell. The total photo-current density J, is given by J = q(nμe + pμh)E, where n and p are the concentrations of photo-generated electrons and holes respectively, μe and μh are the electron mobility and hole mobility respectively, q is electronic charge and E is built-in electric field. Since n = p for photo-generated carriers, it follows then that an increase in J comes principally from the contributions of mobility and built-in electric field. In addition to the effects of high mobility and strong built-in electric field on Jsc, it is worthy of note the latest development in the photovoltaic (PV) field. The graded bandgap type solar cells are capable of enhancing Jsc values making use of impurity PV effect, impact ionisation and absorbing infrared radiation from the surrounding [14–16]. When all these or several of these effects combine in one device structure, very high Jsc values are possible in appropriately designed devices. For Schottky barrier solar cell, the current–voltage characteristics are given by Eqs. (1)–(5) [17,18]. Under illumination, the total current density JL of a Schottky barrier solar cell is given by J L ¼ J D þ J R −J SC

ð1Þ

where JD is the current density under dark condition, JR is the recombination current density and JSC is the short-circuit current density. By the thermionic emission theory, JD is given by     qV −1 J D ¼ J 0 exp nkT

ð2Þ

where J0 is the saturation current density, V is the applied bias voltage, n is the diode ideality factor, q is the electronic charge while k and T are Boltzmann constant and absolute temperature respectively. The diode saturation current density ( J0) is given by   −qϕb 2 J 0 ¼ SA  T exp kT

ð3Þ

where S is the active area of the solar cell, A⁎ is the effective Richardson constant which is taken as 12 Acm− 2 K−1 for CdTe and ϕb is the Schottky barrier height of the cell. If recombination is neglected under the thermionic emission theory, then JR is ignored in Eq. (1). Under short-circuit condition, Eqs. (1) and (2) can be combined and then written as     qV −1 −J SC J L ¼ J D −J SC ¼ J 0 exp nkT

ð4Þ

In the open-circuit condition, V = VOC and JL = 0. Then VOC is obtained from Eq. (4) as V OC ¼

  nkT J ln SC þ 1 q J0

ð5Þ

It is important to note that these equations may not be obeyed strictly by experimental results for various reasons such as the presence of surface states as in chemically etched surfaces and tunnelling taking place across these interfaces. 2. Experimental details For ZnS deposition, the electrolyte contained 0.30 M ZnCl2 and 0.03 M (NH4)2S2O3 in 800 ml of de-ionised water in a 1 l beaker. Both chemicals were laboratory reagent grade obtained from Sigma–Aldrich. The pH of the solution was adjusted to 3.00 ± 0.02 using HCl and NH4OH. Prior to the addition of (NH4)2S2O3, electro-purification of ZnCl2 was carried out for 48 h at a potential slightly lower than that

for the reduction of Zn determined from a 2-electrode cyclic voltammogram using high-purity carbon counter electrode and glass/FTO as the cathode. The glass/FTO substrates were cleaned with acetone and methanol and then rinsed with de-ionised water. The source of electrical power for this and all voltammetry and deposition processes was a computerised Gill AC potentiostat. A second voltammogram was also recorded in a similar way after the addition of (NH4)2S2O3 in order to determine the approximate deposition potential range for ZnS. Amorphous ZnS layers were deposited at a cathodic potential of 1.550 V on cleaned glass/FTO substrates for 1 h to a thickness of ~200 nm estimated from Faraday's equation. The deposition temperature was kept at 30.0 ± 0.2 °C to avoid sulphur precipitation. These layers were annealed at 350 °C in air for 10 min. CdS deposition electrolyte also contained 0.30 M CdCl2 and 0.03 M Na2S2O3 in 800 ml of de-ionised water in a 1 l beaker. Both chemicals were also laboratory reagent grade from Sigma–Aldrich. The pH of the solution was adjusted to 1.80 ± 0.02 using HCl and NH4OH. Similar steps as in the case of ZnS were taken for electro-purification and determination of the approximate deposition potential range for CdS using the 2-electrode system with the carbon counter electrode. CdS layers were deposited on cleaned glass/FTO at a cathodic potential of 1.450 V and a temperature of 85.0 ± 0.2 °C. The thickness of the layer deposited for 45 min was ~ 600 nm. The CdS layers were dipped in a saturated aqueous solution of CdCl2, dried in air and then annealed at 400 °C for 20 min. For CdTe, the electrolyte was an 800 ml aqueous solution containing 1 M CdSO4 of 99.0% purity and 1 mM high-purity TeO2 dissolved in 98% concentrated H2SO4 and then diluted with deionised water. Before the addition of TeO2, electro-purification of CdSO4 was carried out for 48 h. 4 ml of the 1 mM TeO2 was then added initially to the solution. After stirring for 24 h, the pH was finally adjusted to 2.00 ± 0.02 using NH4OH and H2SO4. Cyclic voltammogram was recorded again in 2electrode configuration at 85.0 ± 0.2 °C to determine the cathodic deposition potential range of CdTe. Finally, 1 mM each of high-purity CdCl2 and CdF2 was added to the electrolyte for n-type doping of CdTe. CdTe layers were then deposited at a cathodic potential of 2.038 V with respect to a platinum anode, on glass/FTO/CdS and glass/FTO/ ZnS to thicknesses of ~ 1.7 μm and 1.5 μm respectively. About 1 ml of the already-made TeO2 solution was added to the deposition solution after growing each CdTe sample. The reason for adding Te2 + in this manner was to maintain a low Te2 + level in the bath so as to avoid producing Te-rich CdTe layers which do not produce good devices from the authors' experience. The two structures were then dipped in a mixture of CdCl2 and CdF2 in water, dried and annealed in air at 450 °C for 15 min. The CdTe surfaces were etched for 5 s in an aqueous solution containing 1.0 g of K2Cr2O7, 10 ml of H2SO4 and 10 ml of deionised water. The samples were rinsed in deionised water and then etched for 2 min in a 50 ml aqueous solution containing 0.5 g each of NaOH and Na2S2O3. After drying in a stream of nitrogen gas, circular Au metal contacts each of 2 mm diameter and 100 nm thick (with a cross-sectional area of 0.031 cm2) were made on the etched CdTe surfaces by vacuum evaporation at a pressure of 10−4 Pa. Current–voltage (I–V) measurements of the resulting devices were carried out with a computerised Keithley 619 Electrometer/Multi-meter using a solar simulator with a light intensity of 100 mWcm−2. It is worthy of note at this point that the three different electrodeposited layers (ZnS, CdS and CdTe) studied in this work were tested for their electrical conductivity type using the photoelectrochemical cell as described elsewhere [14]. Using this technique, the electrical conductivity type of all three layers deposited on glass/FTO was studied and confirmed as n-type before and after heat treatment and before fabricating the device structures. DC conductivity measurements under dark condition were used to determine the resistivity of the three materials after making ohmic contacts on them using In metal. Some of the properties of the electrodeposited ZnS, CdS and CdTe layers as well as the fabricated solar cells are presented in the next section.

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Fig. 1. Optical absorption spectra of annealed layers of electrodeposited (a) ZnS and (b) CdS.

3. Results and discussion

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Fig. 1 shows the optical absorption spectra of ZnS and CdS layers after annealing. The ZnS layer (Fig. 1(a)) exhibits a very low absorption property compared to CdS (Fig. 1(b)) and has a wide bandgap of 3.70 eV making it suitable for use as a good window or buffer layer as it will allow more high-energy photons to reach the absorber layer in order to create more photo-generated charge carriers. The ZnS layers were amorphous showing no relevant X-ray diffraction peaks. The bandgap of deposited CdS estimated from Fig. 1(b) is 2.42 eV and the layer shows a hexagonal polycrystalline structure with (002) preferred orientation matching the JCPDS reference file Nos. 00-041-1049 and 01-075-154. Fig. 2(a) and (b) shows the optical absorption spectra of CdTe deposited on ZnS and CdS respectively. These figures show relatively higher absorption for the CdTe grown on the CdS layer than that grown on the ZnS layer. This is attributed to the larger thickness of the CdTe layer deposited on CdS. However, the energy bandgaps of CdTe from both figures are similar (~ 1.48 eV), showing that the quality of CdTe deposited on both ZnS and CdS is very similar. The DC resistivity obtained from I–V measurements under dark conditions at room temperature for typical 218 nm ZnS, 570 nm CdS, and 1.64 μm CdTe layers after

annealing, was ~ 3.00 × 104 Ωcm, ~ 1.30 × 105 Ωcm and ~ 3.30 × 105 Ωcm respectively. The energy band diagrams for the two solar cells fabricated are shown in Fig. 3(a) and (b). The regions marked “b” and “a” in Fig. 3(a) and (b) indicate the formation of the intermediate materials of CdSxTe1 − x and ZnCdSxTe1 − x respectively due to inter-diffusion of atoms at CdS/CdTe and ZnS/CdTe interfaces on annealing. This situation leads to the formation of graded junctions instead of abrupt ones at these interfaces making the bandgap of the device to gradually vary from 2.42 eV to 1.48 eV and from 3.70 eV to 1.48 eV for CdS/CdTe and ZnS/CdTe devices respectively. This is known to be crucial for the improvement of solar cell performance. The device structures are in fact a combination of graded n–n junction and a large Schottky diode enhancing the slope of the energy band diagram. With optimum doping density of the materials, a wider depletion region can arise resulting to full depletion of the devices. When light enters the device through the glass as shown, electron–hole pairs are created. The strong electric field in the wide depletion region helps to sweep the electrons towards the FTO front contact and the holes towards the Au back contact as indicated in Fig. 3(a) and (b). These charge carriers can then be collected in the external circuit with little or no recombination.

1.6

0.8

0 1.4

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2

1.2

1.4

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Fig. 2. Optical absorption spectra of annealed CdTe deposited on (a) ZnS and (b) CdS.

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(a)

(b)

e

e e

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h

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FTO

contact

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b = ZnCdSxTe1-X

contact

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Fig. 3. Energy band diagram (not drawn to scale) of (a) glass/FTO/n-CdS/n-CdTe/Au and (b) glass/FTO/n-ZnS/n-CdTe/Au solar cells.

Fig. 4 shows the current density–voltage (J–V) characteristics of glass/FTO/n-CdS/n-CdTe/Au solar cell structure under dark and AM1.5 illumination conditions. The shapes of the curves (Fig. 4(a) and (b)) show that the device has high series resistance (Rs) and this was calculated from Fig. 4(a) as 2054 Ω and from Fig. 4(b) as 316 Ω. This is attributed mainly to the diffusion of Na from the underlying soda lime glass into the large thickness of CdS (~600 nm) as well as possible formation of thick oxide layer at the n-CdTe/metal interface due to chemical etching of the CdTe surface which may have resulted in an unintended MIS structure. Na diffusion into the CdS layer from the underlying soda lime glass substrate is known to make the CdS layer resistive by self-compensation and this increases series resistance and reduces fill factor [19]. Na is known as an acceptor impurity in CdS and CdTe [20] and can be detrimental in n-type materials used in this work. For this reason also, we are currently trying to effectively replace the Na2S2O3 used as a sulphur precursor in the deposition of CdS with an alternative Na-free precursor. The rectification factor (IF/IR)V = 1 for this device exceeds 4 orders of magnitude with a value of 104.1 but the ideality factor is high (n = 2.54). The use of Eq. (3) to estimate the barrier height yields 1.09 eV indicating the presence of an actual potential barrier height greater than 1.09 eV within the device. It should be noted that the use of high n-values, such as the one above, to calculate barrier heights actually under-estimates the barrier heights obtained. The saturation current density (J0) measured from the log-linear I–V curve (not shown here) was 1.0 × 10− 7 Acm− 2. This value is quite high as is typical of diode structures with lots of recombination centres.

6

The n–n heterojunction present in this device does not provide a significant potential barrier for this device. But it supports the large barrier height providing good rectification property arising from the Schottky barrier at the n-CdTe/Au interface, and this produces the required band-bending and internal electric field to effectively separate photogenerated electron–hole pairs [15]. The open-circuit voltage (Voc), short-circuit current density (Jsc), fill-factor (FF) and conversion efficiency (η) produced by this device under illumination were 630 mV, 38.5 mAcm−2, 0.33 and 8.0% respectively. Fig. 5(a) and (b) also shows the J–V characteristics of the glass/FTO/ n-ZnS/n-CdTe/Au device under dark and AM1.5 illumination conditions respectively. The value of Rs obtained from Fig. 5(a) was 126 Ω while that from Fig. 5(b) was 112 Ω. This is attributed to relatively reduced Na diffusion into the smaller thickness of ZnS (~ 200 nm) and/or due to the formation of a relatively thin oxide layer at the n-CdTe/metal interface due to chemical etching of the CdTe surface. The rectification factor (IF/IR)V = 1, n, J0 and ϕb measured for this device were 104.7, 2.36, 4.0 × 10−7 Acm−2 and 1.13 eV respectively. Again the value of n is high and the barrier height has been under estimated. Observation of high n-values in these devices can be due to several reasons. One of the reasons is the issue of high series resistance. Bayhan and Kavasoglu [21] also obtained a good agreement between the experimentally determined and model calculated diode factors in the range (3.43–4.07) for 13% n-CdS/p-Cu(In,Ga)Se2 solar cell by assuming the presence of high series resistance. The second possible reason may be due to the high density of surface states for the chemically etched CdTe absorber layer

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Fig. 4. Room temperature I–V characteristics of glass/FTO/n-CdS/n-CdTe/Au device (a) under dark condition and (b) under AM1.5 illumination condition.

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Fig. 5. Room temperature I–V characteristics of the glass/FTO/n-ZnS/n-CdTe/Au device under (a) dark and (b) AM1.5 illumination conditions.

and hence enhanced tunnelling through the diode. Another reason is the presence of recombination centres in the materials used in the device. The solar cell parameters obtained under illumination for this cell were Voc = 646 mV, Jsc = 47.8 mAcm− 2, FF = 0.39 and η = 12.0%. This device shows a remarkable higher short-circuit current density compared to the device with the CdS window layer. Part of the reasons for this lies in the optoelectronic properties of the ZnS layer. The wider bandgap of ~3.70 eV and the very low optical absorption of ZnS relative to CdS (see Fig. 1(a) and (b)), make it possible for high-energy photons, especially in the energy range between the bandgaps of ZnS and CdS to reach the CdTe absorber material in order to create more photogenerated charge carriers to enhance JSC. With CdS of considerable thickness, this range of photons is usually lost in CdS as a result of its relatively high absorption and low photo-activity [22]. This is part of the expectations in using ZnS as a window material in this device for possible replacement of CdS as the window layer. Another reason for high JSC values in general, is the use of electrodeposited n-CdTe with superior quality as mentioned earlier. Lyons et al. [23] remarked from their work on CdTe, that cathodically electrodeposited CdTe has superior qualities compared to some high-purity single crystal CdTe obtained from different sources, based on the presence of impurities detected using secondary ion mass spectroscopy analysis under similar conditions. This property serves to improve the carrier mobility in this material. This, combined with our processing steps, helps to obtain devices with improved mobility of photo-generated charge carriers resulting in high current densities for devices with these materials. The device with the ZnS window material also produced slightly higher Voc as a result of its larger barrier height compared to the device with the CdS window layer. This device also produced higher FF than its CdS counterpart due to its reduced series resistance. To ensure that these current densities are genuine, these devices were isolated by removing the CdTe material around the back metal contact in order to eliminate any possible collection of current from the periphery of the diode. The solar cell area in each case was 0.031 cm2 as mentioned earlier. However, a major issue with both devices at present is that of very low fill factor values in addition to the issue of reproducibility and consistency of the device parameters. This is a real concern as the high JSC values are not observed in every batch of devices processed. Both devices also show high diode ideality factor n N 2.00 contrary to an expectation of values in the range 1.00 b n b 2.00. All these issues are currently being studied and addressed in the authors' group in order to further develop these promising solar cell device structures.

It is possible in these devices for photons with energy lower than the bandgap energy of CdTe to create useful electron–hole pairs through the impurity photovoltaic effect and for impact ionisation to take place as well resulting in one photon creating two electron–hole pairs in order to enhance Jsc [24,25]. This is possible because of the shape of the energy band diagrams of the device structures used in these solar cells. Although the authors have not carried out measurements such as quantum efficiency (QE) and responsivity on these devices to confirm the existence of impurity photovoltaic effect and impact ionisation, previous work published by the authors' group based on AlGaAs/GaAs graded bandgap solar cells has shown experimental evidence of impurity photovoltaic effect using responsivity measurement. The full account of this work is contained in a recent paper titled “Solar cells active in complete darkness” (see ref [16,14]) in which evidence of photocurrent generation by photons with energy lower than the bandgap energy of GaAs was experimentally observed. This current collection in the longer wavelength region of the solar spectrum as well as from the infrared radiation in the surroundings could not be detected by conventional QE measurement indicating also a technical deficiency of QE measurement in this regard. Again recent unpublished work by the authors' group on the AlGaAs/GaAs graded bandgap solar cells has shown an internal photon to current conversion efficiency (IPCE) of up to 140% giving evidence of impact ionisation in these devices. The major reasons these measurements were not carried out on the devices reported in this manuscript are the instability and reproducibility issues mentioned earlier. This is because at present these devices degrade easily within weeks and even days of their fabrication and reproduction of the devices with the high Jsc values is not easy at present. For these reasons the authors have not been able to arrange for these measurements to be made in laboratories where the equipment are available since these equipment are not in the authors' group. The authors are eager to carry out “Responsivity” measurements as soon as the stability of these devices has been established. The authors report the current situation, but “Responsivity” measurement has to wait until the stability issue is sorted out. This could take some time due to the complexity of this subject. The existence of several native defect/impurity levels in the bandgap of CdTe that causes a strong Fermi level pinning effect at the CdTe/metal interface in CdTe [13,24] is taken to advantage in the solar cells reported in this manuscript. As shown in Fig. 3(a) and (b) electrons can be promoted to these defect levels (only two levels are shown in Fig. 3 for illustration) by photons with energy lower than the bandgap energy of CdTe. These photons can come from the incident radiation from the sun or from the heat energy in the surroundings of the solar cell.

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Because of the position of the depletion region and the shape of the band diagram of these devices, the holes associated with the electrons promoted to the defect levels, are immediately drifted towards the metal back contact leaving these electrons little or no room for recombining or relaxing back with the holes. From these defect/impurity levels, these electrons can easily be promoted to the conduction band by other photons giving rise to the impurity photovoltaic effect. Alternatively, electrons accelerating from the high Schottky barrier (фb ~ 1.20 eV) existing in the devices (which is comparable with potential barrier in a p–n junction) can knock out these “suspended” electrons from the impurity levels into the conduction band of CdTe in a form of impact ionisation. In this way the combination of these two processes can result in one photon effectively creating two electron–hole pairs bringing about the improvement of the photocurrent (Jsc) of the solar cell. This impurity photovoltaic effect may not be as easy in a p–n junction type CdS/CdTe or ZnS/CdTe solar cell due principally to the position of the depletion region. In the p–n junction type device, electrons can as well be promoted to impurity levels near the p-CdTe/metal interface but because of the position of the depletion region and the “flat” band condition near the p-CdTe/metal ohmic contact, there will be no available electric field near this interface to immediately drift the holes towards the metal back contact due to the presence of the bulk region of CdTe materials between the depletion region and the metal back contact. The result is that these photo-generated electron–hole pairs are still within each other's reach for easy recombination. In addition, the fact that charge carriers generally have higher mobility in n-CdTe than in p-CdTe facilitates the easy transport of these photo-generated electrons and holes towards the respective electrical contacts [26]. The overall shape of the device structure therefore, plays an important role in ensuring effective collection of photo-generated electrons and holes resulting in improved Jsc such as are seen in the devices reported in this paper. 4. Conclusion Thin film n-CdS/n-CdTe and n-ZnS/n-CdTe solar cells with Au Schottky back contacts were fabricated using all-electrodeposited semiconductors. The ED of all three semiconductors was carried out from aqueous solutions using the 2-electrode system for process simplification and elimination of a possible impurity source (the reference electrode). Both devices displayed impressive high current densities which are attributed to the quality of the electroplated semiconductors, the use of n-CdTe and the overall device architecture. The results show that ZnS can replace CdS as the window material in CdTe-based solar cells. These devices also displayed high values of diode ideality factor (n N 2.00), low fill factor values and high J0 values due possibly to high series resistance and recombination centres resulting from Na diffusion from the underlying soda lime glass substrates and un-optimised material layer thicknesses and device processing steps. The major challenge in these devices at present is that of improving the fill factor values which are generally low as well as reducing the reverse saturation current and hence further improving the open-circuit voltage. In addition, the reproducibility, consistency and stability of these devices still remain issues needing serious attention. Our future work is focused on

incorporating appropriate buffer layers between the FTO and the window layers to minimise Na diffusion into the window layers (from the underlying glass substrate) and shunting effect. We also intend to use the Na-free precursor for the deposition of CdS, incorporate an appropriate insulating/oxide layer between the n-CdTe and Au contact for pinhole plugging and improvement of the barrier heights and finally to increase the device area, which at present is very small. These approaches we believe, will help to increase the fill factor and opencircuit voltage, maintain high short-circuit current density and ultimately increase the overall conversion efficiency.

Acknowledgments The authors thank the Pilkington group, UK for providing glass/FTO substrates for this work. The principal author thanks the Federal University of Technology, Owerri, Nigeria and the Tertiary Education Trust Fund, Nigeriafor financial support. Hussein Salim is also thanked for his contribution.

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