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High slew rate CMOS operational amplifier employing internal transistor compensation
0026-269218311405-0005 $5.00/0
High slew rate CMOS operational amplifier employing internal transistor compensation by Bingxin Wu* and John Mayor** *Semiconductor Research Institute, Ministry of Post and Telecommunications, Peking, China (Visiting Research Fellow at Edinburgh UniversiW) **Integrated Systems Group, Department of Electrical Engineering, University of Edinburgh, King's Buildings, Edinburgh EH9 3JL
A compact, high slew rate, low distortion CMOS operational amplifier employing an internal feedback transistor instead of the more usual compensation capacitor is reported, which is fabricated using an n-well CMOS silicon-gate technology. The operational amplifier has an open-loop gain exceeding 60dB, a slew rate of + 3 6 / - 5 0 V per microsecond, a one-per-cent settling time of 0.25 microsecond, a total harmonic distortion of - 7 3 dB and a power dissipation of 11.5 mW. The design principles are summarised with particular emphasis on the novel transistor feedback compensation circuit. Results for a switched-capacitor filter employing such an operational amplifier are summarised.
1.
Introduction
Use of an internal compensation capacitor to stabilise an operational amplifier has long been an established method in operational amplifier design. Because of the delay introduced by the compensation capacitor, most of the reported operational amplifiers have transient responses in the range 1-10 V//.ts 14. Such modest slew rate values have generally restricted their application to low frequencies. Higher speed operational amplifiers require improved gain structures to be designed, usually resulting in increased power dissipation and silicon area. Employing larger area structures results in lower yield, particularly for high-order filters employing many amplifiers, and less compact circuitry. Furthermore, enlarging the active area increases circuit parasitic capacitances which results in increased delay times. Therefore, this solution is not an attractive approach. Alternatively, transistors having small geometries may be employedS; however, small geometry devices usually exhibit higher noise and distortion which contradicts the requirement of analogue integrated circuits6. In a conventional operational amplifier design, the slew rate is mainly determined by two factors: firstly, the average delay, TD, of each stage, including the large delay associated with the compensation capacitor. The second factor is the charging time or discharging time, TR, of the capacitive load. The slew rate, S, is given approximately by S-
V TD+TR
. ....................................................
(1)
where V is the output step voltage. The charging time is given approximately by TR--
VCL Io
. ....................................................
(2)
High slew rate CMOS operational amplifier employing internal transistor compensation conL from page 5
where CL is load capacitance, and Io is the average current through the output stage. It can be seen from equation 2 that if the output stage can offer enough current to charge or discharge the load capacitance, then the charging or discharging time will reduce and solely depend on To. Usually, the delay in each stage is negligible as compared with the delay associated with the compensation capacitor. Thus, an operational amplifier without a compensation capacitor should result in a high speed circuit. A major issue is how to guarantee that the operational amplifier will operate in a stable condition without a compensation capacitor. This paper reports a new technique to increase the speed of a MOS operational amplifier and improve its phase shift whilst preserving stability. The technique adopted employs a feedback transistor to replace the more usual compensation capacitor to improve the frequency response. Results are presented for an integrated operational amplifier implemented using a 6/.tin, n-well CMOS silicon-gate technology. 2.
Operational
amplifier circuit principles
In this section the circuit principles adopted and details of the internal feedback transistor compensation are discussed.
M3. 14
VDD
(7)
]
-
(101
_
VSS
Fig. 1 Differentialinputstagewitha levelshifteras load. *p-channeldevices. N.B. Numbersin bracketsare nodesreferredto in the text.
2.1 Frequencycompensation analysis Consider the analysis for a usual, capacitor compensated amplifier (without a feedback transistor). In a normal CMOS operational amplifier design typically employing two stages, the dominant pole is usually determined by the design of the differential input stage. A conventional differential stage with a level shifter as its load is shown in Fig. 1. The gain, ADt, of this stage is derived to be approximately: Apt--
gm
. ...................................................... (3) g9 where g ~ is the transconductance of transistor Mz, and g9 is the output conductance of the differential stage (node 9). It has one pole at set =
---
g9 C9
. ......................................................
(4)
where C9 is load capacitance of the differential stage. As the NMOS transistor M2 is supplied by an imperfect current source as its load, g9 is modest in value. A differential input stage with a feedback transistor and level-shifter is shown in Fig. 2. The frequency response of the differential input stage with feedback transistor Ms is derived to be approximately gsu + sC~o
A D ~.~
.................................
(5)
+ g~---L ~ + s (c~ -c9,,o~
g9
l+h6
\"
1+X6,]
where gMs is transconductance of Ms; h 6
gMB6 --
; and gMB6is the ID to VBS transconductance
gM6
of M6; and C9, to is the capacitance between nodes 9 and 10. The low frequency gain is now reduced to be g~u AD 2 -g9 +
................................................
(6)
gMs 1+~
VDD
(8) I
I (10)
,J
'1'
It,
1
VSS
Fig. 2 Differential stage with feedback transistor and level shifter as load. *p-channel devices.
with a corresponding pole at gMs
Sp2 =
g9 + - l+h6
...............................................
(7)
C9.10 C 9 - ~ l+h6
Comparison of equations 4 and 7, yields the following interesting results: 1.
In the case without the feedback transistor, the load capacitance of the differential stage, C9, is given by C9 = CGD2 + CGD4+ CGS6"t'-CGD6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(8)
High slew rate CMOS operational amplifier employing internal transistor compensation
conL from page 7
where CGD and CGS are the gate-drain and gate source capacitances of the devices, subscripts 2, 4 and 6 correspond to transistor M2, M4 and M6, respectively. Usually CGs is several times greater than CGD. 2.
In the feedback transistor case, the load capacitance of the differential stage, C;, is reduced to C9,10 C 9 = C9
1+~,6
~ C9 - C9,10 = CGD2 -F CGD4 "It-CGD6
............
(9)
Note that Cc,s~ disappears in equation 9. Thus the pole frequency may be increased in value by a factor greater than the reduced level of the gain, by appropriate choice of the geometry of devices of the differential stage and the level shifter. The results obtained here are different from a resistive feedback loop. The reason for this is that MOS devices have non-linear characteristics modelled by a complex equivalent circuit. Therefore, the feedback function of the transistor is dependent on frequency. The expected frequency response results for the different feedback techniques are illustrated in Fig. 3. The curve (1) in Fig. 3 is the case without feedback; the curve (2) is the case of resistive feedback. The resistive feedback reduces the gain at low frequency but has the same gain-bandwidth, GB 1, as that in the case without feedback. Curve (3) is the case of MOS transistor feedback and here the gain is reduced to the value for resistive feedback; however, the gain-bandwidth is increased to GB2. It is clear that in the case of transistor feedback, an even higher gain-bandwidth can be obtained by reducing the gain of the amplifier.
,%
Ad
I
',
!\,2,
;
I\
I
I
fPO fP1
fP2
\ 6B1
fiB2
frequency Fig. 3
Predicted frequency response of different feedback techniques. Curve (1): No feedback. Curve (2): Resistive feedback. Curve (3): MOS transistor feedback.
2.2 Circuit description A complete operational amplifier circuit consisting of only 13 transistors employing the transistor feedback principle developed in section 2.1 is shown in Hg. 4. Two stages are adequate to obtain more than 60dB gain. Mt, M2, M3 and M4 is a conventional differential input stage, with M5 serving as the current s o u r c e . M9 and M~0 acts as a gain stage/output stage, biased as a class AB amplifier in order to obtain a high output swing with low distortion. Class AB is chosen in preference to class A operation as experiment and theory show that class AB CMOS amplifiers have a much lower distortion than class A, CMOS amplifiers 7. M6 and M7 consists of a level-shifter and Ms, using M4 as its load device, realises the negative feedback compensation. The function of M8 is to move up the low frequency pole, improving the phase shift of the operational amplifier, as described in section 2.1. The
j
M1k
v lifo
-I,
(12) [
(lq)
M1i I _
M5
Fig. 4
Vss
_
CMOS operationalamplifier circuit. *p-channel devices.
2000
~(Pk-to-Pk)/~
II
f phose/ angle
1500
1000
500
lOmV
0lm'~ 103
I
I
104
105
0o 106
107
frequency (Hz) Fig. 5
Simulated frequency response of the amplifier. Input signal I mV rms. Curve (1): Compensated with MOS transistor. Curve (2): Compensated with capacitor.
P
High slew rate CMOS operational amplifier employing internal transistor compensation cont. from page 9
transistor combination, M]t, MI2 and Ml3 forms a bias string to supply a bias to the gate of current source transistor Ms and load transistor M7 of the level-shifter. Most of the MOS devices in this operational amplifier are n-channel which have low body effect and high gain, resulting in an improvement in the performance. For example, the body effect plays a major role in determining the distortion of the amplifier s. The substrate was chosen to be high resistivity to minimise the parasitic capacitances. As is usual practice in CMOS operational amplifier design, the n-well is connected to the positive power supply and the substrate is connected to negative power supply, therefore only two power supplies are needed. The circuit is designed for power supply rails of +-5 volts. The frequency response and phase characteristic simulated by the SPICE simulation program for internal transistor compensation is shown in Fig. 5. The pole frequency has moved up to 8kHz with transistor feedback, from about 2kHz when a compensation capacitor is used and the unity-gain bandwidth is increased to 8MHz from about 2MHz, respectively. The phase margin is predicted to be 50 degrees with transistor compensation. 3.
CMOS processing
The process used is n-well, CMOS, polysilicon-gate technology which combines the low power of CMOS with the high speed of NMOS devices. The process employs five implantation steps; for n-well formation, field threshold-voltage control in the p-substrate, threshold-voltage adjustment of both NMOS and PMOS devices, and the source/drain formation of NMOS and PMOS devices. The silicon wafers were p-type, (100) orientation, having a resistivity of 18flcm. Phosphorus ions were implanted into the substrate at 100keV with doses about 1.5 x 1012cm-2 to form an n-well region. A phosphorus drive-in was undertaken at 1150~ for about 19 hours in an N2 atmosphere, resulting in a well depth of about 5 F m in order to reduce the gain of parasitic PNP transistor and the latch-up effect. Boron ions were implanted into the field regions outside the n-well at 25 keV with doses of 7 x 10t3cm -2 to control the field threshold-voltage in the P-substrate. The threshold-voltage of the complementary-channel devices was adjusted to be 1V for NMOS, and - 1 V for PMOS by boron implantation to NMOS and PMOS regions at 40keV with doses of 6 x 10item -2, simultaneously. The source/drain junctions of the NMOS devices were formed by phosphorus implantation at 90KeV with doses of 7 • 10t~cm-2; the source/drain junctions of the PMOS devices were formed by boron implantation at 35KeV with doses of 2 x 10tScm-2. The junction depths of both the NMOS and PMOS sources/drains were controlled to 1/zm by the subsequent processing.
+VIN -VIN
VSS
II
I VOUT
VDD Fig. 6 Chipphotograph of operationalamplifier. 10
Table I
Note 1: Note 2: Note3: Note 4:
Performance of the CMOS operational amplifier
active area
0.056 mm 2
low frequency gain
60-67dB
power dissipation
11.5 mW
unity-gain bandwidth
8-12MHz
input offset voltage
7.6 - 10roW
slew rate (note 2)
positive 36V - 50V/gs negative 40V - 50V/p.s
settling time to one per cent (note 2)
0.25p.s
common-mode rejection ratio
82-88 dB
power supply rejection
58dB
distortion (note 3)
-73 dB
noise (note 4)
300 - 400 nV/x,,tJT
For above, VDD = "[-5V, VSS = -5V. load capacitance 32 pF; step voltage = 4V. fundamental, 20 kHz; output voltage 5 V peak-to-peak. measured at 1kttz.
4. Experimental results E x p e r i m e n t a l o p e r a t i o n a l a m p l i f i e r s w e r e i n t e g r a t e d as p a r t o f a m o n o l i t h i c fifth-order, elliptic filter r e a l i s e d in a s w i t c h e d - c a p a c i t o r configuration. A chip p h o t o g r a p h o f a typical o p e r a t i o n a l a m p l i f i e r t o p o l o g y is s h o w n in Fig. 6. T h e m e a s u r e d p e r f o r m a n c e o f the o p e r a t i o n a l a m p l i f i e r is s u m m a r i s e d in T a b l e I, e x h i b i t i n g high slew rate a n d low d i s t o r t i o n . F i g u r e 7 d e m o n s t r a t e s t h e slew r a t e p e r f o r m a n c e o f a typical o p e r a t i o n a l a m p l i f i e r w h e n
r~.7 Step response of operational amplifierconnected as voltage follower. Upper trace - input signal. Lower trace - output response. Horizontal scale: 0. l/~s/div. Vertical scale: 1 V/div. 11
High slew rate CMOS operational amplifier employing intemal transistor compensation conL from page 11
Fig. 8 Distortion of CMOS operational amplifierconnectedas voltage follower. Output signal5 V peak-to-peak. Fundamental 20 kHz. c o n n e c t e d as a unity-gain buffer with a load capacitance of 32pF, in response to an input step of 4 volts at a 1MHz rate. The measured slew rate is 36-50 V/~s, and the settling time to one per cent is estimated to be about 0.25/xs. Figure 8 shows the distortion of the amplifier at 2 0 k H z with an output voltage of 5 volts peak-to-peak for a ---5 volts power supply. The second harmonic coefficient is eliminated by the push-pull output stage, and the third harmonic coefficient was measured to be - 7 3 dB. T h e frequency response of a prototype, monolithic, fifth-order, elliptic, lowpass switchedcapacitor filter using this operaticnal amplifier is shown in Fig. 9. T h e experimental frequency response gave acceptance agreement with the simulated variation, validating the
Fig. 9 Frequencyresponse of experimentallmonolithic5th-order, elliptic, lowpass CMOS filter.
performance obtained from the amplifiers. However, the pronounced peak in the passband near the cut-off frequency of 0.88dB is explained due to over-compensation of the finite gain and bandwidth of the operational amplifier. 5.
Conclusions
The results of this work have shown that an operational amplifier employing internal feedback transistor compensation may achieve high speed and low distortion, when realised with n-well CMOS polysilicon technology. The features of this technique are as follows: (i) Reduced silicon area. The operational amplifier presented here has an active area of only 0.056mm 2 by eliminating the compensation capacitor. The amplifier should therefore be a high yielding structure. (i) High slew rate. Up to 50V//.ts with a load capacitance of 32pF. (iii) Non-linear distortion caused by any non-linearity of the usual compensation capacitor is reduced. The internal feedback transistor improves the distortion of the operational amplifier because of internal negative feedback. The total distortion is down to - 7 3 d B with an output voltage up to 5V peak-to-peak. The effect of the feedback transistor on the distortion of the operational amplifier will be described elsewhere 7. This high performance operational amplifier is suitable for many video frequency applications including switched-capacitor filters and analogue/digital interface circuitry. As no compensation capacitor is required it may be integrated in a single layer, polysilicon process which does not support well-defined capacitor formation. 6. Acknowledgments
The wafers were fabricated in the SERC-supported, Edinburgh Microfabrication Facility. The authors wish to thank Mr Tong Qinyi for the innovative CMOS processing and Dr J Pennock for comments on the draft paper. The support of the Ministry of Education of the People's Republic of China is also acknowledged. 7.
References
[I] Tsividis, Y. P., and Gray, P..R., "An integrated NMOS operational amplifier with internal compensation", IEEEJSSC, SC-II, 748-753 (1976). [2] Allstot, et al., "MOS switched capacitor filters", IEEEJSSC, SC-13, 6,806-821 (1978). [3] Senderowicz, D., et aL, "High-performance NMOS operational amplifier", IEEEJSSC, SC-13, 6, 760-766 (1978). [4] Gregorian, R., and Nicholson, W. E., "CMOS switched-capacitor filters for a PCM Voice CODEC", IEEEJSSC, SC-14, 6,970-980 (1979). [5] Ishihara, T., et al., "A high speed NMOS operational amplifier fabricated using VLSI technology", Electronics Letters, 18, 4, 159-161 (1982). [6] Gray, P. R., "Basic MOS op amp design-an overview", in "Analog MOS integrated circuits", ed. P. R. Gray, D. A. Hodges and R. W. Brodersen, IEEE Press, New York (March 1980). [7] Wu, B. X., and Mayor, J., "Distortion in CMOS op amp" (paper in preparation). I'8] Tsividis, Y. P., "Harmonic distortion in single-channel MOS integrated circuits", IEEE JSSC, SC-16,694-702 (1981).
High slew rate CMOS operational amplifier employing internal transistor compensation by Bingxin Wu* and John Mayor** *Semiconductor Research Institute, Ministry of Post and Telecommunications, Peking, China (Visiting Research Fellow at Edinburgh UniversiW) **Integrated Systems Group, Department of Electrical Engineering, University of Edinburgh, King's Buildings, Edinburgh EH9 3JL
A compact, high slew rate, low distortion CMOS operational amplifier employing an internal feedback transistor instead of the more usual compensation capacitor is reported, which is fabricated using an n-well CMOS silicon-gate technology. The operational amplifier has an open-loop gain exceeding 60dB, a slew rate of + 3 6 / - 5 0 V per microsecond, a one-per-cent settling time of 0.25 microsecond, a total harmonic distortion of - 7 3 dB and a power dissipation of 11.5 mW. The design principles are summarised with particular emphasis on the novel transistor feedback compensation circuit. Results for a switched-capacitor filter employing such an operational amplifier are summarised.
1.
Introduction
Use of an internal compensation capacitor to stabilise an operational amplifier has long been an established method in operational amplifier design. Because of the delay introduced by the compensation capacitor, most of the reported operational amplifiers have transient responses in the range 1-10 V//.ts 14. Such modest slew rate values have generally restricted their application to low frequencies. Higher speed operational amplifiers require improved gain structures to be designed, usually resulting in increased power dissipation and silicon area. Employing larger area structures results in lower yield, particularly for high-order filters employing many amplifiers, and less compact circuitry. Furthermore, enlarging the active area increases circuit parasitic capacitances which results in increased delay times. Therefore, this solution is not an attractive approach. Alternatively, transistors having small geometries may be employedS; however, small geometry devices usually exhibit higher noise and distortion which contradicts the requirement of analogue integrated circuits6. In a conventional operational amplifier design, the slew rate is mainly determined by two factors: firstly, the average delay, TD, of each stage, including the large delay associated with the compensation capacitor. The second factor is the charging time or discharging time, TR, of the capacitive load. The slew rate, S, is given approximately by S-
V TD+TR
. ....................................................
(1)
where V is the output step voltage. The charging time is given approximately by TR--
VCL Io
. ....................................................
(2)
High slew rate CMOS operational amplifier employing internal transistor compensation conL from page 5
where CL is load capacitance, and Io is the average current through the output stage. It can be seen from equation 2 that if the output stage can offer enough current to charge or discharge the load capacitance, then the charging or discharging time will reduce and solely depend on To. Usually, the delay in each stage is negligible as compared with the delay associated with the compensation capacitor. Thus, an operational amplifier without a compensation capacitor should result in a high speed circuit. A major issue is how to guarantee that the operational amplifier will operate in a stable condition without a compensation capacitor. This paper reports a new technique to increase the speed of a MOS operational amplifier and improve its phase shift whilst preserving stability. The technique adopted employs a feedback transistor to replace the more usual compensation capacitor to improve the frequency response. Results are presented for an integrated operational amplifier implemented using a 6/.tin, n-well CMOS silicon-gate technology. 2.
Operational
amplifier circuit principles
In this section the circuit principles adopted and details of the internal feedback transistor compensation are discussed.
M3. 14
VDD
(7)
]
-
(101
_
VSS
Fig. 1 Differentialinputstagewitha levelshifteras load. *p-channeldevices. N.B. Numbersin bracketsare nodesreferredto in the text.
2.1 Frequencycompensation analysis Consider the analysis for a usual, capacitor compensated amplifier (without a feedback transistor). In a normal CMOS operational amplifier design typically employing two stages, the dominant pole is usually determined by the design of the differential input stage. A conventional differential stage with a level shifter as its load is shown in Fig. 1. The gain, ADt, of this stage is derived to be approximately: Apt--
gm
. ...................................................... (3) g9 where g ~ is the transconductance of transistor Mz, and g9 is the output conductance of the differential stage (node 9). It has one pole at set =
---
g9 C9
. ......................................................
(4)
where C9 is load capacitance of the differential stage. As the NMOS transistor M2 is supplied by an imperfect current source as its load, g9 is modest in value. A differential input stage with a feedback transistor and level-shifter is shown in Fig. 2. The frequency response of the differential input stage with feedback transistor Ms is derived to be approximately gsu + sC~o
A D ~.~
.................................
(5)
+ g~---L ~ + s (c~ -c9,,o~
g9
l+h6
\"
1+X6,]
where gMs is transconductance of Ms; h 6
gMB6 --
; and gMB6is the ID to VBS transconductance
gM6
of M6; and C9, to is the capacitance between nodes 9 and 10. The low frequency gain is now reduced to be g~u AD 2 -g9 +
................................................
(6)
gMs 1+~
VDD
(8) I
I (10)
,J
'1'
It,
1
VSS
Fig. 2 Differential stage with feedback transistor and level shifter as load. *p-channel devices.
with a corresponding pole at gMs
Sp2 =
g9 + - l+h6
...............................................
(7)
C9.10 C 9 - ~ l+h6
Comparison of equations 4 and 7, yields the following interesting results: 1.
In the case without the feedback transistor, the load capacitance of the differential stage, C9, is given by C9 = CGD2 + CGD4+ CGS6"t'-CGD6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(8)
High slew rate CMOS operational amplifier employing internal transistor compensation
conL from page 7
where CGD and CGS are the gate-drain and gate source capacitances of the devices, subscripts 2, 4 and 6 correspond to transistor M2, M4 and M6, respectively. Usually CGs is several times greater than CGD. 2.
In the feedback transistor case, the load capacitance of the differential stage, C;, is reduced to C9,10 C 9 = C9
1+~,6
~ C9 - C9,10 = CGD2 -F CGD4 "It-CGD6
............
(9)
Note that Cc,s~ disappears in equation 9. Thus the pole frequency may be increased in value by a factor greater than the reduced level of the gain, by appropriate choice of the geometry of devices of the differential stage and the level shifter. The results obtained here are different from a resistive feedback loop. The reason for this is that MOS devices have non-linear characteristics modelled by a complex equivalent circuit. Therefore, the feedback function of the transistor is dependent on frequency. The expected frequency response results for the different feedback techniques are illustrated in Fig. 3. The curve (1) in Fig. 3 is the case without feedback; the curve (2) is the case of resistive feedback. The resistive feedback reduces the gain at low frequency but has the same gain-bandwidth, GB 1, as that in the case without feedback. Curve (3) is the case of MOS transistor feedback and here the gain is reduced to the value for resistive feedback; however, the gain-bandwidth is increased to GB2. It is clear that in the case of transistor feedback, an even higher gain-bandwidth can be obtained by reducing the gain of the amplifier.
,%
Ad
I
',
!\,2,
;
I\
I
I
fPO fP1
fP2
\ 6B1
fiB2
frequency Fig. 3
Predicted frequency response of different feedback techniques. Curve (1): No feedback. Curve (2): Resistive feedback. Curve (3): MOS transistor feedback.
2.2 Circuit description A complete operational amplifier circuit consisting of only 13 transistors employing the transistor feedback principle developed in section 2.1 is shown in Hg. 4. Two stages are adequate to obtain more than 60dB gain. Mt, M2, M3 and M4 is a conventional differential input stage, with M5 serving as the current s o u r c e . M9 and M~0 acts as a gain stage/output stage, biased as a class AB amplifier in order to obtain a high output swing with low distortion. Class AB is chosen in preference to class A operation as experiment and theory show that class AB CMOS amplifiers have a much lower distortion than class A, CMOS amplifiers 7. M6 and M7 consists of a level-shifter and Ms, using M4 as its load device, realises the negative feedback compensation. The function of M8 is to move up the low frequency pole, improving the phase shift of the operational amplifier, as described in section 2.1. The
j
M1k
v lifo
-I,
(12) [
(lq)
M1i I _
M5
Fig. 4
Vss
_
CMOS operationalamplifier circuit. *p-channel devices.
2000
~(Pk-to-Pk)/~
II
f phose/ angle
1500
1000
500
lOmV
0lm'~ 103
I
I
104
105
0o 106
107
frequency (Hz) Fig. 5
Simulated frequency response of the amplifier. Input signal I mV rms. Curve (1): Compensated with MOS transistor. Curve (2): Compensated with capacitor.
P
High slew rate CMOS operational amplifier employing internal transistor compensation cont. from page 9
transistor combination, M]t, MI2 and Ml3 forms a bias string to supply a bias to the gate of current source transistor Ms and load transistor M7 of the level-shifter. Most of the MOS devices in this operational amplifier are n-channel which have low body effect and high gain, resulting in an improvement in the performance. For example, the body effect plays a major role in determining the distortion of the amplifier s. The substrate was chosen to be high resistivity to minimise the parasitic capacitances. As is usual practice in CMOS operational amplifier design, the n-well is connected to the positive power supply and the substrate is connected to negative power supply, therefore only two power supplies are needed. The circuit is designed for power supply rails of +-5 volts. The frequency response and phase characteristic simulated by the SPICE simulation program for internal transistor compensation is shown in Fig. 5. The pole frequency has moved up to 8kHz with transistor feedback, from about 2kHz when a compensation capacitor is used and the unity-gain bandwidth is increased to 8MHz from about 2MHz, respectively. The phase margin is predicted to be 50 degrees with transistor compensation. 3.
CMOS processing
The process used is n-well, CMOS, polysilicon-gate technology which combines the low power of CMOS with the high speed of NMOS devices. The process employs five implantation steps; for n-well formation, field threshold-voltage control in the p-substrate, threshold-voltage adjustment of both NMOS and PMOS devices, and the source/drain formation of NMOS and PMOS devices. The silicon wafers were p-type, (100) orientation, having a resistivity of 18flcm. Phosphorus ions were implanted into the substrate at 100keV with doses about 1.5 x 1012cm-2 to form an n-well region. A phosphorus drive-in was undertaken at 1150~ for about 19 hours in an N2 atmosphere, resulting in a well depth of about 5 F m in order to reduce the gain of parasitic PNP transistor and the latch-up effect. Boron ions were implanted into the field regions outside the n-well at 25 keV with doses of 7 x 10t3cm -2 to control the field threshold-voltage in the P-substrate. The threshold-voltage of the complementary-channel devices was adjusted to be 1V for NMOS, and - 1 V for PMOS by boron implantation to NMOS and PMOS regions at 40keV with doses of 6 x 10item -2, simultaneously. The source/drain junctions of the NMOS devices were formed by phosphorus implantation at 90KeV with doses of 7 • 10t~cm-2; the source/drain junctions of the PMOS devices were formed by boron implantation at 35KeV with doses of 2 x 10tScm-2. The junction depths of both the NMOS and PMOS sources/drains were controlled to 1/zm by the subsequent processing.
+VIN -VIN
VSS
II
I VOUT
VDD Fig. 6 Chipphotograph of operationalamplifier. 10
Table I
Note 1: Note 2: Note3: Note 4:
Performance of the CMOS operational amplifier
active area
0.056 mm 2
low frequency gain
60-67dB
power dissipation
11.5 mW
unity-gain bandwidth
8-12MHz
input offset voltage
7.6 - 10roW
slew rate (note 2)
positive 36V - 50V/gs negative 40V - 50V/p.s
settling time to one per cent (note 2)
0.25p.s
common-mode rejection ratio
82-88 dB
power supply rejection
58dB
distortion (note 3)
-73 dB
noise (note 4)
300 - 400 nV/x,,tJT
For above, VDD = "[-5V, VSS = -5V. load capacitance 32 pF; step voltage = 4V. fundamental, 20 kHz; output voltage 5 V peak-to-peak. measured at 1kttz.
4. Experimental results E x p e r i m e n t a l o p e r a t i o n a l a m p l i f i e r s w e r e i n t e g r a t e d as p a r t o f a m o n o l i t h i c fifth-order, elliptic filter r e a l i s e d in a s w i t c h e d - c a p a c i t o r configuration. A chip p h o t o g r a p h o f a typical o p e r a t i o n a l a m p l i f i e r t o p o l o g y is s h o w n in Fig. 6. T h e m e a s u r e d p e r f o r m a n c e o f the o p e r a t i o n a l a m p l i f i e r is s u m m a r i s e d in T a b l e I, e x h i b i t i n g high slew rate a n d low d i s t o r t i o n . F i g u r e 7 d e m o n s t r a t e s t h e slew r a t e p e r f o r m a n c e o f a typical o p e r a t i o n a l a m p l i f i e r w h e n
r~.7 Step response of operational amplifierconnected as voltage follower. Upper trace - input signal. Lower trace - output response. Horizontal scale: 0. l/~s/div. Vertical scale: 1 V/div. 11
High slew rate CMOS operational amplifier employing intemal transistor compensation conL from page 11
Fig. 8 Distortion of CMOS operational amplifierconnectedas voltage follower. Output signal5 V peak-to-peak. Fundamental 20 kHz. c o n n e c t e d as a unity-gain buffer with a load capacitance of 32pF, in response to an input step of 4 volts at a 1MHz rate. The measured slew rate is 36-50 V/~s, and the settling time to one per cent is estimated to be about 0.25/xs. Figure 8 shows the distortion of the amplifier at 2 0 k H z with an output voltage of 5 volts peak-to-peak for a ---5 volts power supply. The second harmonic coefficient is eliminated by the push-pull output stage, and the third harmonic coefficient was measured to be - 7 3 dB. T h e frequency response of a prototype, monolithic, fifth-order, elliptic, lowpass switchedcapacitor filter using this operaticnal amplifier is shown in Fig. 9. T h e experimental frequency response gave acceptance agreement with the simulated variation, validating the
Fig. 9 Frequencyresponse of experimentallmonolithic5th-order, elliptic, lowpass CMOS filter.
performance obtained from the amplifiers. However, the pronounced peak in the passband near the cut-off frequency of 0.88dB is explained due to over-compensation of the finite gain and bandwidth of the operational amplifier. 5.
Conclusions
The results of this work have shown that an operational amplifier employing internal feedback transistor compensation may achieve high speed and low distortion, when realised with n-well CMOS polysilicon technology. The features of this technique are as follows: (i) Reduced silicon area. The operational amplifier presented here has an active area of only 0.056mm 2 by eliminating the compensation capacitor. The amplifier should therefore be a high yielding structure. (i) High slew rate. Up to 50V//.ts with a load capacitance of 32pF. (iii) Non-linear distortion caused by any non-linearity of the usual compensation capacitor is reduced. The internal feedback transistor improves the distortion of the operational amplifier because of internal negative feedback. The total distortion is down to - 7 3 d B with an output voltage up to 5V peak-to-peak. The effect of the feedback transistor on the distortion of the operational amplifier will be described elsewhere 7. This high performance operational amplifier is suitable for many video frequency applications including switched-capacitor filters and analogue/digital interface circuitry. As no compensation capacitor is required it may be integrated in a single layer, polysilicon process which does not support well-defined capacitor formation. 6. Acknowledgments
The wafers were fabricated in the SERC-supported, Edinburgh Microfabrication Facility. The authors wish to thank Mr Tong Qinyi for the innovative CMOS processing and Dr J Pennock for comments on the draft paper. The support of the Ministry of Education of the People's Republic of China is also acknowledged. 7.
References
[I] Tsividis, Y. P., and Gray, P..R., "An integrated NMOS operational amplifier with internal compensation", IEEEJSSC, SC-II, 748-753 (1976). [2] Allstot, et al., "MOS switched capacitor filters", IEEEJSSC, SC-13, 6,806-821 (1978). [3] Senderowicz, D., et aL, "High-performance NMOS operational amplifier", IEEEJSSC, SC-13, 6, 760-766 (1978). [4] Gregorian, R., and Nicholson, W. E., "CMOS switched-capacitor filters for a PCM Voice CODEC", IEEEJSSC, SC-14, 6,970-980 (1979). [5] Ishihara, T., et al., "A high speed NMOS operational amplifier fabricated using VLSI technology", Electronics Letters, 18, 4, 159-161 (1982). [6] Gray, P. R., "Basic MOS op amp design-an overview", in "Analog MOS integrated circuits", ed. P. R. Gray, D. A. Hodges and R. W. Brodersen, IEEE Press, New York (March 1980). [7] Wu, B. X., and Mayor, J., "Distortion in CMOS op amp" (paper in preparation). I'8] Tsividis, Y. P., "Harmonic distortion in single-channel MOS integrated circuits", IEEE JSSC, SC-16,694-702 (1981).