High speed CMOS gate arrays

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High speed CMOS gate arrays by A. Dantec and J. Desuche Matra-Harris, Nantes, France

A family of high speed CMOS gate arrays has been developed using single metal layer advanced CMOS processing. In this paper we describe the array structure and present the performances obtained on a test vehicle designed on a 1200 gates matrix. Further on, we discuss the user-manufacturer interface by presenting the design procedure and the software aids associated with each step of the development flow.

1. Introduction To electronic engineers worried by packing density, power dissipation, reliability and cost optimisation of equipment, three ways are proposed to integrate systems into silicon: off-the-shelf programmable functions (microcomputers, FPLA, PAL), full custom circuit development and a semi-custom approach. In the last category gate arrays are privileged over other solutions in terms of the optimised trade-off they offer between cost, development cycle time and specific knowledge required by the designer. Ranging from a few hundreds of gates to 5000 gates or even more, a broad range of arrays is now available. By using an advanced but simple (one metal level) 3 micron CMOS process, these arrays provide high speed circuits with typical internal gate delays in the 2-3ns range. After a general description of the architecture and basic cell of the array the process used for manufacturing will be discussed briefly. The performances of these arrays are then presented through the results obtained from a test vehicle developed on the 1200 gates array. Since, for the user, an array is nothing without an extensive cell library and without an efficient set of CAD tools, the procedure for circuit design using these gate arrays is presented. Through the development flow of a circuit, the various aids provided by the manufacturer are then described, pointing out the integrated concept of the CAD system which permits efficient and reliable design. 2.

Array architecture and basic elements

Designed for digital applications, the array structure uses a rather classical approach with a central matrix organised in rows of uncommitted basic cells and routeing channels surrounded by flexible input-output cells. However, the basic cells (Fig. 1) as well as the array itself (Fig. 2) have been designed to achieve maximum efficiency in lay-out and interconnection when using either automated or interactive tools for cell placement and routeing. The basic cell Consists of two pairs of n- and p-channel MOS transistors associated with 2 feed-throughs in low resistivity polysilicon. An all metal supply distribution is achieved within the cell by two wide aluminium lines able to support current surges that may be required in high frequency operation of a circuit. One contact per cell between these supply lines and the substrate and the p-tub achieves a constant bias all through the matrix. M[CROELECTRON1CS JOURNAL Vo114 No 3 © 1983 Benn Electronics Publications Ltd, Luton

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High speed CMOS gate arrays continued f r o m page 41

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Fig. 2b

The array family characteristics.

As a consequence of the regular structure of the array the customisation pattern of library cells can be inserted on the matrix directly or mirrored and can be translated on a row by an integral number of cell steps. Associated with the basic internal cell a set of thirteen routeing channels is provided for metalinterconnection, five of which are located in the active area and are devoted mainly to the library cell customisation pattern. The eight others run over polysilicon underpasses and allow long distance interconnections. Such wiring capability is sufficient to achieve good layout efficiency with most circuits. However, in the case of critical circuits (for instance having highly parallel organisation), six extra wiring channels can be obtained per basic cell. This additional capability is provided by customising the contact level in the routeing areas. Using 3 micron design rules, the size of the basic cell is 290 x 70 microns, all interconnects, being drawn on a 10 x 10 microns grid. An example of a customisation pattern is presented (Fig. 3) for a simple latch circuit using two basic cells. 42

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The peripheral cell (Fig. 4) increases the versatility of the array by providing additional flexibility on input/output. In fact, any of the cells surrounding the matrix can be programmed as: • TTL input • CMOS input • TTL compatible output • high impedance output • bidirectional input/output • VoD orVss Additional possibilities are offered by high impedance transistors which can be used as pull-up, pull-down or for other interface purposes. Particular care has been taken in the layout to protect the circuit against parasitic phenomena such as electrostatic damage and latch-up. Protection networks are available to prevent gate destruction on inputs and extensive guard-bands, in addition to specific processing steps, contribute to make the circuit virtually latch-up free.

Fig. 4 Peripheralcell. 3. Process description and array performances Figure 5 presents a cross section of the scaled CMOS process which is used to manufacture the gate arrays. The association of 3 micron lithography and a self-aligned CMOS process provides electrical parameters which permit the realisation of fast digital circuits. By using local oxidation to separate adjacent active regions a high packing density of chips is achieved together with a lowering of field and side wall capacitances. Self-aligned field implants are utilised to increase the field transistor threshold and to lower the n-substrate and p-well resistance which contribute to latch-up improvement. Some key figures of the process are listed in Table I . To evaluate the array performances a test vehicle has been built using the 1200 gate matrix (Fig. 6). In order to cover static, dynamic and functional aspects of the characterisation this evaluation chip contains various circuits and devices including the major ones listed as follows: internal p- and n-channel transistors; 44

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-- peripheral p- and n-channel transistors; passive devices (underpaths, metal lines, gates, etc.) for resistance and capacitance evaluation; - all configurations of I/O cells (output buffers, TEL or CMOS input buffers, high impedance transistors, etc.); - 39-stage ring oscillator for dynamic evaluation; special cells such as Schmitt trigger, multivibrator, power on reset, oscillator, etc.); functional circuits such as a long shift register (120 stages), barrel shifter, frequency dividers in order to get yield estimation of complex circuits and determine operation limits of the array. This test chip, primarily defined for internal characterisation of the product, will be available in a 64-pin package, permitting further investigation by the user and constituting an ideal qualification vehicle for both process and circuit aspects. Hgure 7 shows the oscillogram of the 39-stages ring oscillator output at room temperature and Vcc = 5 volts. This circuit has an operating frequency of 14.5 MHz, equivalent to an internal propagation delay of 0.9ns per stage (in this case the fan-out of each inverter of the ring is equal to 1). This short propagation delay justifies for this array family the 'high speed' label which is also confirmed in some typical figures listed in Table II. -

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Gate array circuit design procedure The current philosophy in gate array design is clearly to put in the user's hands all information and tools for him to handle directly the development of his circuit. Such an approach requires strong support from the manufacturer to the customer. This support has several aspects including training, a large and well documented cell library, efficient CAD tools, and technical assistance from the feasibility study to the final test and product delivery. Pigure 8 describes a typical development flow, pointing out the responsibility shared between manufacturer and customer. 4.

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In this approach, after a training session, the customer is able, from his specification and the library, to build up the circuit logic schematic. From this point CAD aids reviewed in the next paragraph are used by the customer to construct the data base from which personalisation masks are generated. Then, the manufacturer takes back the control and completes all the back end processing up to the delivery of tested prototypes. The library provided to the customer is somewhat equivalent to a digital products data book. In this library any cell has its own data sheet including logic specification and diagram topological characteristics, electrical data and logic simulator reference as can be seen in Fig. 9. A special feature has to be noticed about this library. It is composed of two distinct levels: • Level 1 consists of elementary cells (such as NOR, NAND, D FLIP-FLOP) always laid out on one active row. • Level 2 consists of more complex cells (counter, adder) which require more than one row to be laid out. Depending on what software is used for mask generation, the level 2 cell behaves differently. In an interactive lay-out is performed the cell is considered as a rigid block whose logical, electrical and graphical characteristics are frozen and not alterable. If automatic placement and routeing is to be used the level 2 cell is then factorised into level 1 cells. The level 2 cell is not any more graphically predefined and becomes a soft cell whose final shape will be determined by the automatic lay-out software. This additional degree of freedom is helpful for the software to get faster convergence during the placement phase. 47

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5. CAD t o o l s for gate arrays 5.1 Goals The realisation of the personalisation mask with present custom design methods can be performed only with diverse and costly C A D aids and by skilled engineers. Moreover, a gate array approach is economic if short turnaround can be attained, which implies availability of tools. The C A D program provides: - a way for a system, rather than a circuit, designer to integrate his logic into silicon. - continuity between the different steps from logic architecture to chip testing. - circuit development without breadboard realisation, thanks to a logic simulation using realistic propagation delays. It has been made possible by a precise, but user-transparent, modelling of the device and its network behaviour. - documentation aids (schematic, simulation results, symbolic lay-out, mask plots). 5.2

The objects

A gate array is defined on a regular matrix. Object co-ordinates are trapped on grids, rows, columns or channels. These data are parameterised which guarantees transparency to technology changes. Blocks, corresponding to logic functions, take place on this matrix; connections between cells lie in wiring channels. This structure is well suited to simple description of circuits; indeed there is a direct correspondence between logic schematic (either in graphic or connection list form) and the lay-out in symbolic form (Fig. 10). Although transcription to a physical mask occurs at the end of the development process, simulation fits electric behaviour from the very beginning. 5.3 Data and program structure The logic data base contains the complete description of the customer circuit. It is a reference file. In order to simulate actual behaviour of the circuit, most of the programs access this data base and use manufacturer's files containing: Q

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truth tables test vectors electrical characteristics topological data This set of information ensures a good fit with the physical reality. The graphic data base contains the lay-out in symbolic form and is generated by interactive and/or automatic lay-out programs. Software uses this file to make correspondence: from graphic symbols to logic from graphic symbols to masks Figure 11 shows the CAD tools flowchart and logic schematic. -

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GRAPItE: Graphic Editor Provides a graphic entry of logic schematic. The editor logically links connected I/O. Node names are given by the user or the system. Outputs are: a connection list plots for production documents -

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LSGA: Logic Simulator for Gate Arrays In addition to normal features of a modern interactive or batch mode logic simulator working with 9 logic states (i.e. timing control and spikes detection), it offers some extra features: - an extensive library describing each cell in terms of simulator primitives (macro) - a zero delay (pseudo functional) simulation mode - a network analyser amd operating conditions scaler calculating separate rise and fall propagation delay times - a test option verifying toggle. It ensures that all nodes in the network have been exercised. - the internal structure of the logic simulation has fault analysis capabilities, so providing fault detection facilities, and then automatic test pattern generation. ILGA: Interactive lay-out of Gate Arrays This is a graphic editor providing an easy way to lay down and move cells and metallisation. The routeing task is facilitated because special symbols indicate I/O in the current connection. Partial or total symbolic plots of the circuit can be drawn for documentation use.

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Fig. 12 MHS gate arrays CAD tools. CHECK: Lay-out and design rule checker This is ILGA's complement. It checks correspondence between logic description and lay-out and detects design rule~ violation. Intermediate checking capability limits the risk of serious mistakes and ensures a good final result. ALGA: Automatic Lay-out of Gate Arrays Automatic placement and routeing in one level of interconnection is automatically performed. I L G A is therefore useful to pre-place cells (pads for instance), to check the lay-out and to route some possible unrouted connections. 80% silicon use is normally expected with fully automatic routeing. The lay-out of 800 gates on the 1200 array is achieved on a V A X 780 in about 20 minutes. ECOGA: Electric Checking Of Gate Arrays: For each equipotential line, the total length of metal and polysilicon is computed. It gives worst case capacitance and resistance values and therefore additional parasitic delays. A new simulation taking into account delays over standard value can now be run. 51

High speed CMOS gate arrays continued from page 51

A logic simulation output file is the basis of functional testing which is made on S E N T R Y test equipment. PATFORM is an intelligent translator, generating and compacting bit patterns and inserting a logical mask to prevent erroneous sampling. PATFORM:

MASGEN: Mask Generator Using a graphic data base, this program: - generates a PG tape in optic or e-beam format makes plots of the metallisation mask. 6.

Conclusion

We have outlined in this paper the major features of a gate array family which associates high speed characteristics with the well known very low power consumption inherent to CMOS structures. Simple in their concept, since they are using just one metal layer for customisation, these arrays appear also simple to use, thanks to efficient software. However, for higher density arrays presently in development, two metal layers of interconnection are mandatory to achieve good lay-out efficiency. Most of the software that has been presented remains compatible with the new gate array generation to come.

52