High speed decimal scaler with a centesimal top counting stage

NUCLEAR INSTRUMENTS AND METHODS IO6 (I973) 563-567;

© NORTH-HOLLAND PUBLISHING CO.

H I G H S P E E D D E C I M A L SCALER W I T H A C E N T E S I M A L T O P C O U N T I N G STAGE SUSUMU INABA and KAZUO HUSIMI Institute for Nuclear Study, University of Tokyo, Tokyo, Japan

Received 25 September 1972 A high speed decade scaler with a unique centesimal counter at the top stage has been designed using integrated circuits. The centesimal counter consists of two high speed IC flip-flops and two quinary counters in series. By using this circuit configuration,

it is possible to improve the counting rate of this decade scaler up to the maximum rate of the first flip-flop. This method will be superior in many respects compared with other methods of high speed decimal counting.

1. Introduction

components. This type of high speed decimal scaler is referred to as the H-scaler, and will be explained briefly in the following section. The scaler using the centesimal counter at the top stage is a special case of the H-scaler; however, it greatly simplifies the circuit technique, because conversion from a centesimal number to a two-digit decimal number is not so difficult. This also brings about the possibility of designing an economical high speed decimal scaler with integrated circuits.

The decimal scaler is the most popular electronic instrument for counting random events and is widely used, not only in high energy physics experiments, but also in many fields of digital measurements. The binary scaler is suitable for high speed counting, but is used in a limited field like computer aided data acquisition. Therefore, improvement of the decimal counter time resolution embodies a large technical benefit. Though integrated circuit binary counters which have counting rates higher than 100 M H z are now available, counting rates of the integrated circuit decade counters are still as high as 50 MHz. These circuits are composed of four flip-flops and precautions are taken to suppress 6 out of the 2 4 = 16 possible states. The feedback technique is one of the common methods for this purpose. Obviously, the counting rate of a scaler using this feedback is not determined by the resolution of the flip-flop itself but by the much greater signal propagation delay from the first to the last counting stages. There are several methods I'2) proPOsed for this high speed decimal counting, but these seem inevitably to be complicated or to have critical tolerance. In general, the scaler has a possibility of the upper limit of the counting rate being solely determined by the maximum rate of the first stage. For realizing this extreme case in the decimal counting, one of the authors has developed a high speed decimal counting method by using "the nondecimal top counting stage"3). The 120 M H z frequency counter TR-3189", which used the Esaki-diode pair flip-flop at the first stage, was designed applying this method. But this type of decimal counter is not in production now, because the conversion circuits from non-decimal to decimal counting require many excessive circuit * Product of Takeda Riken Industry Co., 1964.

2. Counting principle The counting rate of the decade counting circuit can be increased by connecting one or two flip-flops in the preceding stage of the decade counter. Fig. 1 shows an example of the H-scaler, where two flip-flops, BI and B2, and one decade counter D O are connected in series. These consist of the forty counter scale P. The maximum counting rate of this forty counter scale is four times the maximum counting rate of the decade if the first stage flip-flop is able to work at this rate. The carry output from this forty counter scale appears not for every ten input pulses but for every forty input pulses, therefore it is necessary to send out four carry pulses for each carry output to the following decade by the pulse multiplier. It is also necessary to convert the count number in the forty counter scale into decimal number each time the counting is completed. This is performed by decade counter D1 and P i

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preset pulse generator E, which send out the same number of pulses with the count stored in the forty counter scale. Carry output from decade scaler D~ is sent out to the following decade scaler Dlo. In this way, the final decimal count is obtained in the decade scalers D1, D~o, D~oo .... The H-scaler is applicable not only to the forty counter scale but also to the integer multiple of the decimal type counter, such as the twenty or thirty scale counter. It is interesting to know that the ternary counter is also useful for the purpose of decimal counting in the form of the H-scaler. The ternary ring counter is expected to have a counting rate higher than that of the binary counter and a wider tolerance for circuit components compared with the quinary ring counter. Moreover, the ternary ring counter will perhaps consume a smaller driving power compared with the quinary counter. The centesimal scaler is a special H-scaler, but it greatly simplifies the code conversion circuit. The decade scaler is usually composed of a binary counter (a)

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and a quinary counter connected in series. The two-digit decimal scaler is composed of two decade scalels, as shown in fig. 2a. The counting rate in this case is limited not by the counting rate of the binary counter at the top stage but by the maximum rate of the quinary counter at the second stage. In the centesimal counter, two binary counters and the two quinary counters are connected in series, as shown in fig. 2b. In this circuit configuration, the input pulse rate is divided by two by each flip-flop before entering the quinary counter, and the maximum counting rate of the quinary counter is no more a limiting factor of the counting rate of this scaler. By using this centesimal scaler, it is not only possible to send out the carry signal directly to the following stage, but it is also possible to simplify the complicated conversion circuit of the stored number, which is necessary in the H-scaler. These are the important advantages of this centesimal scaler. The count number in the centesimal scaler is continuously being converted during counting into the two-digit decimal number by the decoder described in the following section. 3. Circuits

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3.1. DECODER The function of this decoder is to transpose the binary counter at the second stage and the quinary counter at the third stage logically. The two binary counters and the first quinary counter consist of the twenty counters scale. The number in the twenty counter scale belongs to either the group 0-9 or the group 10-19. The decoder detects to which group the

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number belongs and determines the number itself (modulus 10). It is possible to drive several variations of the decoder according to this relation. Fig. 3 shows one of the circuits, in which the number in the centesimal counter is not decoded into decimal directly, but to the BCD code at first and then decoded into decimal form by using the BCD-to-decimal decoders. This method is not only useful for reducing the number of integrated circuits used, but is also suitable for deriving the outputs of the BCD code. This method is also well adapted for using the solid state light emitting diode indicator. Because BCD-to-7 segment decoder/drivers are available instead of the BCD-to-decimal decoders. Fig. 4 shows a block diagram of the counter and the readout circuits. The first quinary scaler is the divide-byfive counter mounted in the decade counter SN74196, and the second quinary scaler is also the divide-by-five counter mounted in the decade counter SN7490. The readout gate uses the open collector N A N D gate for each data line, therefore it is possible to perform wired-OR of the outputs of the counter modules. 3.2. INPUT PULSE SHAPER The pulse forming network which amplifies the 2AV q r OV'-' 0

input pulse and shapes it into a proper wave form for driving the first counter is important for an accurate and stable operation of a high speed counter. The input pulse shaper used in this scaler is designed for counting the output pulse from a high speed discriminator or a fast coincidence circuit. The circuit of this shaper is composed of a differential amplifier and a power amplifier, as shown in fig. 5, and has a sharp cut-off threshold characteristic for the input pulse amplitude. It delivers no output for a negative pulse with an amplitude of less than 350 mV, but produces a positive 2 V output pulse for a negative pulse with an amplitude larger than 450mV. This circuit has a propagation delay time of about 3 ns. Rise time of the output pulse is 1.5 ns and the fall time is 2 ns. The start-stop gate and inhibit signals are applied on the input terminals of the diode AND gate, and the output from the gate is led to the control transistor connected directly to the differential amplifier. This circuit configuration is suitable for high speed gating. This gate is closed when the control signal is at the ground level, and is open when the signal level is lower than the threshold of - 3 V. The indicator lamp at the front panel lights up when the gate is open.

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3.3. BLOCK DIAGRAM The circuit of this scaler, as shown in fig. 6, is composed of the following: 1) mode select switch, 2) input pulse shaper, 3) counter, decoder driver and readout gate, 4) output pulse shaper, 5) carry flag control circuit, 6) visual indicator. All the circuits are enclosed in the NIM module 5¼ inch in height and 22 inch in width. The mode select switch determines the appropriate routes of the start, stop and the reset signals according to the functions specified by the switch positions " M A S T E R " , " S L A V E " and " L O C A L " . The output pulse shaper converts the IC logic level output from the last decade counter to the negative 1 ps pulse with an amplitude of 1 V across the 50 f2 load. The carry flag control circuit consists of A N D gates and a flip-flop. The output pulse from the last decade counter sets the carry flag flip-flop. This carry flag is read out by the read-out signal. The carry flag line is wired for each module, so this output can be used as the interrupt request to the computer. The carry flag can be cleared independently by the coincidence of the reset signal and the readout signal. This scaler is designed to meet the requirements of flexible uses by a combination of external controls.

SCALER

567

expected to play an important role in high energy physics experiments. The most important advantage of this counting method is to simplify the circuit technique which is required by high speed counting. This method is also economical, because the high speed counter can be designed of integrated circuits. The decoder requires only one extra BCD-to-decimal converter and four extra N A N D gates. The millesimal counter is also applicable as an extension, if an ultra high speed binary counter is available. The Esaki-diode flip-flop will also be used for this purpose. The millesimal counter requires three extra BCD-to-decimal converters and a certain quantity of N A N D circuits for the decoder. This will not be so expensive, and the method will also be superior in many respects compared with the other method of high speed decimal counting. The authors wish to express their sincere thanks to Dr M. Mishina for his valuable advice and kind encouragement throughout this work. Thanks are also due to Mr A. Yoshimura of Kyushu University for his helpful discussion about the problems of the centesimal and millesimal counters. They are also indebted to Messrs S. Tazawa, M. Kaizu and to Miss A. Sato for their kind assistance.

References 4. Conclusion

The scaler described here has been proved to work satisfactorily over the 125 MHz counting rate, and is

1) R. Engelmann, Electronics 36, no. 46 (1963) 34. 2) E. Baldinger and A. Simmen, Nucl. Instr. and Meth. 57 (1967) 141. a) K. Husimi and K. Homma, J. IECE Japan 48 (1965) 936.