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High speed simultaneous measurement of pulse area and time-of-flight for photomultiplier signals
Nuclear Instruments and Methods in Physics Research A317 (1992) 161-169 North-Holland
igh speed simultaneous measurement of pulse area and time-of-flight for photomultiplier signals E.P. Hartouni, D.A . Jensen ', B. Klima ', M.N. Kreisler, S. Lee, K. Markianos, M. Nordberg 2, M.S.Z . Rabin, J. Uribe and D. Wesson Department of Physics and Astronomy, University of Massachusetts, Amherst, Massachusetts 01003, USA
M. Church ', A. Gara, E. Gottschalk, R. Hylton 3, B.C. Knapp, W. Sippach, B. Stern and L. Wiencke
4
Columbia University, Nevis Laboratories, Irvington-on-Hudson, New York, 10533, USA
D. Christian, M.C.B. Etchegoyen, G. Gutierrez, S. Holmes, J. Strait and A. Wehmann
Fermilab, Batavia, Illinois 60510, USA
C. Avilez ', W. Correa, J. Felix, H. Flores, G. Moreno, M. Romero and M. Sosa
Instituto de Fisica, Universidad de Guanajuato, Leon, Gto., Mexico
M. Forbush 5, F.R. Huson, J .T. White and J.A . Wightman Department of Physics, Texas A&M University, College Station, Texas 77843, USA Received 17 February 1992
A modular system to provide high speed simultaneous measurements of pulse area and time-of-flight for photomultiplier signals is described . By requiring a minimum pulse size and a time-of-flight signal within a gate before recording either measurement, the system achieves several advantages over other techniques . In particular, since no time is wasted reading channels without useful information, readout speed is enhanced . The system permits accurate measurements at rates exceeding 10 MHz per channel and can be read out without excessive dead time at rates up to approximately 100 kHz . Data storage problems are also reduced. Both pulse area and time-of-flight are measured using 128 bins (7 bits). Costs are less than $40 US per channel . Other advantages and design features are discussed .
One of the challenges facing experiments in elementary particle physics is dealing with both very large numbers of detector elements and ever increasing interaction rates . For every interaction of interest, each * Supported in part by the U .S . National Science Foundation, the US Department of Energy, and the CONACyT de Mexico . Current address : Fermilab, Batavia, Illinois 60510, USA . 2 Current address : Fitchburg, MA 01420, USA. 3 Current address : IBM Research Laboratories, Yorktown Heights, New York 10598, USA . 4 Current address: AT&T Research Laboratories, Murray Hill, New Jersey 07974, USA . S Current address : DESY, Hamburg, Germany. t Deceased .
element must be interrogated, its information digitized, and read out to a data storage device . This process must be rapid enough to avoid significant reductions in the live-time of the detector . In a program of experiments (BNL E766 [1]/FNAL E690 [2]) studying hadron interactions at MHz rates, we have developed a spectrometer system [3] which addresses this challenge. In this paper, we present the details of one of the subsystems of that spectrometer - the high speed simultaneous measurement of pulse area and time-of-flight for photomultipiier signals. The design of this pulse height and time system, the PHT system, was driven by the desire for both measurement accuracy and readout speed, was limited by the constraints of overall system cost, and was guided
0168-9()2/92/$05 .() ,) 1992 - Elsevier Science Publishers B .V . All rights reserved
162
E . P. Hartouni et al. / High speed measurement for photomultiplier signals
baseline restoration circuit is included . This allows the use of ac coupling for the ADCs without pileup, even at MHz rates. This system was employed in two recent experiments. In each experiment, 240 photomultiplier channels [4] were used. Although the measurement process, readout, and reset of the PHT system could be accomplished in less than 1 Rs, both experiments used a 3 ws readout time to match the somewhat longer readout of the rest of the detector . In these experiments, several detector elements experience? -rates exceeding 10 MHz and showed no rate dependence in the ADC measurements. A sketch of the measurement technique used in our experiments is shown in fig . 1. Light from one of the detectors in the spectrometer enters a photomultiplier tube. The photomultiplier base contains a voltage divider resistor chain, a simple amplifier, and a discriminator . The photomultiplier pulse is amplified and then split into two parts. One part is transported directly to the ADC input of a PHT board. The other copy of the pulse is input to the time-over-threshold discriminator in the base. If the pulse is larger than a remotely controllable threshold, an ECL logic pulse is generated and transported to a latch [5] . If it arrives at the latch within a gate, it is restored to a full ECL level and extended in time slightly past the end of the gate. This ECL pulse, the width of which is proportional to (1 the time-of-flight being measured), is input to the TDC section of the PHT board. In our experiments, we used RG8 50 fl cable to carry the analog pulse for the ADC measurement while lower yuaiity RG58 50 ft coax was sufficient for the time-over-threshold ECL pulse to the latch. When the TDC input to the PHT board is coinci-
by a philosophy to produce systems with capabilities well matched to the measurement requirements of the experimental program. Once reaching that goal, the design is not pushed, often reducing cost and complexity. An essential feature of the resulting design is the simultaneous nature of the pulse area (ADC) and time-of-flight (TDC) measurements. For a given channel, the ADC and TDC measurements were made only if: 1) the pulse height was above a threshold : and 2) there was a coincidence between the TDC signal and the gate for that channel . If either of these conditions were not satisfied, neither the ADC nor the TDC information for that channel was digitized or read out . This suppression of channels with zeroes or nonuseful information is accomplished using discriminators in the photomultiplier bases rather than by discrimination in the ADCs or by pedestal subtraction after digitization . This method allows the use of very low thresholds since the discrimination is performed before the signals have been degraded by transit over long cables . The ADC and TDC measurements in channels with useful information are digitized using shared Wilkenson ramps with modest dynamic range, 128 bins. Only those channels are then read out . The readout proceeds through a priority sequence in which channels are read out in a predetermined order without computer control and in which each measurement is labeled for later identification. Since only channels with information are read out and since the digitized information is contained in a small number of bits, the readout is very fast and places minimal strain on the subsequent elements of a data acquisition system. Because of concerns about the reliability of the measurements at high instantaneous rates, a dynamic
High Voltage
Pulse Height Threshold
Analog P.M . Signal Base
!NfNj_"~ ~
I
Photomultiplier Tube
Digital P.M . Signal
Time of Flight Gate -
External Gate ADC Channell TDC Channel 1 PHT Board
Latch Electronics ECL Time of Flight Pulse Fig. 1 . Sketch of the measurement technique.
E.P. Hartouni et al. / High speed measurement forphotomultiplier signals
dent with an external trigger logic gate, both the TDC and ADC pulses are digitized for that channel . Otherwise, the digitization process does not occur . In what follows, we present details of the PHT board with emphasis on the digitization process and the readout scheme .
163
The PHT system is implemented with ECL10K technology. The ADC and TDC measurements for eight photomultiplier channels are made on one double-sided, 28 cm x 28 cm printed circuit board. See fig. 2. The PHT board digitizes all eight inputs to its ADC, section and all eight inputs to its TDC section simulta-
P '.
Fig. 2. Pictme of the cornimnent side of an eight-channel PHT board.
164
E.P. Hartouni et al. / High speed measurement forphotomultiplier signals
neously . This is done using a separate integration capacitor and comparator for every input and two shared reference capacitors and Wilkenson ramps - one for the ADC section, and one for the TDC section . Power (-5 .2, + 12, and -12 V), data busses, air cooling, and local controllers are provided in crates which can house
up to 128 channels. The cost of the complete PHT system is rather modest, averaging less than $40 US per channel . The digitization process for both the ADC and TDC sections of the PHT board begins with the arrival of a gate from external trigger logic. The gate, typically
GATE
5 ft . mini coax delay
+5
END
RAMP
1K
1%
10H105
50 ihev
10H105
n
ADC UNCLAMP
510
VBB
510 -12
ADC RAMP
+12
50 Pf NPO 100
ADC GATE
CONVERT 1K 1%
51
10HO116
510 1%
51 ECL Time ®f
VBB
Flight Signal
510 1% TDC Encode 50 pf NPO
100 thev
SD306DE
Fig . 3 . Schematic of the TDC measurement circuit . Only one channel is shown for clarity. the pnp transistors are unmarked capacitors are 0 .1 g F.
HOLD COMP
MPS3640 and the
EP. Hartouni et al. / High speed measurement forphotomuhiplier signals
a 25 ns wide ECL level pulse, initiates acceptance and processing of digital time and analog pulse area signals. Signals which arrive outside the gate are not processed . This gate is driven differentially to a 10H116 for each channel . The digital time-of-flight signals, also differentially driven ECL level pulses, are carried to the PHT board over 17-pair twist and flat cables . These signals arrive at the same 1OH116 while the gate is present . Fig . 3 shows the time-to-digital conversion section of the PHT board. The signal output from the 1OH116 is wire AND tied to the 1OH116 gate output (low true). The combination of these signals is logic high unless both are low. The gate-signal combination is used as the input to another buffer on the 1OH116 . The complementary outputs of this buffer are connected to the bases of a transistor differential pair to control integration . The current from a - 5 mA current source is sent through a direct path across one transistor to ground when the input to the buffer is high (no gate or gate with signal). When the input is low (gate without signal), the current is directed across the other transistor of the pair to a 50 pF integrating capacitor . The capacitor charges only when there is a gate without a signal, so the time is measured with respect to the start of the gate. Note that the gate-signal combination also excludes noise outside the gate, since a lew level initiates integration . Channels without a signal integrate for the entire width of the gate yielding the maximum possible voltage on the capacitor . After the capacitor charges, the voltage for each channel is held constant and is used as one input of a comparator. The complementary input is tied to a voltage reference, a single Wilkenson ramp. This is supplied by a similar integration circuit . However, the current source for this circuit supplies only - 0.1 mA, so the integration rate is about 1/50th that of the signal . The output of the comparator is ECL low unless the voltage ramp exceeds the voltage of the integratetii signal . When the two voltages are equal, the output swings high. Since channels that do not contain data integrate for the entire gate, the ramp is designed never to exceed the integrated signal of these channels and the comparator output never goes high (fig. 4). The comparator output is used as the clock input for two quad 10153 latches. The signal input for these latches is a Gray code generated by binary counter circuitry discussed below. The digitization of the pulse area is very similar to that for the time-of-flight. Fig. 5 shows the pulse area digitization circuitry . Each input pulse is supplied to the base of a 918 npn transistor. The emitter of the
transistor is connected to the -12 V supply by an 820 fl resistor. The transistor is therefore a current source depending on the base input voltage (the input analog
Channel Containing Data
Integrated Data Signal
Voltage Ramp
Input Output
Data in counters No Data In Counters
Integrated Data Signal
Channel Containing No Data
Voltage Ramp
Input Output
165
Data In Counters No Data In Counters
Fig. 4. Comparator logic and suppression of channels with no data. As described in the text, digitization of the integrated data signal begins only when the voltage ramp equals that signal. When the channel does not contain data, that condi tion is not satisfied and no data is stored in the counters for that channel .
signal). The + 12 V supply provides current for this source through a 470 fl resistor tied to the collector of the transistor . The current through the 470 fl resistor is held constant by another current source consisting of a 3640 pnp transistor whose base is held at constant voltage and whose collector is also attached to the resistor. The emitter of the 3640 is tied to a differential pair of 3640s with bases at complementary voltages. The gate is driven differentially to the bases of the 3640s so that at any time only one is on. Other circuitry is present to regulate the current passing through the 3640s. When the gate is present, current is directed to the integrating capacitor. The input . analog signal has the effect of decreasing the current demand through the transistor to which it supplies the base voltage . The larger the input signal, the less current the input signal branch requires. The current diverted from the input branch is passed to the integrating capacitor when a gate is present . Thus, the voltage on the capacitor increases proportionally to the size of the input signal. As with the TDC section, the voltage on the integrating capacitor is compared to a voltage ramp. The ADC voltage ramp 22 pF capacitor is supplied with 0.05 mA during integration and charges at a constant rate of a 0.0022 V/ns. The output of the comparator is used as the clock input to latch the Gray code.
E.P. Hartouni et al. / High speed measurement for photomultiplier signals
166
During the absence of the gate, the current is switched to a baseline restoration circuit, effectively providing ac coupling with a 1 Rs time constant, but with large fast signals clipped and not contributing to the average baseline. This strongly rejects ac power noise and removes any baseline shift introduced by a 10 lis ac coupling of the analog signal from the phototube bases . The baseline restoration circuit consists of a TL082 opamp with negative feedback with a 1 p,s integration time, and 1N914B diodes that clip the
4 .3v
300
51
voltage excursions of the unavoidable capacitance integrating the current . Fig . 6 shows the counter and latch circuitry for the PHT board, including the Gray code generation and the readout controls . The Gray code generation uses a 90 MHz clock, driven differentially to the PHT board and the input of a 10116 buffer . The buffer output is the clock input for a pair of 10HO16 binary counters which were reset at the end of the last conversion sequence . At the end of the previous measurement
100K
5 .6v
51
390
1K
510
-5
n
50 thev
390 Analog P .M . Signal
56
-5
ADC RAMP
6 .2K
L
ADC ENCODE
820
HOLD COMP
ADC UNCLAMP .tgt
ADC GATE
130
-5
100 thev
Fig. 5 . Schematic of the circuitry to perform the ADC measurement . Only one channel is shown for clarity . The pnp transistors are MPS3640 and the npn transistors are MP591H. The unmarked capacitors are 0 .1 p,F.
E.P. Hartouni et al. / High speed measurement for photomultiplier signals
167
TO
TDC ENCODE
10153
HOLD COMP
V30
ADC ENCODE
10153
IC
D201DOD3
Fig. 6. Counter and latch circuits, including the Gray code generation logic . cycle, a 10131 dual-D flip-flop was used to reset all counters . When a new gate arrives, the flip-flop is clocked and the reset counters begin a new counting sequence. The binary counters are cascaded as inputs to exclusive ORs to produce an 8 bit Gray code with one redundant bit, yielding 128 time bins. The Gray code is latched when the ramp voltage exceeds the
integrating capacitor voltage for the ADC or TDC section . At the end of the counting cycle, the change in state of the most significant counter bit activates the readout phase. In a multiple board system, readout order between boards is determined by an address "priority patch". The address priority patch system allows boards with
168
E. P. Hartouni et al. / High speed measurement for photomultiplier signals
lower addresses and data to hold off the readout of boards with higher addresses and data. The presence of data on the board drives the readout for the board. The change in state of the last counter bit of the Gray code generator ends the ramp cycle, allows SD306 FETs to discharge the integrating capacitors, clocks a 10131 dual-D flip-flop for each TDC channel and resets the comparator for the signal-ramp comparison. The D input for the flip-flops is the comparator output for the TDC signal-ramp comparison. If the channel contains data, the Q output on the flip-flop will go high. This output is connected to a 10165 priority encoder in order by increasing TDC channel number . Channels with data are prioritized for readout with channel 0 having highest priority . The 03 output of the encoder is used to signal that data is present . The other three outputs, QO-Q2, of the encoder serve multiple purposes . The outputs are used to define the address of the channel currently being read out . These outputs are also connected to two 10161 binary to 1-8 decoders, one each for the TDC and ADC sections. The outputs of these decoders, when gated by a read clock (supplied externally), are used to gate consecutively the latches which contain the TDC and ADC data. To teduce the number of data output lines, the latch outputs for all eight channels are connected to a data bus . Channels containing data are read into data buffers . Finally the encoder outputs are passed to a 10162 binary to 1-8 decoder which is used to reset the flip-flop of the channel being read out . Each flip-flop is reset as its latch is read into the data buffers. This insures the proper readout sequence. The number of channels containing data determines the duration of the read cycle since no time is wasted reading empty channels . Since the ADC and TDC information for a given nonempty channel are transferred simultaneously, a single channel can be read out in about 25 ns (the read cycle clock period). The complete read cycle duration if all eight channels contain data is about 200 ns. At the completion of the read cycle, the Q3 output of the priority decoder goes low . This generates a logic signal to the system that the board is ready for the next gate. Studies of the performance of the PHT system were made in a test stand [6] constructed for that purpose . In that setup, the behavior of the TDC section was investigated by repeatedly adding 1 ns delays to the TDC input signal . As expected, these studies showed some small nonlinearity of the TDC for times near the beginning of the ramp due to the finite time response of the current switch . This posed no problem for our needs. The time-of-flight measurement range used in the experiment was selected to avoid that portion of the ramp. The linearity of the rest of the ramp was quite adequate. These test stand studies were augmented by calibra-
tions of the 240 channel system measured in place during the experiments. A precision computer controlled pulser was used to generate a start and stop pulse . The time between these pulses could be adjusted in 51 .3 ps steps . The start pulse was used as the external trigger to generate the gate for the PHT boards . The stop signal was used to generate the ECL digital input signal to the TDC section of the PHT board, thereby simulating the signals received by the system in normal operation . All 240 channels were tested . By performing a linear fit to the data from each channel, we obtain an average slope of 0.127 ns/bin . The channel to channel variations in the slopes were quite reasonable. The distribution of slopes for the 240 channels had a half width half maximum of 0.008 ns/bin . The calibration of the pulse area measurement was studied using the test stand. By attenuating an input pulse from a photomultiplier, the pulse area or charge on the integrating capacitor needed to produce a one bin change in the ADC reading could be determined . Typically, a charge of 0.31 pC produces an output change of one bin . Since zero suppression was done using a discriminator in the phototube base, it was possible to make meaningful measurements of very small pulses . The discriminator thresholds were set low enough that good time measurements were made even for the smallest signals - a few mV at the peak and roughly 5 ns wide. For some of the Cherenkov counter photomultiplier tubes in the spectrometer, the pulse height spectra for one photoelectron signals were not separated from the ADC pedestals . Yet, the efficiency of the measurement of such signals was - 100%. The effects of power supply voltage variations were also studied . The PHT board requires three supplies; -5 .2, + 12, -12 V. No effect on the performance or calibration of either the ADC or TDC measurements could be observed when the regulation on these supplies was kept within the following limits : - 5 .2 ± 0.1 ; +12±0 .2, and -12±0.4 V. The PHT board can be modified for other applications easily . For example, it would be straightforward to change the current 8 bit Gray code - 128 bins with redundancy - to 256 bins without redundancy . Also, the Wilkenson ramp circuit can be adjusted to set the size of a single bin for the TDC section . By changing the 39 W resistor from + 12 V to the emitter of the 3640 transistor, the current for the ramp is modified and a new bin width is set . In the same manner, changing the 100 kil resistor for the ADC ramp circuit sets the bin size for that section . We typically allow 10 min for a newly powered PHT board to reach thermal equilibrium. If large variations
in the temperature of the boards are possible, studies of the effect sin the calibration would be advisable .
E.P. Hartouni et al. / High speed measurement for photomultiplier signals The system was used in two experiments in which more that six billion events were recorded. The PHT system proved to be quite reliable . When a channel died, it was almost always due to the failure of a JFET SD306 or one of the 10116s. Once the system was operational, failures were quite infrequent. Acknowledgement We would like to acknowledge the able assistance of the electronics technicians at the University of Massachusetts, Nevis Laboratories, and Fermilab. References [1] BNL E766, Study of fl- Production and Development of On-Line Hardware Processing, Columbia University, University of Massachusetts, Universidad de Guanajuato, Fermilab, and Texas A & M University collaboration, Brookhaven National Laboratories, Upton, Long Island, NY 11973, USA .
169
[2] FNAL E690, Study of Hadronic Production and Spectroscopy of Strange, Charm and Bottom Particles at the Tevatron, Columbia University, University of Massachusetts, Universidad de Guanajuato, and Fermilab collaboration, Fermi National Accelerator Laboratory, Batavia, IL 60510, USA. [3] A description of the spectrometer is in preparation. See also: M. Church, 'E-Production in 15-28 GeV NeutronProton Interactions, Columbia University Ph.D. Thesis, Nevis 260 (1986), Nevis Preprint R#1354 ; B. Stern, A Search for Charmed Particles in 15-28 GeV Neutron-Proton Interactions, Columbia University Ph.D. Thesis, Nevis 266 (1988), Nevis Preprint R#1386. [4] In BNL E766 and FNAL E690, both EMI 9954B and Amperex XP2262/H02 photomultipliers were used. [5] The photomultiplier system including the choice of tubes, the design and operation of the bases, the high voltage distribution system, and the latch electronics for this spectrometer will be discussed in a separate paper, in preparation. [6] M.M. Nordberg, Analysis of Time Measurement Resolution of the Brookhaven Experiment 766 PHT System, M.S. Thesis, University of Massachusetts (1988), unpublished .
igh speed simultaneous measurement of pulse area and time-of-flight for photomultiplier signals E.P. Hartouni, D.A . Jensen ', B. Klima ', M.N. Kreisler, S. Lee, K. Markianos, M. Nordberg 2, M.S.Z . Rabin, J. Uribe and D. Wesson Department of Physics and Astronomy, University of Massachusetts, Amherst, Massachusetts 01003, USA
M. Church ', A. Gara, E. Gottschalk, R. Hylton 3, B.C. Knapp, W. Sippach, B. Stern and L. Wiencke
4
Columbia University, Nevis Laboratories, Irvington-on-Hudson, New York, 10533, USA
D. Christian, M.C.B. Etchegoyen, G. Gutierrez, S. Holmes, J. Strait and A. Wehmann
Fermilab, Batavia, Illinois 60510, USA
C. Avilez ', W. Correa, J. Felix, H. Flores, G. Moreno, M. Romero and M. Sosa
Instituto de Fisica, Universidad de Guanajuato, Leon, Gto., Mexico
M. Forbush 5, F.R. Huson, J .T. White and J.A . Wightman Department of Physics, Texas A&M University, College Station, Texas 77843, USA Received 17 February 1992
A modular system to provide high speed simultaneous measurements of pulse area and time-of-flight for photomultiplier signals is described . By requiring a minimum pulse size and a time-of-flight signal within a gate before recording either measurement, the system achieves several advantages over other techniques . In particular, since no time is wasted reading channels without useful information, readout speed is enhanced . The system permits accurate measurements at rates exceeding 10 MHz per channel and can be read out without excessive dead time at rates up to approximately 100 kHz . Data storage problems are also reduced. Both pulse area and time-of-flight are measured using 128 bins (7 bits). Costs are less than $40 US per channel . Other advantages and design features are discussed .
One of the challenges facing experiments in elementary particle physics is dealing with both very large numbers of detector elements and ever increasing interaction rates . For every interaction of interest, each * Supported in part by the U .S . National Science Foundation, the US Department of Energy, and the CONACyT de Mexico . Current address : Fermilab, Batavia, Illinois 60510, USA . 2 Current address : Fitchburg, MA 01420, USA. 3 Current address : IBM Research Laboratories, Yorktown Heights, New York 10598, USA . 4 Current address: AT&T Research Laboratories, Murray Hill, New Jersey 07974, USA . S Current address : DESY, Hamburg, Germany. t Deceased .
element must be interrogated, its information digitized, and read out to a data storage device . This process must be rapid enough to avoid significant reductions in the live-time of the detector . In a program of experiments (BNL E766 [1]/FNAL E690 [2]) studying hadron interactions at MHz rates, we have developed a spectrometer system [3] which addresses this challenge. In this paper, we present the details of one of the subsystems of that spectrometer - the high speed simultaneous measurement of pulse area and time-of-flight for photomultipiier signals. The design of this pulse height and time system, the PHT system, was driven by the desire for both measurement accuracy and readout speed, was limited by the constraints of overall system cost, and was guided
0168-9()2/92/$05 .() ,) 1992 - Elsevier Science Publishers B .V . All rights reserved
162
E . P. Hartouni et al. / High speed measurement for photomultiplier signals
baseline restoration circuit is included . This allows the use of ac coupling for the ADCs without pileup, even at MHz rates. This system was employed in two recent experiments. In each experiment, 240 photomultiplier channels [4] were used. Although the measurement process, readout, and reset of the PHT system could be accomplished in less than 1 Rs, both experiments used a 3 ws readout time to match the somewhat longer readout of the rest of the detector . In these experiments, several detector elements experience? -rates exceeding 10 MHz and showed no rate dependence in the ADC measurements. A sketch of the measurement technique used in our experiments is shown in fig . 1. Light from one of the detectors in the spectrometer enters a photomultiplier tube. The photomultiplier base contains a voltage divider resistor chain, a simple amplifier, and a discriminator . The photomultiplier pulse is amplified and then split into two parts. One part is transported directly to the ADC input of a PHT board. The other copy of the pulse is input to the time-over-threshold discriminator in the base. If the pulse is larger than a remotely controllable threshold, an ECL logic pulse is generated and transported to a latch [5] . If it arrives at the latch within a gate, it is restored to a full ECL level and extended in time slightly past the end of the gate. This ECL pulse, the width of which is proportional to (1 the time-of-flight being measured), is input to the TDC section of the PHT board. In our experiments, we used RG8 50 fl cable to carry the analog pulse for the ADC measurement while lower yuaiity RG58 50 ft coax was sufficient for the time-over-threshold ECL pulse to the latch. When the TDC input to the PHT board is coinci-
by a philosophy to produce systems with capabilities well matched to the measurement requirements of the experimental program. Once reaching that goal, the design is not pushed, often reducing cost and complexity. An essential feature of the resulting design is the simultaneous nature of the pulse area (ADC) and time-of-flight (TDC) measurements. For a given channel, the ADC and TDC measurements were made only if: 1) the pulse height was above a threshold : and 2) there was a coincidence between the TDC signal and the gate for that channel . If either of these conditions were not satisfied, neither the ADC nor the TDC information for that channel was digitized or read out . This suppression of channels with zeroes or nonuseful information is accomplished using discriminators in the photomultiplier bases rather than by discrimination in the ADCs or by pedestal subtraction after digitization . This method allows the use of very low thresholds since the discrimination is performed before the signals have been degraded by transit over long cables . The ADC and TDC measurements in channels with useful information are digitized using shared Wilkenson ramps with modest dynamic range, 128 bins. Only those channels are then read out . The readout proceeds through a priority sequence in which channels are read out in a predetermined order without computer control and in which each measurement is labeled for later identification. Since only channels with information are read out and since the digitized information is contained in a small number of bits, the readout is very fast and places minimal strain on the subsequent elements of a data acquisition system. Because of concerns about the reliability of the measurements at high instantaneous rates, a dynamic
High Voltage
Pulse Height Threshold
Analog P.M . Signal Base
!NfNj_"~ ~
I
Photomultiplier Tube
Digital P.M . Signal
Time of Flight Gate -
External Gate ADC Channell TDC Channel 1 PHT Board
Latch Electronics ECL Time of Flight Pulse Fig. 1 . Sketch of the measurement technique.
E.P. Hartouni et al. / High speed measurement forphotomultiplier signals
dent with an external trigger logic gate, both the TDC and ADC pulses are digitized for that channel . Otherwise, the digitization process does not occur . In what follows, we present details of the PHT board with emphasis on the digitization process and the readout scheme .
163
The PHT system is implemented with ECL10K technology. The ADC and TDC measurements for eight photomultiplier channels are made on one double-sided, 28 cm x 28 cm printed circuit board. See fig. 2. The PHT board digitizes all eight inputs to its ADC, section and all eight inputs to its TDC section simulta-
P '.
Fig. 2. Pictme of the cornimnent side of an eight-channel PHT board.
164
E.P. Hartouni et al. / High speed measurement forphotomultiplier signals
neously . This is done using a separate integration capacitor and comparator for every input and two shared reference capacitors and Wilkenson ramps - one for the ADC section, and one for the TDC section . Power (-5 .2, + 12, and -12 V), data busses, air cooling, and local controllers are provided in crates which can house
up to 128 channels. The cost of the complete PHT system is rather modest, averaging less than $40 US per channel . The digitization process for both the ADC and TDC sections of the PHT board begins with the arrival of a gate from external trigger logic. The gate, typically
GATE
5 ft . mini coax delay
+5
END
RAMP
1K
1%
10H105
50 ihev
10H105
n
ADC UNCLAMP
510
VBB
510 -12
ADC RAMP
+12
50 Pf NPO 100
ADC GATE
CONVERT 1K 1%
51
10HO116
510 1%
51 ECL Time ®f
VBB
Flight Signal
510 1% TDC Encode 50 pf NPO
100 thev
SD306DE
Fig . 3 . Schematic of the TDC measurement circuit . Only one channel is shown for clarity. the pnp transistors are unmarked capacitors are 0 .1 g F.
HOLD COMP
MPS3640 and the
EP. Hartouni et al. / High speed measurement forphotomuhiplier signals
a 25 ns wide ECL level pulse, initiates acceptance and processing of digital time and analog pulse area signals. Signals which arrive outside the gate are not processed . This gate is driven differentially to a 10H116 for each channel . The digital time-of-flight signals, also differentially driven ECL level pulses, are carried to the PHT board over 17-pair twist and flat cables . These signals arrive at the same 1OH116 while the gate is present . Fig . 3 shows the time-to-digital conversion section of the PHT board. The signal output from the 1OH116 is wire AND tied to the 1OH116 gate output (low true). The combination of these signals is logic high unless both are low. The gate-signal combination is used as the input to another buffer on the 1OH116 . The complementary outputs of this buffer are connected to the bases of a transistor differential pair to control integration . The current from a - 5 mA current source is sent through a direct path across one transistor to ground when the input to the buffer is high (no gate or gate with signal). When the input is low (gate without signal), the current is directed across the other transistor of the pair to a 50 pF integrating capacitor . The capacitor charges only when there is a gate without a signal, so the time is measured with respect to the start of the gate. Note that the gate-signal combination also excludes noise outside the gate, since a lew level initiates integration . Channels without a signal integrate for the entire width of the gate yielding the maximum possible voltage on the capacitor . After the capacitor charges, the voltage for each channel is held constant and is used as one input of a comparator. The complementary input is tied to a voltage reference, a single Wilkenson ramp. This is supplied by a similar integration circuit . However, the current source for this circuit supplies only - 0.1 mA, so the integration rate is about 1/50th that of the signal . The output of the comparator is ECL low unless the voltage ramp exceeds the voltage of the integratetii signal . When the two voltages are equal, the output swings high. Since channels that do not contain data integrate for the entire gate, the ramp is designed never to exceed the integrated signal of these channels and the comparator output never goes high (fig. 4). The comparator output is used as the clock input for two quad 10153 latches. The signal input for these latches is a Gray code generated by binary counter circuitry discussed below. The digitization of the pulse area is very similar to that for the time-of-flight. Fig. 5 shows the pulse area digitization circuitry . Each input pulse is supplied to the base of a 918 npn transistor. The emitter of the
transistor is connected to the -12 V supply by an 820 fl resistor. The transistor is therefore a current source depending on the base input voltage (the input analog
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Fig. 4. Comparator logic and suppression of channels with no data. As described in the text, digitization of the integrated data signal begins only when the voltage ramp equals that signal. When the channel does not contain data, that condi tion is not satisfied and no data is stored in the counters for that channel .
signal). The + 12 V supply provides current for this source through a 470 fl resistor tied to the collector of the transistor . The current through the 470 fl resistor is held constant by another current source consisting of a 3640 pnp transistor whose base is held at constant voltage and whose collector is also attached to the resistor. The emitter of the 3640 is tied to a differential pair of 3640s with bases at complementary voltages. The gate is driven differentially to the bases of the 3640s so that at any time only one is on. Other circuitry is present to regulate the current passing through the 3640s. When the gate is present, current is directed to the integrating capacitor. The input . analog signal has the effect of decreasing the current demand through the transistor to which it supplies the base voltage . The larger the input signal, the less current the input signal branch requires. The current diverted from the input branch is passed to the integrating capacitor when a gate is present . Thus, the voltage on the capacitor increases proportionally to the size of the input signal. As with the TDC section, the voltage on the integrating capacitor is compared to a voltage ramp. The ADC voltage ramp 22 pF capacitor is supplied with 0.05 mA during integration and charges at a constant rate of a 0.0022 V/ns. The output of the comparator is used as the clock input to latch the Gray code.
E.P. Hartouni et al. / High speed measurement for photomultiplier signals
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During the absence of the gate, the current is switched to a baseline restoration circuit, effectively providing ac coupling with a 1 Rs time constant, but with large fast signals clipped and not contributing to the average baseline. This strongly rejects ac power noise and removes any baseline shift introduced by a 10 lis ac coupling of the analog signal from the phototube bases . The baseline restoration circuit consists of a TL082 opamp with negative feedback with a 1 p,s integration time, and 1N914B diodes that clip the
4 .3v
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voltage excursions of the unavoidable capacitance integrating the current . Fig . 6 shows the counter and latch circuitry for the PHT board, including the Gray code generation and the readout controls . The Gray code generation uses a 90 MHz clock, driven differentially to the PHT board and the input of a 10116 buffer . The buffer output is the clock input for a pair of 10HO16 binary counters which were reset at the end of the last conversion sequence . At the end of the previous measurement
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Fig. 5 . Schematic of the circuitry to perform the ADC measurement . Only one channel is shown for clarity . The pnp transistors are MPS3640 and the npn transistors are MP591H. The unmarked capacitors are 0 .1 p,F.
E.P. Hartouni et al. / High speed measurement for photomultiplier signals
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TO
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Fig. 6. Counter and latch circuits, including the Gray code generation logic . cycle, a 10131 dual-D flip-flop was used to reset all counters . When a new gate arrives, the flip-flop is clocked and the reset counters begin a new counting sequence. The binary counters are cascaded as inputs to exclusive ORs to produce an 8 bit Gray code with one redundant bit, yielding 128 time bins. The Gray code is latched when the ramp voltage exceeds the
integrating capacitor voltage for the ADC or TDC section . At the end of the counting cycle, the change in state of the most significant counter bit activates the readout phase. In a multiple board system, readout order between boards is determined by an address "priority patch". The address priority patch system allows boards with
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E. P. Hartouni et al. / High speed measurement for photomultiplier signals
lower addresses and data to hold off the readout of boards with higher addresses and data. The presence of data on the board drives the readout for the board. The change in state of the last counter bit of the Gray code generator ends the ramp cycle, allows SD306 FETs to discharge the integrating capacitors, clocks a 10131 dual-D flip-flop for each TDC channel and resets the comparator for the signal-ramp comparison. The D input for the flip-flops is the comparator output for the TDC signal-ramp comparison. If the channel contains data, the Q output on the flip-flop will go high. This output is connected to a 10165 priority encoder in order by increasing TDC channel number . Channels with data are prioritized for readout with channel 0 having highest priority . The 03 output of the encoder is used to signal that data is present . The other three outputs, QO-Q2, of the encoder serve multiple purposes . The outputs are used to define the address of the channel currently being read out . These outputs are also connected to two 10161 binary to 1-8 decoders, one each for the TDC and ADC sections. The outputs of these decoders, when gated by a read clock (supplied externally), are used to gate consecutively the latches which contain the TDC and ADC data. To teduce the number of data output lines, the latch outputs for all eight channels are connected to a data bus . Channels containing data are read into data buffers . Finally the encoder outputs are passed to a 10162 binary to 1-8 decoder which is used to reset the flip-flop of the channel being read out . Each flip-flop is reset as its latch is read into the data buffers. This insures the proper readout sequence. The number of channels containing data determines the duration of the read cycle since no time is wasted reading empty channels . Since the ADC and TDC information for a given nonempty channel are transferred simultaneously, a single channel can be read out in about 25 ns (the read cycle clock period). The complete read cycle duration if all eight channels contain data is about 200 ns. At the completion of the read cycle, the Q3 output of the priority decoder goes low . This generates a logic signal to the system that the board is ready for the next gate. Studies of the performance of the PHT system were made in a test stand [6] constructed for that purpose . In that setup, the behavior of the TDC section was investigated by repeatedly adding 1 ns delays to the TDC input signal . As expected, these studies showed some small nonlinearity of the TDC for times near the beginning of the ramp due to the finite time response of the current switch . This posed no problem for our needs. The time-of-flight measurement range used in the experiment was selected to avoid that portion of the ramp. The linearity of the rest of the ramp was quite adequate. These test stand studies were augmented by calibra-
tions of the 240 channel system measured in place during the experiments. A precision computer controlled pulser was used to generate a start and stop pulse . The time between these pulses could be adjusted in 51 .3 ps steps . The start pulse was used as the external trigger to generate the gate for the PHT boards . The stop signal was used to generate the ECL digital input signal to the TDC section of the PHT board, thereby simulating the signals received by the system in normal operation . All 240 channels were tested . By performing a linear fit to the data from each channel, we obtain an average slope of 0.127 ns/bin . The channel to channel variations in the slopes were quite reasonable. The distribution of slopes for the 240 channels had a half width half maximum of 0.008 ns/bin . The calibration of the pulse area measurement was studied using the test stand. By attenuating an input pulse from a photomultiplier, the pulse area or charge on the integrating capacitor needed to produce a one bin change in the ADC reading could be determined . Typically, a charge of 0.31 pC produces an output change of one bin . Since zero suppression was done using a discriminator in the phototube base, it was possible to make meaningful measurements of very small pulses . The discriminator thresholds were set low enough that good time measurements were made even for the smallest signals - a few mV at the peak and roughly 5 ns wide. For some of the Cherenkov counter photomultiplier tubes in the spectrometer, the pulse height spectra for one photoelectron signals were not separated from the ADC pedestals . Yet, the efficiency of the measurement of such signals was - 100%. The effects of power supply voltage variations were also studied . The PHT board requires three supplies; -5 .2, + 12, -12 V. No effect on the performance or calibration of either the ADC or TDC measurements could be observed when the regulation on these supplies was kept within the following limits : - 5 .2 ± 0.1 ; +12±0 .2, and -12±0.4 V. The PHT board can be modified for other applications easily . For example, it would be straightforward to change the current 8 bit Gray code - 128 bins with redundancy - to 256 bins without redundancy . Also, the Wilkenson ramp circuit can be adjusted to set the size of a single bin for the TDC section . By changing the 39 W resistor from + 12 V to the emitter of the 3640 transistor, the current for the ramp is modified and a new bin width is set . In the same manner, changing the 100 kil resistor for the ADC ramp circuit sets the bin size for that section . We typically allow 10 min for a newly powered PHT board to reach thermal equilibrium. If large variations
in the temperature of the boards are possible, studies of the effect sin the calibration would be advisable .
E.P. Hartouni et al. / High speed measurement for photomultiplier signals The system was used in two experiments in which more that six billion events were recorded. The PHT system proved to be quite reliable . When a channel died, it was almost always due to the failure of a JFET SD306 or one of the 10116s. Once the system was operational, failures were quite infrequent. Acknowledgement We would like to acknowledge the able assistance of the electronics technicians at the University of Massachusetts, Nevis Laboratories, and Fermilab. References [1] BNL E766, Study of fl- Production and Development of On-Line Hardware Processing, Columbia University, University of Massachusetts, Universidad de Guanajuato, Fermilab, and Texas A & M University collaboration, Brookhaven National Laboratories, Upton, Long Island, NY 11973, USA .
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[2] FNAL E690, Study of Hadronic Production and Spectroscopy of Strange, Charm and Bottom Particles at the Tevatron, Columbia University, University of Massachusetts, Universidad de Guanajuato, and Fermilab collaboration, Fermi National Accelerator Laboratory, Batavia, IL 60510, USA. [3] A description of the spectrometer is in preparation. See also: M. Church, 'E-Production in 15-28 GeV NeutronProton Interactions, Columbia University Ph.D. Thesis, Nevis 260 (1986), Nevis Preprint R#1354 ; B. Stern, A Search for Charmed Particles in 15-28 GeV Neutron-Proton Interactions, Columbia University Ph.D. Thesis, Nevis 266 (1988), Nevis Preprint R#1386. [4] In BNL E766 and FNAL E690, both EMI 9954B and Amperex XP2262/H02 photomultipliers were used. [5] The photomultiplier system including the choice of tubes, the design and operation of the bases, the high voltage distribution system, and the latch electronics for this spectrometer will be discussed in a separate paper, in preparation. [6] M.M. Nordberg, Analysis of Time Measurement Resolution of the Brookhaven Experiment 766 PHT System, M.S. Thesis, University of Massachusetts (1988), unpublished .