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High temperature processing of poly-SiC substrates from the vapor phase for wafer-bonding
Surface & Coatings Technology 201 (2006) 4014 – 4020 www.elsevier.com/locate/surfcoat
High temperature processing of poly-SiC substrates from the vapor phase for wafer-bonding G. Chichignoud a,⁎, M. Pons a , E. Blanquet a , D. Chaussende a , M. Anikin a , E. Pernot a , M. Mermoux a , R. Madar a , C. Moisson b , F. Letertre c b
a INPGrenoble, CNRS-ENSEEG, BP 75, 38402 Saint Martin d'Hères, France NOVASiC, Savoie Technolac, BP 267, 73375 Le Bourget du Lac Cedex, France c SOITEC, Parc Technologique des Fontaines 38190 Bernin, France
Available online 19 October 2006
Abstract The transfer by wafer-bonding of single-crystalline SiC thin films to a polycrystalline SiC substrate to obtain a “quasi-wafer” requires high quality polycrystalline substrates with controlled bulk properties (thermal conductivity, electrical resistivity) as well as with very low surface roughness (RMS b 5 nm) and bowing (b 10 μm). Currently, available polycrystalline SiC wafers are processed by sintering or by Chemical Vapor Deposition (CVD). Sintered ceramic wafers are very heterogeneous (mixture of 3C, 6H, 4H and silicon), while CVD ones are of better quality (homogeneous and textured 3C). The aim of this paper is to investigate the fabrication and the properties (bulk and surface) of SiC substrates with large (0.1 to a few mm) grains. To meet these requirements, two high temperature processes (around 2000 °C) for single crystal growth were used: Physical Vapor Transport (PVT) and the recently developed CVD Feed Physical Vapor Transport (CF-PVT). Structural investigations performed on large grain wafers sliced and polished from the grown ingots showed an important influence of the initial seed on the grain size, polytype and crystallographic texture. Chemical and Mechanical Polishing (CMP) of such structures was studied and optimized to obtain low surface roughness. The intra-grain roughness is very low (RMS b 0.5 nm) but a few nanometer of height steps were observed between grains. The relations between bulk properties, surface functionalization and process conditions are discussed. This first seeding step with commercial substrates is necessary for the creation of original substrates which can be used for the fabrication of new substrates. © 2006 Elsevier B.V. All rights reserved. Keywords: Polycrystalline SiC; Vapour deposition; Wafer bonding
1. Introduction The transfer by wafer-bonding of single-crystalline SiC thin films to a polycrystalline SiC substrate to obtain a “quasi-wafer” is an attractive way for lowering the cost of single crystal SiC wafers. The generic nature of the Smart-Cut™ process, based on ion implantation and wafer bonding, is now recognized through successful demonstrations of Si, III–V and SiC thin film transfers (Fig. 1) [1,2]. First, an oxide layer is performed on the single-crystal and a fragile zone below the surface is created by hydrogen implantation (Fig. 1a). Then, the oxidized polycrystalline substrate is pressed against the single-crystal to induce a ⁎ Corresponding author. E-mail addresses: [email protected] (G. Chichignoud), [email protected] (M. Pons), [email protected] (E. Blanquet). 0257-8972/$ - see front matter © 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.surfcoat.2006.08.097
hydrophilic bounding (Fig. 1b). The single-crystal is split by heating (Fig. 1c) and the damaged zone at the surface is removed by polishing (Fig. 1d). The most successful demonstration was made on low crystalline quality single SiC wafers or on CVD polycrystalline SiC [2]. The success of the bonding technique is first based (i) on the quality of the surface, roughness lower than 5 nm (on 5 × 5 μm2) and (ii) on the bow of the wafer, lower than 10 μm. Currently 3CSiC CVD wafers, highly textured and with a fine grained structure (grain size around 3 μm), are used. However, it is difficult to use the Chemical-Mechanical-Polishing (CMP) technique to obtain surfaces with a very low roughness as for single-crystals [3]. In the literature, there is no systematic study of high temperature (2000 °C), high growth rate (N 200 μm/h) processing of polycrystalline SiC by vapor deposition and on the tailoring of bulk properties and on the functionalization of the surface in the nanometer range. In this paper, the evaluation of polishing on large
G. Chichignoud et al. / Surface & Coatings Technology 201 (2006) 4014–4020
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Fig. 1. Schematic representation of thin film transfer technology.
poly-SiC grains processed by the classical PVT [4] and the CFPVT [5] techniques at high growth rate was investigated, with the aim to fabricate low roughness and low bow substrates able to fulfill the constraints of wafer bonding. This first seeding step with commercial substrates is necessary for the creation of original substrates which can be used as seeds for the fabrication of new substrates. In addition, it is well-known that polycrystalline SiC produced by vapor deposition exhibits very high thermal conductivity values (around 300 W m− 1 K− 1) comparable to the best values that metals exhibit and only exceeded by diamond. The control of the electrical resistivity is based on the doping level by nitrogen. When the doping level varies from 1015 to 1018 cm− 3, the wafer is semi-insulating (around 109 Ω cm) or conductive (around 0.1 Ω cm). For this preliminary research study, substrates of about 2″ were processed. In the literature, no papers were found on the properties of standalone polycrystalline SiC substrate with millimeter grain size. The doping level and the resulting electrical resistivity were measured but not controlled. We rather focus our attention on the investigation of different microstructures as a function of growth parameters and on surface quality resulting from the observed microstructure and CMP. 2. Experimental setup and characterization techniques For bulk growth, two well-established growth systems are generally used (Fig. 2). The first one is the Modified-Lely me-
thod [4] based on PVT (Physical Vapor Transport), where sublimation of a SiC powder leads to a gaseous phase which condensates on a colder seed (Fig. 2a). The control of the temperature and concentration field in this closed system remains one of the challenges. The second one is a high temperature CVD technique [6] (Fig. 2b). This growth system is based on vertical geometry, where the precursors, diluted in a carrier gas, are fed upwards, through a heating zone, to a rotating seed crystal holder. Inherent advantages of this technique include the continuous supply of the source material, the relatively economical availability of high purity gases, the control of the C/Si ratio and the ability of pulling the growing crystal. Two concurrent processes appeared over the few last years. The first one, called M-PVT adds to the Modified-Lely method a gas supply into the graphite crucible through a narrow pipe passing inside the SiC powder [7]. This arrangement allows in situ doping of the boule and the possibility to adjust the Si/C ratio by the introduction of Si- and C-containing gas species like silane and propane. The second one, called CF-PVT, is the continuous feeding of the source material by CVD, transfer across a porous material and sublimation [5]. Inherent advantage of this technique is the ability of growing long boules. In this study, particular attention was put on the SiC ingot grown by the PVT process to demonstrate the potential of largegrain poly-SiC. This process consists in the sublimation of a high purity SiC powder (particle size about 100 μm) into a furnace at
Fig. 2. Schematic representation of (a) PVT and (b) HTCVD setups for SiC bulk crystal growth.
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Table 1 Characteristics of the seeds used in this work
Sintered SiC CVD SiC Graphite
Grain size (μm)
Porosity (%)
Polytype
Texture
3.2 3.1 b5
7 – 11
3C, 4H, 6H 3C –
No texture Highly [111] No texture
high temperature and low pressure (around 500 Pa) during 30 h. Reactive gases are condensed directly onto the top of the crucible or onto a polycrystalline seed glued to it. The graphite crucible was heated up to 2000 °C via RF induction. The beginning of the sublimation was controlled by slowly decreasing the pressure. Under these conditions, the average growth rate is around 300 μm h− 1. We chose to investigate three different types of substrates as seeds for the growth: (1) graphite considered as the reference, (2) sintered SiC and (3) dense SiC obtained by CVD. The graphite used for the lid is of high purity. Its surface is as-machined with a high roughness value. Sintered and CVD substrates were polished and characterized by Scanning Electron Microscopy (SEM), X-ray Diffraction and Raman spectroscopy. Their main characteristics are presented in Table 1. Sintered SiC wafers exhibit an average grain size around 3 μm, huge polytype heterogeneity since it presents a mixture of all common SiC polytypes: cubic (3C), hexagonal (4H and mainly 6H). As a consequence, this kind of material is very heterogeneous in terms of crystallographic orientations. Moreover, it has a large surface porosity. However, sintered SiC is a very low cost material. CVD SiC substrates have also a small grain size
(3 μm). X-ray diffraction investigations showed that this material is [111] textured and homogeneous in terms of polytype (cubic form 3C). The rocking curve carried out on this sample exhibits a broad [111] peak with 10° width. Such a result indicates that CVD wafers are textured but not oriented (fiber texture). This material is free of porosities. The boules (Fig. 3a) were sliced either perpendicular (Fig. 3b) or parallel (Fig. 3c and d) to the growing direction in order to characterize the microstructure evolution (porosity, grain size, texture, polytypes) and surface roughness. The thickness of the sliced wafers is typically 700 μm. They were chemically and mechanically polished (CMP) with the same protocol as for hexagonal single crystals [3]. Large-scale surface roughness (Ra and RMS) was studied by optical and mechanical profilometry and small-scale roughness by Atomic Force Microscopy (AFM). They were characterized by several techniques: SEM, Electron Back Scattering Diffraction (EBSD) and Raman spectroscopy (exitation wavelength 514 nm). 3. Experimental results 3.1. Porosity A large amount of porosity is observed in all wafers mainly at grain boundaries, irrespective of distance from the seed (Fig. 4 and Table 2). The occurrence of porosity is well-known in SiC single crystals grown by PVT. It is caused by backside sublimation due to the temperature gradient from the powder source to the seed [8]. These macro-defects are likely to occur as soon as gaseous species can diffuse out of the ingot. Such
Fig. 3. (a) Example of a boule grown by PVT on graphite and its (b) cross-section; sliced wafers (c) with large grains (N1 mm) grown on graphite, (d) grown on a CVD seed with smaller grains (0.1 mm).
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are observed. This result is quite surprising but would show that SiC nucleation on the graphite involves less misorientation than the intrinsic misorientation of this wafer. For the growth on CVD SiC, the structure is highly textured with mainly one orientation along the [0001] axis. Moreover, surface crystallographic pattern tends to reproduce seed crystallographic orientation. Indeed, CVD seed is highly [111] oriented and ingot grown on it presents a [0001] – which corresponds to [111] cubic direction – preferred orientation but disordered hexagons in the surface plane. Raman investigations carried out on these samples indicate that the ingots grown on graphite and sintered SiC substrate contain many polytypes. The high temperature growth conditions generally lead to hexagonal polytypes (6H and 4H) (Fig. 7a) although some inclusions of 3C can be found. For the ingot grown on the CVD substrate, only the 4H polytype is observed (Fig. 7b). Texture and polytype measurements carried out by EBSD technique and Raman spectroscopy indicates that the crystallographic structure of the different wafers sliced from the ingots is strongly dependent on the nature of the seed. Indeed, a low ordered and heterogeneous substrate as the sintered substrate leads to a disordered structure and to a mixture of polytypes. CVD SiC substrates (3C polytype and highly textured) lead to a 4H growth with the [0001] preferred orientation. 3.3. Grain size
Fig. 4. Microstructure evolution along the growing direction (distance from the sintered SiC seed (see Table 2)) (a): 0.7 mm, (b): 1.4 mm, (c): 2.1 mm, (d): 2.8 mm).
porosity may also be induced by low seed stability in these high temperature conditions. Indeed, both seeds were processed at low temperature compared to that of PVT. As a consequence, their fine-grained microstructure is likely to evolve and to coarsen during the first hours of growth. In addition, the sintered substrate is composed of silicon carbide and silicon, which is not stable at 2000 °C.
SEM observations indicate a quick evolution of the grain size from the seed to the end of the ingot independent of the used seed (Fig. 3b). Grain size has been evaluated by image analysis. It appears that the grain size increases from 0.5 mm at 0.7 mm from the seed to 2.4 mm at the end of the boule (Table 3). It is expected that microstructure coarsening leads to high internal stresses which makes the material not suitable both its bulk properties and surface polishing. Moreover, not only the grain size is modified during the growth but the general shape of the grain evolves from fine needles at the bottom of the boule to large and smooth grains. 3.4. Polishing
3.2. Polytype formation and texture EBSD measurements performed on ingots grown on sintered SiC indicate that no texture has been induced since no preferential growth of one family of planes is observed (Fig. 5). Even at several millimeters from the seed, many crystallographic families are still present. However, pole figures exhibit an evolution of the crystal orientation along the growing direction since the slice extracted at 2 mm from the seed is less disordered and closer to [0001] direction than slices closer to the seed. The influence of the seed on texture is clearly shown on the pole figures (Fig. 6). The wafers sliced at the same distance from the seed but grown on different substrates exhibit very different crystallographic orientations. For the growth on graphite, many ¯0]. For the growth orientations are present, from [0001] to [101 on sintered SiC, the structure is more disordered than that grown ¯0] and [21 ¯ ¯10] on graphite. All orientations between [0001], [101
All the samples were chemically and mechanically polished (CMP). Mappings on large areas indicate that inside the grains, CMP is efficient whatever the substrate used for growth experiments. The average roughness Ra is around 2 nm and the intra-grain RMS values are about 3 Å (on 5 × 5 μm areas). However, all the grains are not all polished at the same rate, which leads to steps between grains. For example, for samples grown on graphite and sintered SiC, two adjacent grains can be shifted by several hundred nanometers. In addition, grains boundaries exhibit a wavelike shape, with a difference between
Table 2 Porosity evolution along the growth direction (growth on sintered SiC) Distance from the seed (mm) Porosity (%)
0.7 1.2
1.4 0.5
2.1 0.3
2.8 0.3
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Fig. 5. Pole figures measured at different distance from the sintered SiC seed (see Table 2): (a): 0.7 mm, (b): 2.1 mm and (c): 2.8 mm.
higher and lower levels larger than 150 nm. The origin of wavelike patterns or hills at grain boundaries is not understood yet. For the wafers sliced from the boule grown on the CVD substrate, the steps between grains are less than 50 nm. Such a result confirms the interest of texture and polytype homogeneity for the CMP procedure. CMP is well suited to reveal the atomic step structure in single crystals and to suppress the cold rolled zone at the surface. However, for heterogeneous substrates, it failed to fulfill the requirements of surface roughness for thin film transfer. A new mechanical polishing procedure is needed to minimize the steps between grains. By a trial and error method on different polishing plates and pastes, a roughness lower than 10 nm was reached. 4. Discussion Generally vapor deposition at high temperature begins by nucleation of individual crystallites at random spots on the substrate, followed by competitive growth as the crystallites enlarge and merge, so that a strong columnar structure develops with the long axis of the columnar grains normally oriented to the substrate (Fig. 3b). The average in-plane dimensions of the grains increase more or less linearly with the distance to the substrate. With such a microstructure, one would expect transport properties such as thermal and electrical conductivity to be anisotropic and thickness-dependent [9]. But, the polycrystalline substrate is mainly used for thermal management of the device. It ensures long-term reliability and enables the device to maintain its maximum output power. The size of the grain is sufficient to ensure an average thermal conductivity of around 300 W m− 1 K− 1 at room temperature [10]. The average electrical resistivity can be managed by the purification of the source powder to avoid nitrogen incorporation during growth. The measured value, around 1 Ω cm, corresponds to the N-doping level, 1018 cm− 3, measured in 4H single crystal grown in the same conditions. These polycrystalline substrates are conductive and can be used for the fabrication of Schottky diodes. For RF applications, the
ideal substrate must be electrically insulating with as little RF loss as possible. The evolution of grain coarsening and of the texture was analyzed with well-known models describing crystal growth from the vapor phase such as the Van der Drift model [11]. The competition between various growth mechanisms was put in evidence. The evolutionary selection model explains how even randomly oriented nucleation can lead to preferential orientation. The essence of this model is that a crystallographic plane that grows the fastest envelops the other planes and determines the orientation. In vapor growth at high temperature, the deposition rate is fast and consequently, the adsorption of gaseous species in the different planes and the large surface diffusion length lead to a random orientation. In the experiments, no texture selection seems to occur during the growth, while according to the Van der Drift model a preferential crystallographic orientation is likely to emerge. Such a result indicates that the main assumption of this model, namely that the final texture corresponds to one fastest adsorbing plane, is not valid in our conditions. As a consequence, the final texture and surface roughness of polycrystalline SiC strongly depend on the seed. It appears that the surface roughness after CMP is strongly dependent on the nature of the substrate, since local processing conditions are likely to be similar for each experiment. That selective behavior can be associated to the nature of SiC polytypes [3], grain orientation, grain shape and size and consequently grain boundary density internal stress. From these results, we can conclude that the best samples came from the CVD seeds because it allows keeping the same polytype and orientation. However, the grain size is smaller than in samples grown on graphite (Fig. 7). This result is not still well understood. At the present stage of this research program, a combination between CMP and mechanical polishing gives the best roughness results which are near the requirements of wafer bonding. To further decrease the roughness, wafers sliced from the ingot grown on CVD SiC seeds were used as new seeds. The
Fig. 6. Pole figures obtained on ingots grown on (a) graphite, (b) sintered SiC and (c) CVD SiC.
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Fig. 7. Superposition of EBSD and Raman spectroscopy mappings for a wafer grown (a) on sintered SiC and (b) on CVD SiC.
growth of larger grains (N 1 cm) and a polishing procedure was established to ensure the reproducibility of the surface roughness. The best results are a bow of about 3 μm and an RMS lower than 10 nm. 5. Conclusion Ingots were grown from the vapor phase at high temperature on two different seeds and compared to growth on graphite. Original substrates with large grains were processed. The crystallographic properties of the boules were investigated by Raman and EBSD. At the high temperature used for the growth,
it appeared that the selection model is not valid. The texture and polytype nature were strongly dependant on the used seed, a heterogeneous seed leading to the absence of texture and polytype heterogeneity. Due to the different polishing rate for each crystallographic orientation, the polishing ability can be directly related to the surface homogeneity. To fulfill the strict wafer bonding conditions, the SiC CVD seed was found to be the best. This study was made on commercially available seeds and on their selection to process original substrates with tailor bulk and surface properties. They can be used for the next fabrication of substrates for wafer bonding. Acknowledgements
Table 3 Grain size evolution along the growth direction (growth on sintered SiC) Distance from the seed (mm) Average grain area (mm2) Average dimension (mm)
0.7 0.086 0.5
1.4 0.98 1.8
2.1 1.8 2.4
2.8 1.9 2.4
This work was funded by the Région Rhône-Alpes and Novasic Company. The authors would like to thank SOITEC and Picogiga companies (Robert Langer and Bruce Faure) for providing CVD substrates and doing electrical characterizations.
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References [1] L. Di Cioccio, E. Jalaguier, F. Letertre, Phys. Status Solidi, A 202 (2005) 509. [2] F. Letertre, N. Daval, F. Templier, E. Bano, D. Planson, L. Di Cioccio, E. Jalaguier, T. Billon, R. Madar, J.P. Chante, et al., Mat. Sci. Forum 433–436 (2003) 813. [3] S. Monnoye, D. Turover, in: W.J. Choyke, H. Matsunami, G. Pensl (Eds.), Recent Major Advances in Silicon Carbide, Springer, 2004, p. 699. [4] H. McD. Hobgood, M.F. Brady, M.R. Calus, J.R. Jeny, R.T. Leonard, D.P. Malta, St.G. Mueller, A.R. Powell, V.F. Tsvetkov, R.C. Glass, C.H. Carter, Mat. Sci. Forum 457–460 (2004) 3.
[5] D. Chaussende, F. Baillet, L. Charpentier, E. Pernot, M. Pons, R. Madar, J. Electrochem. 150 (2003) G653. [6] A. Ellison, B. Magnusson, B. Sundqvist, G. Pozina, J.P. Bergman, E. Janzen, Mat. Sci. Forum 457–460 (2004) 9. [7] T.L. Straubinger, M. Bikermann, R. Weingärtner, P.J. Wellmann, A. Winnacker, J. Cryst. Growth 240 (2002) 117. [8] K. Chourou, M. Anikin, J.M. Bluet, J.M. Dedulle, R. Madar, M. Pons, E. Blanquet, C. Bernard, P. Grosse, C. Faure, G. Basset, Y. Grange, Mater. Sci. Eng., B 61–62 (1999) 82. [9] J.E. Graebner, S. Jin, JOM 6 (1998) 52. [10] J.S. Goela, N.E. Brese, M.A. Pickering, J.E. Graebner, JOM 6 (2001) 458. [11] A. Van der Drift, Philips Res. Rep. 22 (1967) 267.
High temperature processing of poly-SiC substrates from the vapor phase for wafer-bonding G. Chichignoud a,⁎, M. Pons a , E. Blanquet a , D. Chaussende a , M. Anikin a , E. Pernot a , M. Mermoux a , R. Madar a , C. Moisson b , F. Letertre c b
a INPGrenoble, CNRS-ENSEEG, BP 75, 38402 Saint Martin d'Hères, France NOVASiC, Savoie Technolac, BP 267, 73375 Le Bourget du Lac Cedex, France c SOITEC, Parc Technologique des Fontaines 38190 Bernin, France
Available online 19 October 2006
Abstract The transfer by wafer-bonding of single-crystalline SiC thin films to a polycrystalline SiC substrate to obtain a “quasi-wafer” requires high quality polycrystalline substrates with controlled bulk properties (thermal conductivity, electrical resistivity) as well as with very low surface roughness (RMS b 5 nm) and bowing (b 10 μm). Currently, available polycrystalline SiC wafers are processed by sintering or by Chemical Vapor Deposition (CVD). Sintered ceramic wafers are very heterogeneous (mixture of 3C, 6H, 4H and silicon), while CVD ones are of better quality (homogeneous and textured 3C). The aim of this paper is to investigate the fabrication and the properties (bulk and surface) of SiC substrates with large (0.1 to a few mm) grains. To meet these requirements, two high temperature processes (around 2000 °C) for single crystal growth were used: Physical Vapor Transport (PVT) and the recently developed CVD Feed Physical Vapor Transport (CF-PVT). Structural investigations performed on large grain wafers sliced and polished from the grown ingots showed an important influence of the initial seed on the grain size, polytype and crystallographic texture. Chemical and Mechanical Polishing (CMP) of such structures was studied and optimized to obtain low surface roughness. The intra-grain roughness is very low (RMS b 0.5 nm) but a few nanometer of height steps were observed between grains. The relations between bulk properties, surface functionalization and process conditions are discussed. This first seeding step with commercial substrates is necessary for the creation of original substrates which can be used for the fabrication of new substrates. © 2006 Elsevier B.V. All rights reserved. Keywords: Polycrystalline SiC; Vapour deposition; Wafer bonding
1. Introduction The transfer by wafer-bonding of single-crystalline SiC thin films to a polycrystalline SiC substrate to obtain a “quasi-wafer” is an attractive way for lowering the cost of single crystal SiC wafers. The generic nature of the Smart-Cut™ process, based on ion implantation and wafer bonding, is now recognized through successful demonstrations of Si, III–V and SiC thin film transfers (Fig. 1) [1,2]. First, an oxide layer is performed on the single-crystal and a fragile zone below the surface is created by hydrogen implantation (Fig. 1a). Then, the oxidized polycrystalline substrate is pressed against the single-crystal to induce a ⁎ Corresponding author. E-mail addresses: [email protected] (G. Chichignoud), [email protected] (M. Pons), [email protected] (E. Blanquet). 0257-8972/$ - see front matter © 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.surfcoat.2006.08.097
hydrophilic bounding (Fig. 1b). The single-crystal is split by heating (Fig. 1c) and the damaged zone at the surface is removed by polishing (Fig. 1d). The most successful demonstration was made on low crystalline quality single SiC wafers or on CVD polycrystalline SiC [2]. The success of the bonding technique is first based (i) on the quality of the surface, roughness lower than 5 nm (on 5 × 5 μm2) and (ii) on the bow of the wafer, lower than 10 μm. Currently 3CSiC CVD wafers, highly textured and with a fine grained structure (grain size around 3 μm), are used. However, it is difficult to use the Chemical-Mechanical-Polishing (CMP) technique to obtain surfaces with a very low roughness as for single-crystals [3]. In the literature, there is no systematic study of high temperature (2000 °C), high growth rate (N 200 μm/h) processing of polycrystalline SiC by vapor deposition and on the tailoring of bulk properties and on the functionalization of the surface in the nanometer range. In this paper, the evaluation of polishing on large
G. Chichignoud et al. / Surface & Coatings Technology 201 (2006) 4014–4020
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Fig. 1. Schematic representation of thin film transfer technology.
poly-SiC grains processed by the classical PVT [4] and the CFPVT [5] techniques at high growth rate was investigated, with the aim to fabricate low roughness and low bow substrates able to fulfill the constraints of wafer bonding. This first seeding step with commercial substrates is necessary for the creation of original substrates which can be used as seeds for the fabrication of new substrates. In addition, it is well-known that polycrystalline SiC produced by vapor deposition exhibits very high thermal conductivity values (around 300 W m− 1 K− 1) comparable to the best values that metals exhibit and only exceeded by diamond. The control of the electrical resistivity is based on the doping level by nitrogen. When the doping level varies from 1015 to 1018 cm− 3, the wafer is semi-insulating (around 109 Ω cm) or conductive (around 0.1 Ω cm). For this preliminary research study, substrates of about 2″ were processed. In the literature, no papers were found on the properties of standalone polycrystalline SiC substrate with millimeter grain size. The doping level and the resulting electrical resistivity were measured but not controlled. We rather focus our attention on the investigation of different microstructures as a function of growth parameters and on surface quality resulting from the observed microstructure and CMP. 2. Experimental setup and characterization techniques For bulk growth, two well-established growth systems are generally used (Fig. 2). The first one is the Modified-Lely me-
thod [4] based on PVT (Physical Vapor Transport), where sublimation of a SiC powder leads to a gaseous phase which condensates on a colder seed (Fig. 2a). The control of the temperature and concentration field in this closed system remains one of the challenges. The second one is a high temperature CVD technique [6] (Fig. 2b). This growth system is based on vertical geometry, where the precursors, diluted in a carrier gas, are fed upwards, through a heating zone, to a rotating seed crystal holder. Inherent advantages of this technique include the continuous supply of the source material, the relatively economical availability of high purity gases, the control of the C/Si ratio and the ability of pulling the growing crystal. Two concurrent processes appeared over the few last years. The first one, called M-PVT adds to the Modified-Lely method a gas supply into the graphite crucible through a narrow pipe passing inside the SiC powder [7]. This arrangement allows in situ doping of the boule and the possibility to adjust the Si/C ratio by the introduction of Si- and C-containing gas species like silane and propane. The second one, called CF-PVT, is the continuous feeding of the source material by CVD, transfer across a porous material and sublimation [5]. Inherent advantage of this technique is the ability of growing long boules. In this study, particular attention was put on the SiC ingot grown by the PVT process to demonstrate the potential of largegrain poly-SiC. This process consists in the sublimation of a high purity SiC powder (particle size about 100 μm) into a furnace at
Fig. 2. Schematic representation of (a) PVT and (b) HTCVD setups for SiC bulk crystal growth.
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Table 1 Characteristics of the seeds used in this work
Sintered SiC CVD SiC Graphite
Grain size (μm)
Porosity (%)
Polytype
Texture
3.2 3.1 b5
7 – 11
3C, 4H, 6H 3C –
No texture Highly [111] No texture
high temperature and low pressure (around 500 Pa) during 30 h. Reactive gases are condensed directly onto the top of the crucible or onto a polycrystalline seed glued to it. The graphite crucible was heated up to 2000 °C via RF induction. The beginning of the sublimation was controlled by slowly decreasing the pressure. Under these conditions, the average growth rate is around 300 μm h− 1. We chose to investigate three different types of substrates as seeds for the growth: (1) graphite considered as the reference, (2) sintered SiC and (3) dense SiC obtained by CVD. The graphite used for the lid is of high purity. Its surface is as-machined with a high roughness value. Sintered and CVD substrates were polished and characterized by Scanning Electron Microscopy (SEM), X-ray Diffraction and Raman spectroscopy. Their main characteristics are presented in Table 1. Sintered SiC wafers exhibit an average grain size around 3 μm, huge polytype heterogeneity since it presents a mixture of all common SiC polytypes: cubic (3C), hexagonal (4H and mainly 6H). As a consequence, this kind of material is very heterogeneous in terms of crystallographic orientations. Moreover, it has a large surface porosity. However, sintered SiC is a very low cost material. CVD SiC substrates have also a small grain size
(3 μm). X-ray diffraction investigations showed that this material is [111] textured and homogeneous in terms of polytype (cubic form 3C). The rocking curve carried out on this sample exhibits a broad [111] peak with 10° width. Such a result indicates that CVD wafers are textured but not oriented (fiber texture). This material is free of porosities. The boules (Fig. 3a) were sliced either perpendicular (Fig. 3b) or parallel (Fig. 3c and d) to the growing direction in order to characterize the microstructure evolution (porosity, grain size, texture, polytypes) and surface roughness. The thickness of the sliced wafers is typically 700 μm. They were chemically and mechanically polished (CMP) with the same protocol as for hexagonal single crystals [3]. Large-scale surface roughness (Ra and RMS) was studied by optical and mechanical profilometry and small-scale roughness by Atomic Force Microscopy (AFM). They were characterized by several techniques: SEM, Electron Back Scattering Diffraction (EBSD) and Raman spectroscopy (exitation wavelength 514 nm). 3. Experimental results 3.1. Porosity A large amount of porosity is observed in all wafers mainly at grain boundaries, irrespective of distance from the seed (Fig. 4 and Table 2). The occurrence of porosity is well-known in SiC single crystals grown by PVT. It is caused by backside sublimation due to the temperature gradient from the powder source to the seed [8]. These macro-defects are likely to occur as soon as gaseous species can diffuse out of the ingot. Such
Fig. 3. (a) Example of a boule grown by PVT on graphite and its (b) cross-section; sliced wafers (c) with large grains (N1 mm) grown on graphite, (d) grown on a CVD seed with smaller grains (0.1 mm).
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are observed. This result is quite surprising but would show that SiC nucleation on the graphite involves less misorientation than the intrinsic misorientation of this wafer. For the growth on CVD SiC, the structure is highly textured with mainly one orientation along the [0001] axis. Moreover, surface crystallographic pattern tends to reproduce seed crystallographic orientation. Indeed, CVD seed is highly [111] oriented and ingot grown on it presents a [0001] – which corresponds to [111] cubic direction – preferred orientation but disordered hexagons in the surface plane. Raman investigations carried out on these samples indicate that the ingots grown on graphite and sintered SiC substrate contain many polytypes. The high temperature growth conditions generally lead to hexagonal polytypes (6H and 4H) (Fig. 7a) although some inclusions of 3C can be found. For the ingot grown on the CVD substrate, only the 4H polytype is observed (Fig. 7b). Texture and polytype measurements carried out by EBSD technique and Raman spectroscopy indicates that the crystallographic structure of the different wafers sliced from the ingots is strongly dependent on the nature of the seed. Indeed, a low ordered and heterogeneous substrate as the sintered substrate leads to a disordered structure and to a mixture of polytypes. CVD SiC substrates (3C polytype and highly textured) lead to a 4H growth with the [0001] preferred orientation. 3.3. Grain size
Fig. 4. Microstructure evolution along the growing direction (distance from the sintered SiC seed (see Table 2)) (a): 0.7 mm, (b): 1.4 mm, (c): 2.1 mm, (d): 2.8 mm).
porosity may also be induced by low seed stability in these high temperature conditions. Indeed, both seeds were processed at low temperature compared to that of PVT. As a consequence, their fine-grained microstructure is likely to evolve and to coarsen during the first hours of growth. In addition, the sintered substrate is composed of silicon carbide and silicon, which is not stable at 2000 °C.
SEM observations indicate a quick evolution of the grain size from the seed to the end of the ingot independent of the used seed (Fig. 3b). Grain size has been evaluated by image analysis. It appears that the grain size increases from 0.5 mm at 0.7 mm from the seed to 2.4 mm at the end of the boule (Table 3). It is expected that microstructure coarsening leads to high internal stresses which makes the material not suitable both its bulk properties and surface polishing. Moreover, not only the grain size is modified during the growth but the general shape of the grain evolves from fine needles at the bottom of the boule to large and smooth grains. 3.4. Polishing
3.2. Polytype formation and texture EBSD measurements performed on ingots grown on sintered SiC indicate that no texture has been induced since no preferential growth of one family of planes is observed (Fig. 5). Even at several millimeters from the seed, many crystallographic families are still present. However, pole figures exhibit an evolution of the crystal orientation along the growing direction since the slice extracted at 2 mm from the seed is less disordered and closer to [0001] direction than slices closer to the seed. The influence of the seed on texture is clearly shown on the pole figures (Fig. 6). The wafers sliced at the same distance from the seed but grown on different substrates exhibit very different crystallographic orientations. For the growth on graphite, many ¯0]. For the growth orientations are present, from [0001] to [101 on sintered SiC, the structure is more disordered than that grown ¯0] and [21 ¯ ¯10] on graphite. All orientations between [0001], [101
All the samples were chemically and mechanically polished (CMP). Mappings on large areas indicate that inside the grains, CMP is efficient whatever the substrate used for growth experiments. The average roughness Ra is around 2 nm and the intra-grain RMS values are about 3 Å (on 5 × 5 μm areas). However, all the grains are not all polished at the same rate, which leads to steps between grains. For example, for samples grown on graphite and sintered SiC, two adjacent grains can be shifted by several hundred nanometers. In addition, grains boundaries exhibit a wavelike shape, with a difference between
Table 2 Porosity evolution along the growth direction (growth on sintered SiC) Distance from the seed (mm) Porosity (%)
0.7 1.2
1.4 0.5
2.1 0.3
2.8 0.3
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Fig. 5. Pole figures measured at different distance from the sintered SiC seed (see Table 2): (a): 0.7 mm, (b): 2.1 mm and (c): 2.8 mm.
higher and lower levels larger than 150 nm. The origin of wavelike patterns or hills at grain boundaries is not understood yet. For the wafers sliced from the boule grown on the CVD substrate, the steps between grains are less than 50 nm. Such a result confirms the interest of texture and polytype homogeneity for the CMP procedure. CMP is well suited to reveal the atomic step structure in single crystals and to suppress the cold rolled zone at the surface. However, for heterogeneous substrates, it failed to fulfill the requirements of surface roughness for thin film transfer. A new mechanical polishing procedure is needed to minimize the steps between grains. By a trial and error method on different polishing plates and pastes, a roughness lower than 10 nm was reached. 4. Discussion Generally vapor deposition at high temperature begins by nucleation of individual crystallites at random spots on the substrate, followed by competitive growth as the crystallites enlarge and merge, so that a strong columnar structure develops with the long axis of the columnar grains normally oriented to the substrate (Fig. 3b). The average in-plane dimensions of the grains increase more or less linearly with the distance to the substrate. With such a microstructure, one would expect transport properties such as thermal and electrical conductivity to be anisotropic and thickness-dependent [9]. But, the polycrystalline substrate is mainly used for thermal management of the device. It ensures long-term reliability and enables the device to maintain its maximum output power. The size of the grain is sufficient to ensure an average thermal conductivity of around 300 W m− 1 K− 1 at room temperature [10]. The average electrical resistivity can be managed by the purification of the source powder to avoid nitrogen incorporation during growth. The measured value, around 1 Ω cm, corresponds to the N-doping level, 1018 cm− 3, measured in 4H single crystal grown in the same conditions. These polycrystalline substrates are conductive and can be used for the fabrication of Schottky diodes. For RF applications, the
ideal substrate must be electrically insulating with as little RF loss as possible. The evolution of grain coarsening and of the texture was analyzed with well-known models describing crystal growth from the vapor phase such as the Van der Drift model [11]. The competition between various growth mechanisms was put in evidence. The evolutionary selection model explains how even randomly oriented nucleation can lead to preferential orientation. The essence of this model is that a crystallographic plane that grows the fastest envelops the other planes and determines the orientation. In vapor growth at high temperature, the deposition rate is fast and consequently, the adsorption of gaseous species in the different planes and the large surface diffusion length lead to a random orientation. In the experiments, no texture selection seems to occur during the growth, while according to the Van der Drift model a preferential crystallographic orientation is likely to emerge. Such a result indicates that the main assumption of this model, namely that the final texture corresponds to one fastest adsorbing plane, is not valid in our conditions. As a consequence, the final texture and surface roughness of polycrystalline SiC strongly depend on the seed. It appears that the surface roughness after CMP is strongly dependent on the nature of the substrate, since local processing conditions are likely to be similar for each experiment. That selective behavior can be associated to the nature of SiC polytypes [3], grain orientation, grain shape and size and consequently grain boundary density internal stress. From these results, we can conclude that the best samples came from the CVD seeds because it allows keeping the same polytype and orientation. However, the grain size is smaller than in samples grown on graphite (Fig. 7). This result is not still well understood. At the present stage of this research program, a combination between CMP and mechanical polishing gives the best roughness results which are near the requirements of wafer bonding. To further decrease the roughness, wafers sliced from the ingot grown on CVD SiC seeds were used as new seeds. The
Fig. 6. Pole figures obtained on ingots grown on (a) graphite, (b) sintered SiC and (c) CVD SiC.
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Fig. 7. Superposition of EBSD and Raman spectroscopy mappings for a wafer grown (a) on sintered SiC and (b) on CVD SiC.
growth of larger grains (N 1 cm) and a polishing procedure was established to ensure the reproducibility of the surface roughness. The best results are a bow of about 3 μm and an RMS lower than 10 nm. 5. Conclusion Ingots were grown from the vapor phase at high temperature on two different seeds and compared to growth on graphite. Original substrates with large grains were processed. The crystallographic properties of the boules were investigated by Raman and EBSD. At the high temperature used for the growth,
it appeared that the selection model is not valid. The texture and polytype nature were strongly dependant on the used seed, a heterogeneous seed leading to the absence of texture and polytype heterogeneity. Due to the different polishing rate for each crystallographic orientation, the polishing ability can be directly related to the surface homogeneity. To fulfill the strict wafer bonding conditions, the SiC CVD seed was found to be the best. This study was made on commercially available seeds and on their selection to process original substrates with tailor bulk and surface properties. They can be used for the next fabrication of substrates for wafer bonding. Acknowledgements
Table 3 Grain size evolution along the growth direction (growth on sintered SiC) Distance from the seed (mm) Average grain area (mm2) Average dimension (mm)
0.7 0.086 0.5
1.4 0.98 1.8
2.1 1.8 2.4
2.8 1.9 2.4
This work was funded by the Région Rhône-Alpes and Novasic Company. The authors would like to thank SOITEC and Picogiga companies (Robert Langer and Bruce Faure) for providing CVD substrates and doing electrical characterizations.
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