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High-voltage NMOS design in fully implanted twin-well CMOS
Microelectronics Journal 35 (2004) 723–730 www.elsevier.com/locate/mejo
High-voltage NMOS design in fully implanted twin-well CMOS P.M. Santos*, H. Quaresma, A.P. Silva, M. Lanc¸a Instituto de Telecomunicac¸o˜es/Instituto Superior Te´cnico, Av. Rovisco Pais, 1049-001 Lisboa, Portugal Received 1 April 2004; revised 24 May 2004; accepted 1 June 2004 Available online 28 July 2004
Abstract This paper discusses the viability of using last generation CMOS technology to develop a High-Voltage NMOS library for smart power integration. Breakdown voltages of the order of 30 V can be achieved for Gate-Shifted extended drain NMOS devices fabricated in a fully implanted, twin-well, 0.5 mm CMOS core process, aimed for mixed-mode applications, without process modification or any additional mask. The trade-offs of using high overdrive voltages, above nominal supply, to reduce On-resistance is also discussed. According to experiments on prototypes, devices under excessive overdrive voltages over long periods revealed threshold voltage and transconductance variations, due to gate oxide degradation. q 2004 Elsevier Ltd. All rights reserved. Keywords: CMOS compatible; Drain engineering; Power integrated circuits; Reliability; Smart power
1. Introduction Smart power is also trying to follow the Roadmap with high-resolution lithography, answering to the increased demand in complexity and integration density, mainly in portable applications [1,2]. Consequently, projecting smart power ICs is becoming more expensive and inaccessible for fabless design houses. According to this scenario, several foundries developed commercially available High-Voltage CMOS processes derived from the CMOS core, with some additional steps and mask layers to perform the high voltage device, usually an LDMOS. Another approach for smart power integration for low power applications involves the extended drain technique [3] to perform High-Voltage (HV) NMOS in a digital or mixed-mode core CMOS process with no extra processing. Previous works [4,5] indicated another fully CMOS compatible drain engineering technique—the gate-shifting—useful to increase extended drain transistors breakdown voltages fabricated in CMOS processes with long term diffused wells. As mask lithography is still shrinking to pursue Moore’s law, CMOS process steps were also adapted to fulfil minimum feature lengths. In this way, wells are no longer * Corresponding author. Fax: þ 35-12-1841-8472. E-mail address: [email protected] (P.M. Santos). 0026-2692/$ - see front matter q 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2004.06.002
diffused but fully implanted at high energies in deep submicron CMOS. To prove the viability of last generation CMOS for smart power applications, this paper presents the criteria to project and design HV NMOS transistors in a deep submicron CMOS technology, commercially available for digital and mixed-mode ASICs. In particular, this work explains the unconventional required mask manipulation to design HV gate-shifted lightly-doped drain (GS-LDD) transistors. Experimental results will be presented and devices performances compared. Finally, the trade-offs of using voltages well above the nominal process supply, especially high overdrive voltages in the thin gate oxide, is discussed in terms of On-resistance and long term reliability.
2. The 0.5 mm CMOS process The High voltage NMOS transistors were projected and ‘full-custom’ designed to be fabricated in a mixedmode 0.5 mm, single level poly, triple level metal, and twin-tub CMOS process. The starting material is a , 100 . p-substrate with a 10 – 13 Vcm epitaxial layer. The process uses high-energy ion implantation to obtain the twin retrograde wells, with metallurgical junctions around 1 mm deep. Typical oxide thickness is 10 nm with
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a dielectric breakdown around 11 V. The standard low-voltage NMOS and PMOS transistors are designed for a nominal 3.3 V supply operation, with typical threshold voltages of the order of 0.6/2 0.6 V and breakdown voltages above 7 V. According to the process documentation, these standard cells present a 25 years lifetime with less then 10% transconductance ðgm Þ degradation and less than 100 mV threshold voltage ðVTH Þ increase, when operating continuously under nominal supply voltage in digital applications. Operation at higher voltages reduces devices lifetime.
The HV LDD channel is formed by two implants: the retrograde p-well implant, usually automatically defined by the complement of n-well mask (not shown in Fig. 1); and the corresponding threshold implant adjustment, mainly defined by the n þ layer, like in the low voltage NMOS standard cell. Devices cross-section optimisation, namely channel length and drain drift path, was carried out with the aid of 2D simulations. It was found that the channel length of 3 mm, defined by the minimum allowable design rule for two adjacent n-wells, was enough to avoid punchthrough.
4. Breakdown voltage improvement 3. High voltage NMOS in core CMOS The development of a symmetric High-Voltage extended drain or LDD NMOS transistor in this process can be easily obtained with a layout mask arrangement analogous to the indicated in Fig. 1(a). In this symmetric (high-side) layout, n-well mask is defined in both drain and source regions to allow lightly doped drift paths between the channel and drain/source contacts. Only one layout rule is not verified with the mask arrangement of Fig. 1. Other possible layouts could be valid, depending on foundry available layers, design rules check (DRC) tool and automatic mask generation criteria. As p-well mask is automatically generated as the complement of n-well, channel active area region below polysilicon gate is formed by the retrograde p-well, which, in fact, is the process substrate for the low voltage standard NMOS. Transistor gate is aligned with the highly resistive n-well implant of the drain and source. This arrangement reduces the electric field stress at the semiconductor surface when the device is blocking a drain voltage (VDS . VGS ¼ 0 V). Due to the presence of the n-well path, critical electric field for Silicon, responsible for electron-hole pair generation by impact ionisation, is reached at drain voltages well above the standard cell NMOS breakdown voltage (7 V). For the asymmetric (low-side) HV LDD device, the source-side mask layout is similar to the NMOS standard cell design (Fig. 1(b)).
Breakdown voltage improvement of HV extended drain NMOS devices using core CMOS processes is not an easy task. In fact, when compared with BCD, BiCMOS or dedicated smart power technologies, CMOS is the less complex of all, due to the reduced number of masks and specific implant regions. On the other hand, the fully CMOS compatible gate-shifting technique was found efficient to perform breakdown voltage increase in GS-LDD devices fabricated in diffused wells CMOS processes [4,5]. However, the implementation of GS-LDD devices in a twin and fully implanted wells CMOS process is not so obvious. The implementation of the gate-shifting technique in this scenario must take into account the following aspects: (1) implanted p and n wells junction at device Si – SiO2 interface is defined by the end of n-well mask, as p-well is usually automatically generated as the complement of this layer; (2) with the gate-shifting technique, the drain side gate edge should be shifted from n-well edge by an LGS length, in order to lower electric field at off-state, resulting in breakdown voltage improvement [4]. As can be seen in Fig. 2(a), this procedure locates the gate edge in alignment with a portion of the p-well implant causing channel interruption (Fig. 2(a)). In this paper, a fully CMOS compatible new layout strategy is suggested, which is based on the p-well inhibition near the wells junction and beneath the gate edge,
Fig. 1. Cross section and mask arrangement of fully CMOS compatible extended drain NMOS High-Voltage structures: (a) symmetric HV LDD NMOS with inclusion of the lightly doped n-well path in both drain and source; (b) detail of the source side for an asymmetric HV LDD NMOS.
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Fig. 2. Application of the gate-shifting technique in a fully implanted twin well process: (a) incorrect mask arrangement, which causes channel interruption; (b) proposed layout arrangement to avoid channel interruption.
like depicted in Fig. 2(b), to perform gate-shifting. This p-well retraction is achieved with mask manipulation, resorting to the layer nogen, which acts as an inhibitor to the foundry automatic mask generation procedure. Thus, p-well will not be implanted in nogen regions allowing n-well expansion to the channel. As the intersection of poly and active-area mask edge is located in the middle of the region defined by nogen, gate edge will be positioned in alignment with the low concentrated n-well lateral scattering path, avoiding channel interruption and improving breakdown. The nlddprot mask over the entire cell avoids implants of shallow lightly doped regions used for hot carrier injection reduction in low voltage standard NMOS, which are higher concentrated than n-well surface. nldd and p-well masks must also be drawn coincident to the nogen layer, since they are negative masks. The complete inhibition of p-well with nogen is not recommended since it will also inhibit
n þ mask layer and GS-LDD channel would not be implanted for threshold voltage adjustment. For a comparative study with the classical HV LDD solution, three GS-LDD NMOS transistors were fabricated with LGS lengths of 0.05, 0.1 and 0.3 mm. Channel width, length and cell pitch were kept identical. nogen layer was set to 0.5 mm, allowing a total p-well implant reduction of 1 mm. Gate-shifting was carried out by active-area (AA) mask shrinking in both drain and source sides, while poly mask was maintained at the same length. Fig. 3 shows a photomicrograph of one of the GS-LDD structures fabricated in the CMOS process. Table 1 summarises the layout dimensions of the most relevant HV extended drain and HV GS-LDD fabricated transistors. Symmetric HV LDD and GS-LDD NMOS were designed with the same channel width and cell pitch lengths, along with the same layout and routing arrangement, occupying the same integration area.
5. Experimental static characteristics Experimental static device characterisation was done with an HP4145B semiconductor parameter analyser. The most relevant characteristics are summarised in Table 2. Table 1 Prototyped HV LDD and GS-LDD layout dimensions
Fig. 3. Photomicrograph of one of the GS-LDD prototyped devices.
LDD asymmetric LDD symmetric GS-LDD symmetric
W (mm)
L (mm)
LGS (mm)
Cell pitch (mm)
Gate area (mm2)
1880 1747 1747
1.5 4.0 4.0
0 0 0.05– 0.3
4.65 7.2 7.2
2820 6988 6289
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Table 2 Electrical characteristics for the experimental HV transistors
LDD asym. (LDD15) LDD symmetric (LDD40) GS-LDD (GS005) GS-LDD (GS01) GS-LDD (GS03) a b c
LGS (mm)
Ileak a (pA)
BV (V)
VTH b (mV)
RON (V)
0 0 0.05 0.1 0.3
600 575 454 488 288
22.1 23.9 23.6 27.6 29.8
0.56 0.54 0.52 0.52 0.52
33.0 25.7 22.2 26.6 32.5
c
At VDS ¼ 15 V. At 50 mA. AtVGS ¼ 5 V, VDS ¼ 0.1 V.
The symmetric LDD breakdown voltage is almost 2 V higher than the asymmetric LDD and the symmetric GS-LDD has a breakdown voltage around 30 V, which corresponds to an improvement of 6 V when compared to its equivalent symmetric LDD. As can be concluded from the experimental results in Table 2 and ID 2 VDS curves at off-state illustrated in Fig. 4, the employment of the gate-shifting technique allows a breakdown voltage increment of almost 6 V when compared to the classical extended drain or HV LDD solution. This 25% increase is reached with the maximum prototyped LGS length of 0.3 mm. For LGS ¼ 0:1 mm breakdown voltage improvement is around 15%, while the shorter gate-shifting GS-LDD disrupts at a slightly lower drain voltage than the LDD device. In fact, GS-LDD with LGS ¼ 0.05 mm and LDD devices are almost structurally identical, but it should be remembered that the drain-channel region is different, due to the retraction of p-well by 0.5 mm in the GS-LDD. As can be noticed in the ID 2 VGS curves of Fig. 5, both LDD and GS-LDD devices have identical performance at sub-threshold, weak and strong inversion. A closer look evidences a slight difference for the LDD device, which could be explained again by the discrepancy in
Fig. 5. Experimental ID 2 VGS (ID log scale) curves for the prototyped devices.
Fig. 4. Experimental ID 2 VDS (ID log scale) curves for the GS-LDD devices, together with the LDD, at off-state (VGS ¼ 0 V).
Fig. 6. Influence of the gate-shift length LGS in the GS-LDD devices specific On-resistance.
channel doping. In fact, as mentioned in the previous section, the intersection of nogen and n þ masks inhibits the threshold voltage implant by a total amount of 1 mm in the channel region. Therefore, in the GS-LDD devices, total doping at the surface is lower when compared with the LDD device. This explains the slight decrease in threshold voltage for the GS-LDD devices, as depicted in Table 2. As in GS-LDD devices fabricated in diffused wells CMOS processes, the use of the gate-shifting technique increases transistor On-resistance, due to the increase on devices drift path by an LGS amount. Table 2 also shows the influence of gate-shifting on devices On-resistance. For the GS-LDD with longer LGS length (0.3 mm) On-resistance is increased by 26% in comparison with the classical solution. Even so, GS-LDD devices keep reasonable values in terms of specific On-resistance, as can be seen in the graphic of Fig. 6. In saturation, GS-LDD devices evidence improved performance than the corresponding LDD. Fig. 7 illustrates devices static performance in saturation for drain voltages below breakdown and with VGS ¼ 1 V. As can be seen, parasitic bipolar effect is visible at lower drain voltages for the classical solution. As a consequence, GS-LDD devices will permit larger safe-operation area (SOA).
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Fig. 7. Experimental ID 2 VDS curves at VGS ¼ 1 V for the GS-LDD and the LDD devices, showing the reduction of the parasitic bipolar effect for the former.
6. Switching characteristics Both symmetric LDD and GS-LDD where tested to evaluate their switching characteristics. Experimental switching times were taken with gate pulses of 5 V, with 6% duty cycle and rise and fall times of 57 and 72 ns, respectively. Transistors switching times are summarized in Table 3. As can be noticed, HV LDD and GS-LDD switching times values are close, with a slightly better performance for the former. To illustrate the dynamic performance of the GS-LDD, the device was tested in a simple circuit, switching a resistive load at high frequencies. Fig. 8 shows GS-LDD device VDS switching signal at 1 and 3 MHz when driven with a poor signal-to-noise ratio gate control signal. It is expected that with an improved gate control signal, especially in terms of rise and fall times, the GS-LDD maximum switching frequency would increase.
7. Devices degradation and reliability for switching applications Experimental results in the previous sections prove the viability of the GS-LDD NMOS transistor in last generation CMOS. However, HV LDD and GS-LDD NMOS specific On-resistance is still higher when compared to an LDMOS, available in more complex but also much more expensive technologies. This drawback is a limitation especially if the device is targeted for high current applications.
Fig. 8. Experimental waveforms for the GS-LDD switching a resistive load: (a) fs ¼ 1 MHz, VDD ¼ 20 V and RD ¼ 1 kV; (b) fs ¼ 3 MHz, VDD ¼ 20 V and RD ¼ 100 V.
Devices On-resistance (and consequently, specific On-resistance) can be reduced by applying higher overdrive voltages at gate-source, when the transistor is in the triode region. This behaviour is depicted in Fig. 9 for the prototyped devices. As can be noticed, taken the example
Table 3 Experimental switching times (ns) for the symmetric LDD and the GS-LDD NMOS
Sym. LDD GS-LDD
tdon
tfv
tdoff
trv
24 25
27 32
94 93
69 72
Fig. 9. Experimental dependence of the specific On-resistance on the gatesource voltage, for the prototyped HV transistors (At VDS ¼ 0.5 V).
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of the GS-LDD, specific On-resistance is considerably reduced (33%) if the gate-source voltage is set above 2 V. For a gate-source voltage of 3 V, which is close to the process nominal digital supply (3.3 V), the GS-LDD presents a specific On-resistance of 5.2 mVcm2. Increasing VGS above this nominal value further reduces On-resistance, at a lower rate, but device lifetime and reliability should decrease. Thus, a study of the optimum overdrive voltage for these HV transistors is mandatory. Fig. 10 shows simulation results for electric field strength at device surface (10 nm deep) for the prototyped symmetric HV LDD NMOS at three distinct operating points (Fig. 10(a)): triode, saturation and cut-off regions. At cut-off (Fig. 10(b)), with VGS ¼ 0 V, electric field peak (0.5 MV/cm) is aligned with the drain side gate edge, while electric field is constant along the channel. As VDS is decreased and VGS increased to enter saturation, the electric field drops at drain side gate edge and the peak is dislocated to the channel. In the triode region, the device is mainly under a strong channel stress. As can be concluded, saturation is the most stressed operating condition, due to both drain-avalanche and channel hot-carrier injection into the gate oxide, causing a long-term degradation of MOS behaviour.
This is a serious problem in analogue applications since degraded devices origin mismatch and circuit malfunction, due to threshold voltage and transcondutance degradation [6,7]. However, in Power Electronics circuits and in switching systems, devices change between cut-off and triode region. These operation modes are the main responsible for device degradation in Power Electronics applications. Degradation in saturation is less important, since it occurs during rise and fall switching times, and only in the worst-case hard switching topology. Maximum allowable gate voltages are strongly dependent on gate oxide thickness but also depend on expected device lifetime [8,9]. The evaluation of the maximum voltage to be applied to a specific oxide can be calculated from the time-to-breakdown [9]. As previously mentioned in Section 2, the gate oxide for this CMOS process is 10 nm thick. Experiments on the HV devices gate-bulk capacitor revealed a dielectric breakdown above 11 V, like mentioned in the process documentation and in Section 2. As can be seen in Fig. 11, experimental dielectric breakdown is almost coincident for the considered devices and not related to gate area (Table 1), which is in agreement with other works [10]. According to time-to-breakdown calculations [9,10] for a 10 years lifetime at 25 8C,
Fig. 10. Simulation results for the electric field distribution at the surface (10 nm deep) of a symmetric LDD structure: (a) ohmic, saturation and cut-off simulated operating points; (b) cut-off, with VGS ¼ 0 V and VDS ¼ 20 V; (c) saturation, with VGS ¼ 3 V and VDS ¼ 10 V; (d) triode region, with VGS ¼ 5 V and VDS ¼ 0.5 V.
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Fig. 11. Gate current (log scale) against gate-bulk voltage, for the HV prototyped devices.
and assuming a defect free oxide, the maximum allowable gate voltage for this CMOS process is limited to 7.8 V, which is well above the 3.3 V nominal supply. However, experiments revealed severe degradation of electrical parameters for high gate electric fields and stress conditions, above the calculated 7.8 V. Fig. 12(a) shows curves obtained from asymmetric LDD devices under
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similar stress conditions, in the triode region (VDS ¼ 0.1 V), one after a DC stress with a gate voltage of 8 V (8 MV/cm gate field) for 1.5 h and the other with a gate voltage of 10 V (10 MV/cm gate field) for 20 min. The sub threshold slope and the significant threshold voltage degradations are evident when comparing the stressed curves with the curve obtained from a non-stressed sample. Device performance was also changed in saturation with a strong transconductance decrease, as can be seen in Fig. 12(b). Thus, the influence of the gate voltage (and gate electric field) in device degradation and lifetime is crucial. Considering trade-offs between specific On-resistance and device reliability and lifetime it was found advisable to switch the prototyped devices at lower overdrive voltages, in the 2– 3 V range. LDD and GS-LDD devices were also tested for degradation in the saturation region, near cut-off, with a high VDS voltage (20 V) and with VGS ¼ 1 V, corresponding to a low overdrive voltage. As mentioned before, this region of operation corresponds to a strong carrier injection into the oxide near the drain gate edge, caused by avalanche impact ionisation generated carriers. Fig. 12(c) shows devices sub threshold and threshold degradation after a 60 h DC stress. As can be seen, degradation in this region is less dramatic
Fig. 12. Device performance before and after DC stress: (a) ID 2 VGS and (b) ID 2 VDS for the asymmetric LDD; (c) ID 2 VGS and (d) ID 2 VDS for the symmetric LDD and GS-LDD.
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when compared to a DC stress in the triode region with high overdrive voltages. Furthermore, the GS-LDD degradation is much less visible then that of the LDD in the sub threshold region, for VGS , 0.6 V. On-resistance degradation is also lower for the GS-LDD, as can be seen in Fig. 12(d). The degradation in saturation does not correspond to the usual transconductance degradation [6,7], like in low voltage MOSFETs. This behaviour is still under investigation and should be discussed in future contributions. These experimental results evidence an additional benefit of using GS-LDD instead of LDD for HV structures. In fact, for the same drain voltage, GS-LDD electric field peak, at cut-off or near cut-off with low overdrive voltage, is lower than in the classical HV LDD structure. Thus, impact generation rate is lower and hot-carrier injection into the oxide is reduced for the GS-LDD.
8. Conclusions The viability of using the gate-shifting technique to improve extended drain HV NMOS breakdown voltage was demonstrated for last generation fully implanted CMOS processes, only resorting to mask manipulation. Comparatively to the classical HV LDD solution, the HV GS-LDD revealed better performance in terms of breakdown and parasitic bipolar effect. Furthermore, the GS-LDD lifetime is longer than the similar LDD solution for identical blocking conditions with high drain voltages, especially due to its hot-carrier resistant structure. It was also experimentally confirmed that the CMOS process oxide thickness is the main limitation for device switching at high overdrive voltages. Considering devices specific On-resistance and reliability it is suggested a maximum control voltage between 2– 3 V for this 10 nm gate oxide. With this contribution, smart power integrated circuits designers could continue to resort to the accessible CMOS technology for High-Voltage applications.
Acknowledgements To the memory of Professor Ineˆs Castro Simas, from who it all started. This work is supported by FCT/MCES (Portugal) and FSE/FEDER under the program POCTI 34424/ESE/2000.
References [1] J. Sanchez, State of the art and trends in power integration, Invited paper, Second International Conference on Modelling and Simulation of Microsystems, Semiconductors, Sensors and Actuators (MSM’99), San Juan (Porto Rico) April (1999) 20–29. [2] C. Contiero, et al., Smart power approaches VLSI complexity, Proceedings of International Symposium on Power Semiconductor Devices and ICs, ISPSD’98, Kyoto, Japan (1998) 11–16. [3] G. Dolny, O. Shade, B. Goldsmith, L. Goodman, Enhanced CMOS for analog-digital power IC applications, IEEE Transactions on Electron Devices 33 (12) (1986) 1985–1991. [4] P.M. Santos, A.P. Casimiro, M.I. Castro Simas, M. Lanc¸a, CMOS compatible HV gate-shifted LDD-NMOS, IEEE Transactions on Electron Devices 48 (5) (2001) 1013–1015. [5] P.M. Santos, A.P. Casimiro, M. Lanc¸a, M.I. Castro Simas, High Voltage Solutions in CMOS Technology, vol. 33, Microelectronics Journal, Elsevier, 2002, pp. 1013–1015. [6] C. Hu, et al., Hot-electron-induced MOSFET degradation-model, monitor and improvement, IEEE Transactions on Electron Devices 32 (2) (1985) 375–385. [7] K. Chen, S. Saller, I. Groves, D. Scott, Reliability effects on MOS transistors due to hot-carrier injection, IEEE Transactions on Electron Devices 32 (2) (1985) 386– 393. [8] K. Yamabe, K. Taniguchi, Time-Dependent Dielectric Breakdown of Thermally Grown SiO2 Films, IEEE Transactions on Electron Devices 32 (2) (1985) 423– 428. [9] R. Moazzami, C. Hu, Projecting gate oxide reliability and optimizing reliability screens, IEEE Transactions on Electron Devices 37 (7) (1990) 1643–1650. [10] D. Dumin, N. Heilemen, N. Husain, Test structures to investigate thin insulator wearout and breakdown, Proceedings of the IEEE International Conference on Microelectronic Test Structures 4 (1) (1991) 61– 67.
High-voltage NMOS design in fully implanted twin-well CMOS P.M. Santos*, H. Quaresma, A.P. Silva, M. Lanc¸a Instituto de Telecomunicac¸o˜es/Instituto Superior Te´cnico, Av. Rovisco Pais, 1049-001 Lisboa, Portugal Received 1 April 2004; revised 24 May 2004; accepted 1 June 2004 Available online 28 July 2004
Abstract This paper discusses the viability of using last generation CMOS technology to develop a High-Voltage NMOS library for smart power integration. Breakdown voltages of the order of 30 V can be achieved for Gate-Shifted extended drain NMOS devices fabricated in a fully implanted, twin-well, 0.5 mm CMOS core process, aimed for mixed-mode applications, without process modification or any additional mask. The trade-offs of using high overdrive voltages, above nominal supply, to reduce On-resistance is also discussed. According to experiments on prototypes, devices under excessive overdrive voltages over long periods revealed threshold voltage and transconductance variations, due to gate oxide degradation. q 2004 Elsevier Ltd. All rights reserved. Keywords: CMOS compatible; Drain engineering; Power integrated circuits; Reliability; Smart power
1. Introduction Smart power is also trying to follow the Roadmap with high-resolution lithography, answering to the increased demand in complexity and integration density, mainly in portable applications [1,2]. Consequently, projecting smart power ICs is becoming more expensive and inaccessible for fabless design houses. According to this scenario, several foundries developed commercially available High-Voltage CMOS processes derived from the CMOS core, with some additional steps and mask layers to perform the high voltage device, usually an LDMOS. Another approach for smart power integration for low power applications involves the extended drain technique [3] to perform High-Voltage (HV) NMOS in a digital or mixed-mode core CMOS process with no extra processing. Previous works [4,5] indicated another fully CMOS compatible drain engineering technique—the gate-shifting—useful to increase extended drain transistors breakdown voltages fabricated in CMOS processes with long term diffused wells. As mask lithography is still shrinking to pursue Moore’s law, CMOS process steps were also adapted to fulfil minimum feature lengths. In this way, wells are no longer * Corresponding author. Fax: þ 35-12-1841-8472. E-mail address: [email protected] (P.M. Santos). 0026-2692/$ - see front matter q 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2004.06.002
diffused but fully implanted at high energies in deep submicron CMOS. To prove the viability of last generation CMOS for smart power applications, this paper presents the criteria to project and design HV NMOS transistors in a deep submicron CMOS technology, commercially available for digital and mixed-mode ASICs. In particular, this work explains the unconventional required mask manipulation to design HV gate-shifted lightly-doped drain (GS-LDD) transistors. Experimental results will be presented and devices performances compared. Finally, the trade-offs of using voltages well above the nominal process supply, especially high overdrive voltages in the thin gate oxide, is discussed in terms of On-resistance and long term reliability.
2. The 0.5 mm CMOS process The High voltage NMOS transistors were projected and ‘full-custom’ designed to be fabricated in a mixedmode 0.5 mm, single level poly, triple level metal, and twin-tub CMOS process. The starting material is a , 100 . p-substrate with a 10 – 13 Vcm epitaxial layer. The process uses high-energy ion implantation to obtain the twin retrograde wells, with metallurgical junctions around 1 mm deep. Typical oxide thickness is 10 nm with
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a dielectric breakdown around 11 V. The standard low-voltage NMOS and PMOS transistors are designed for a nominal 3.3 V supply operation, with typical threshold voltages of the order of 0.6/2 0.6 V and breakdown voltages above 7 V. According to the process documentation, these standard cells present a 25 years lifetime with less then 10% transconductance ðgm Þ degradation and less than 100 mV threshold voltage ðVTH Þ increase, when operating continuously under nominal supply voltage in digital applications. Operation at higher voltages reduces devices lifetime.
The HV LDD channel is formed by two implants: the retrograde p-well implant, usually automatically defined by the complement of n-well mask (not shown in Fig. 1); and the corresponding threshold implant adjustment, mainly defined by the n þ layer, like in the low voltage NMOS standard cell. Devices cross-section optimisation, namely channel length and drain drift path, was carried out with the aid of 2D simulations. It was found that the channel length of 3 mm, defined by the minimum allowable design rule for two adjacent n-wells, was enough to avoid punchthrough.
4. Breakdown voltage improvement 3. High voltage NMOS in core CMOS The development of a symmetric High-Voltage extended drain or LDD NMOS transistor in this process can be easily obtained with a layout mask arrangement analogous to the indicated in Fig. 1(a). In this symmetric (high-side) layout, n-well mask is defined in both drain and source regions to allow lightly doped drift paths between the channel and drain/source contacts. Only one layout rule is not verified with the mask arrangement of Fig. 1. Other possible layouts could be valid, depending on foundry available layers, design rules check (DRC) tool and automatic mask generation criteria. As p-well mask is automatically generated as the complement of n-well, channel active area region below polysilicon gate is formed by the retrograde p-well, which, in fact, is the process substrate for the low voltage standard NMOS. Transistor gate is aligned with the highly resistive n-well implant of the drain and source. This arrangement reduces the electric field stress at the semiconductor surface when the device is blocking a drain voltage (VDS . VGS ¼ 0 V). Due to the presence of the n-well path, critical electric field for Silicon, responsible for electron-hole pair generation by impact ionisation, is reached at drain voltages well above the standard cell NMOS breakdown voltage (7 V). For the asymmetric (low-side) HV LDD device, the source-side mask layout is similar to the NMOS standard cell design (Fig. 1(b)).
Breakdown voltage improvement of HV extended drain NMOS devices using core CMOS processes is not an easy task. In fact, when compared with BCD, BiCMOS or dedicated smart power technologies, CMOS is the less complex of all, due to the reduced number of masks and specific implant regions. On the other hand, the fully CMOS compatible gate-shifting technique was found efficient to perform breakdown voltage increase in GS-LDD devices fabricated in diffused wells CMOS processes [4,5]. However, the implementation of GS-LDD devices in a twin and fully implanted wells CMOS process is not so obvious. The implementation of the gate-shifting technique in this scenario must take into account the following aspects: (1) implanted p and n wells junction at device Si – SiO2 interface is defined by the end of n-well mask, as p-well is usually automatically generated as the complement of this layer; (2) with the gate-shifting technique, the drain side gate edge should be shifted from n-well edge by an LGS length, in order to lower electric field at off-state, resulting in breakdown voltage improvement [4]. As can be seen in Fig. 2(a), this procedure locates the gate edge in alignment with a portion of the p-well implant causing channel interruption (Fig. 2(a)). In this paper, a fully CMOS compatible new layout strategy is suggested, which is based on the p-well inhibition near the wells junction and beneath the gate edge,
Fig. 1. Cross section and mask arrangement of fully CMOS compatible extended drain NMOS High-Voltage structures: (a) symmetric HV LDD NMOS with inclusion of the lightly doped n-well path in both drain and source; (b) detail of the source side for an asymmetric HV LDD NMOS.
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Fig. 2. Application of the gate-shifting technique in a fully implanted twin well process: (a) incorrect mask arrangement, which causes channel interruption; (b) proposed layout arrangement to avoid channel interruption.
like depicted in Fig. 2(b), to perform gate-shifting. This p-well retraction is achieved with mask manipulation, resorting to the layer nogen, which acts as an inhibitor to the foundry automatic mask generation procedure. Thus, p-well will not be implanted in nogen regions allowing n-well expansion to the channel. As the intersection of poly and active-area mask edge is located in the middle of the region defined by nogen, gate edge will be positioned in alignment with the low concentrated n-well lateral scattering path, avoiding channel interruption and improving breakdown. The nlddprot mask over the entire cell avoids implants of shallow lightly doped regions used for hot carrier injection reduction in low voltage standard NMOS, which are higher concentrated than n-well surface. nldd and p-well masks must also be drawn coincident to the nogen layer, since they are negative masks. The complete inhibition of p-well with nogen is not recommended since it will also inhibit
n þ mask layer and GS-LDD channel would not be implanted for threshold voltage adjustment. For a comparative study with the classical HV LDD solution, three GS-LDD NMOS transistors were fabricated with LGS lengths of 0.05, 0.1 and 0.3 mm. Channel width, length and cell pitch were kept identical. nogen layer was set to 0.5 mm, allowing a total p-well implant reduction of 1 mm. Gate-shifting was carried out by active-area (AA) mask shrinking in both drain and source sides, while poly mask was maintained at the same length. Fig. 3 shows a photomicrograph of one of the GS-LDD structures fabricated in the CMOS process. Table 1 summarises the layout dimensions of the most relevant HV extended drain and HV GS-LDD fabricated transistors. Symmetric HV LDD and GS-LDD NMOS were designed with the same channel width and cell pitch lengths, along with the same layout and routing arrangement, occupying the same integration area.
5. Experimental static characteristics Experimental static device characterisation was done with an HP4145B semiconductor parameter analyser. The most relevant characteristics are summarised in Table 2. Table 1 Prototyped HV LDD and GS-LDD layout dimensions
Fig. 3. Photomicrograph of one of the GS-LDD prototyped devices.
LDD asymmetric LDD symmetric GS-LDD symmetric
W (mm)
L (mm)
LGS (mm)
Cell pitch (mm)
Gate area (mm2)
1880 1747 1747
1.5 4.0 4.0
0 0 0.05– 0.3
4.65 7.2 7.2
2820 6988 6289
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Table 2 Electrical characteristics for the experimental HV transistors
LDD asym. (LDD15) LDD symmetric (LDD40) GS-LDD (GS005) GS-LDD (GS01) GS-LDD (GS03) a b c
LGS (mm)
Ileak a (pA)
BV (V)
VTH b (mV)
RON (V)
0 0 0.05 0.1 0.3
600 575 454 488 288
22.1 23.9 23.6 27.6 29.8
0.56 0.54 0.52 0.52 0.52
33.0 25.7 22.2 26.6 32.5
c
At VDS ¼ 15 V. At 50 mA. AtVGS ¼ 5 V, VDS ¼ 0.1 V.
The symmetric LDD breakdown voltage is almost 2 V higher than the asymmetric LDD and the symmetric GS-LDD has a breakdown voltage around 30 V, which corresponds to an improvement of 6 V when compared to its equivalent symmetric LDD. As can be concluded from the experimental results in Table 2 and ID 2 VDS curves at off-state illustrated in Fig. 4, the employment of the gate-shifting technique allows a breakdown voltage increment of almost 6 V when compared to the classical extended drain or HV LDD solution. This 25% increase is reached with the maximum prototyped LGS length of 0.3 mm. For LGS ¼ 0:1 mm breakdown voltage improvement is around 15%, while the shorter gate-shifting GS-LDD disrupts at a slightly lower drain voltage than the LDD device. In fact, GS-LDD with LGS ¼ 0.05 mm and LDD devices are almost structurally identical, but it should be remembered that the drain-channel region is different, due to the retraction of p-well by 0.5 mm in the GS-LDD. As can be noticed in the ID 2 VGS curves of Fig. 5, both LDD and GS-LDD devices have identical performance at sub-threshold, weak and strong inversion. A closer look evidences a slight difference for the LDD device, which could be explained again by the discrepancy in
Fig. 5. Experimental ID 2 VGS (ID log scale) curves for the prototyped devices.
Fig. 4. Experimental ID 2 VDS (ID log scale) curves for the GS-LDD devices, together with the LDD, at off-state (VGS ¼ 0 V).
Fig. 6. Influence of the gate-shift length LGS in the GS-LDD devices specific On-resistance.
channel doping. In fact, as mentioned in the previous section, the intersection of nogen and n þ masks inhibits the threshold voltage implant by a total amount of 1 mm in the channel region. Therefore, in the GS-LDD devices, total doping at the surface is lower when compared with the LDD device. This explains the slight decrease in threshold voltage for the GS-LDD devices, as depicted in Table 2. As in GS-LDD devices fabricated in diffused wells CMOS processes, the use of the gate-shifting technique increases transistor On-resistance, due to the increase on devices drift path by an LGS amount. Table 2 also shows the influence of gate-shifting on devices On-resistance. For the GS-LDD with longer LGS length (0.3 mm) On-resistance is increased by 26% in comparison with the classical solution. Even so, GS-LDD devices keep reasonable values in terms of specific On-resistance, as can be seen in the graphic of Fig. 6. In saturation, GS-LDD devices evidence improved performance than the corresponding LDD. Fig. 7 illustrates devices static performance in saturation for drain voltages below breakdown and with VGS ¼ 1 V. As can be seen, parasitic bipolar effect is visible at lower drain voltages for the classical solution. As a consequence, GS-LDD devices will permit larger safe-operation area (SOA).
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Fig. 7. Experimental ID 2 VDS curves at VGS ¼ 1 V for the GS-LDD and the LDD devices, showing the reduction of the parasitic bipolar effect for the former.
6. Switching characteristics Both symmetric LDD and GS-LDD where tested to evaluate their switching characteristics. Experimental switching times were taken with gate pulses of 5 V, with 6% duty cycle and rise and fall times of 57 and 72 ns, respectively. Transistors switching times are summarized in Table 3. As can be noticed, HV LDD and GS-LDD switching times values are close, with a slightly better performance for the former. To illustrate the dynamic performance of the GS-LDD, the device was tested in a simple circuit, switching a resistive load at high frequencies. Fig. 8 shows GS-LDD device VDS switching signal at 1 and 3 MHz when driven with a poor signal-to-noise ratio gate control signal. It is expected that with an improved gate control signal, especially in terms of rise and fall times, the GS-LDD maximum switching frequency would increase.
7. Devices degradation and reliability for switching applications Experimental results in the previous sections prove the viability of the GS-LDD NMOS transistor in last generation CMOS. However, HV LDD and GS-LDD NMOS specific On-resistance is still higher when compared to an LDMOS, available in more complex but also much more expensive technologies. This drawback is a limitation especially if the device is targeted for high current applications.
Fig. 8. Experimental waveforms for the GS-LDD switching a resistive load: (a) fs ¼ 1 MHz, VDD ¼ 20 V and RD ¼ 1 kV; (b) fs ¼ 3 MHz, VDD ¼ 20 V and RD ¼ 100 V.
Devices On-resistance (and consequently, specific On-resistance) can be reduced by applying higher overdrive voltages at gate-source, when the transistor is in the triode region. This behaviour is depicted in Fig. 9 for the prototyped devices. As can be noticed, taken the example
Table 3 Experimental switching times (ns) for the symmetric LDD and the GS-LDD NMOS
Sym. LDD GS-LDD
tdon
tfv
tdoff
trv
24 25
27 32
94 93
69 72
Fig. 9. Experimental dependence of the specific On-resistance on the gatesource voltage, for the prototyped HV transistors (At VDS ¼ 0.5 V).
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of the GS-LDD, specific On-resistance is considerably reduced (33%) if the gate-source voltage is set above 2 V. For a gate-source voltage of 3 V, which is close to the process nominal digital supply (3.3 V), the GS-LDD presents a specific On-resistance of 5.2 mVcm2. Increasing VGS above this nominal value further reduces On-resistance, at a lower rate, but device lifetime and reliability should decrease. Thus, a study of the optimum overdrive voltage for these HV transistors is mandatory. Fig. 10 shows simulation results for electric field strength at device surface (10 nm deep) for the prototyped symmetric HV LDD NMOS at three distinct operating points (Fig. 10(a)): triode, saturation and cut-off regions. At cut-off (Fig. 10(b)), with VGS ¼ 0 V, electric field peak (0.5 MV/cm) is aligned with the drain side gate edge, while electric field is constant along the channel. As VDS is decreased and VGS increased to enter saturation, the electric field drops at drain side gate edge and the peak is dislocated to the channel. In the triode region, the device is mainly under a strong channel stress. As can be concluded, saturation is the most stressed operating condition, due to both drain-avalanche and channel hot-carrier injection into the gate oxide, causing a long-term degradation of MOS behaviour.
This is a serious problem in analogue applications since degraded devices origin mismatch and circuit malfunction, due to threshold voltage and transcondutance degradation [6,7]. However, in Power Electronics circuits and in switching systems, devices change between cut-off and triode region. These operation modes are the main responsible for device degradation in Power Electronics applications. Degradation in saturation is less important, since it occurs during rise and fall switching times, and only in the worst-case hard switching topology. Maximum allowable gate voltages are strongly dependent on gate oxide thickness but also depend on expected device lifetime [8,9]. The evaluation of the maximum voltage to be applied to a specific oxide can be calculated from the time-to-breakdown [9]. As previously mentioned in Section 2, the gate oxide for this CMOS process is 10 nm thick. Experiments on the HV devices gate-bulk capacitor revealed a dielectric breakdown above 11 V, like mentioned in the process documentation and in Section 2. As can be seen in Fig. 11, experimental dielectric breakdown is almost coincident for the considered devices and not related to gate area (Table 1), which is in agreement with other works [10]. According to time-to-breakdown calculations [9,10] for a 10 years lifetime at 25 8C,
Fig. 10. Simulation results for the electric field distribution at the surface (10 nm deep) of a symmetric LDD structure: (a) ohmic, saturation and cut-off simulated operating points; (b) cut-off, with VGS ¼ 0 V and VDS ¼ 20 V; (c) saturation, with VGS ¼ 3 V and VDS ¼ 10 V; (d) triode region, with VGS ¼ 5 V and VDS ¼ 0.5 V.
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Fig. 11. Gate current (log scale) against gate-bulk voltage, for the HV prototyped devices.
and assuming a defect free oxide, the maximum allowable gate voltage for this CMOS process is limited to 7.8 V, which is well above the 3.3 V nominal supply. However, experiments revealed severe degradation of electrical parameters for high gate electric fields and stress conditions, above the calculated 7.8 V. Fig. 12(a) shows curves obtained from asymmetric LDD devices under
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similar stress conditions, in the triode region (VDS ¼ 0.1 V), one after a DC stress with a gate voltage of 8 V (8 MV/cm gate field) for 1.5 h and the other with a gate voltage of 10 V (10 MV/cm gate field) for 20 min. The sub threshold slope and the significant threshold voltage degradations are evident when comparing the stressed curves with the curve obtained from a non-stressed sample. Device performance was also changed in saturation with a strong transconductance decrease, as can be seen in Fig. 12(b). Thus, the influence of the gate voltage (and gate electric field) in device degradation and lifetime is crucial. Considering trade-offs between specific On-resistance and device reliability and lifetime it was found advisable to switch the prototyped devices at lower overdrive voltages, in the 2– 3 V range. LDD and GS-LDD devices were also tested for degradation in the saturation region, near cut-off, with a high VDS voltage (20 V) and with VGS ¼ 1 V, corresponding to a low overdrive voltage. As mentioned before, this region of operation corresponds to a strong carrier injection into the oxide near the drain gate edge, caused by avalanche impact ionisation generated carriers. Fig. 12(c) shows devices sub threshold and threshold degradation after a 60 h DC stress. As can be seen, degradation in this region is less dramatic
Fig. 12. Device performance before and after DC stress: (a) ID 2 VGS and (b) ID 2 VDS for the asymmetric LDD; (c) ID 2 VGS and (d) ID 2 VDS for the symmetric LDD and GS-LDD.
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when compared to a DC stress in the triode region with high overdrive voltages. Furthermore, the GS-LDD degradation is much less visible then that of the LDD in the sub threshold region, for VGS , 0.6 V. On-resistance degradation is also lower for the GS-LDD, as can be seen in Fig. 12(d). The degradation in saturation does not correspond to the usual transconductance degradation [6,7], like in low voltage MOSFETs. This behaviour is still under investigation and should be discussed in future contributions. These experimental results evidence an additional benefit of using GS-LDD instead of LDD for HV structures. In fact, for the same drain voltage, GS-LDD electric field peak, at cut-off or near cut-off with low overdrive voltage, is lower than in the classical HV LDD structure. Thus, impact generation rate is lower and hot-carrier injection into the oxide is reduced for the GS-LDD.
8. Conclusions The viability of using the gate-shifting technique to improve extended drain HV NMOS breakdown voltage was demonstrated for last generation fully implanted CMOS processes, only resorting to mask manipulation. Comparatively to the classical HV LDD solution, the HV GS-LDD revealed better performance in terms of breakdown and parasitic bipolar effect. Furthermore, the GS-LDD lifetime is longer than the similar LDD solution for identical blocking conditions with high drain voltages, especially due to its hot-carrier resistant structure. It was also experimentally confirmed that the CMOS process oxide thickness is the main limitation for device switching at high overdrive voltages. Considering devices specific On-resistance and reliability it is suggested a maximum control voltage between 2– 3 V for this 10 nm gate oxide. With this contribution, smart power integrated circuits designers could continue to resort to the accessible CMOS technology for High-Voltage applications.
Acknowledgements To the memory of Professor Ineˆs Castro Simas, from who it all started. This work is supported by FCT/MCES (Portugal) and FSE/FEDER under the program POCTI 34424/ESE/2000.
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