Highly accelerated life testing (HALT) for multilayer ceramic capacitor qualification

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World Abstracts on Microelectronics and Reliability

capacitors (MLC) using the temperature-humidity-bias test (THB). The cumulative failure data showed that the MLC failures occurred in several stages in the duration of the THB test, with the extent of failures depending on the quality of the capacitor lot and the bias voltage. THB failures increased after some of the MLC lots had undergone a barrel plating operation, indicating moisture penetration and ionic contaminants as the likely cause of accelerating the failure rate. In cross sections of failed MLC, we observed large holes caused by high-temperature explosive events occurring inside the MLC. There were also internal cracks connecting electrodes of opposite polarity, with silver inclusions along the length of the cracks. These observations strongly suggested that silver migration was the cause of electrically short-circuit paths, leading to subsequent failure of the MLC. This conclusion was supported by model experiments in which silver from exposed electrodes migrated large distances (700/~m) under standard THB conditions. These experiments also showed that electromigration of silver could occur in the absence of ionic contaminants from plating baths.

Mathematical model of a plated-through hole under a load induced by thermal mismatch. BoRIs A, MIRMAN. IEEE Trans. Comp. Hybrids Manufact. Tech. 11(4), 506 (December 1988). A mathematical model simulating a platedthrough hole (PTH) under a thermal load is proposed to predict PTH reliability. The PTH is treated, as a system of disks joined to a barrel. Under the load, the disks bend and the barrel undergoes either tension or compression. The resulting failures are predicted by computing "failure indicators." Also presented are simple formulas to estimate some of these failure indicators.

Experimental and statistical analyses of surface-mount technology PLCC solder-joint reliability. JOHN H. LAU, GIRVlN HARKINS, DONALD RICE, JOSEPH KRAL and BETTY WELLS. IEEE Trans. Reliab. 37(5), 524 (December 1988). The mechanical integrity of surface mount technology (SMT) plastic leaded chip carrier (PLCC) solder joints has been studied by a 4-point mechanical flexure fatigue test. The effects of printed circuit board (PCB) pad surface composition and testing temperature on solder joint reliability are emphasized. Three sets of PCBs have been tested, one with Cu-Ni-Sn pad surface metallurgy, one with Cu-Ni-Au, and one with SMOBC/SSC (Solder Mask Over Bare Copper/Selective Solder Coating, or simply, SMOBC). The solder composition was the 63wt%Sn/37wt%Pb eutectic. A 2-parameter Weibull distribution was used for the lifetime model for these three products. The uniformity, quality, reliability, and a comparison of these products are discussed. The joints formed on Cu-Ni-Au and SMOBC boards were appreciably more reliable than those formed on Cu-Ni-Sn board. Specific conclusions are: • The solder-joint fatigue cracking starts near the tip of the outer solder fillet and propagates along the interface between the J-lead and the solder joint. • The solder joints attached to a Cu-Ni-Au PCB and a SMOBC PCB are more uniform than those attached to a Cu-Ni-Sn PCB. There are more voids in the solder joints attached to a Cu-Ni-Sn board. • The mean life of solder joints attached to a Cu-Ni-Au PCB and a SMOBC PCB is better than those attached to a Cu-Ni-Sn PCB. • The uniformity and mean life of solder joints attached to a Cu-Ni-Au board and a SMOBC board are about the same. • Higher temperature reduces the fatigue life of the solder joints, especially above 60 C.

Application of non-destructive testing to inspection of soldered joints. M. FORSHAW. Circuil World 15(3), 14 (1989). There is an increasing requirement for inspection of electronic

components, assemblies and interconnections, and to meet this demand there are new developments in inspection techniques. None of the techniques is universally applicable, but many are capable of consistent and reliable results. This paper outlines the major techniques which are available and summarises their capabilities. The limitations on types of component and boards which may be examined are listed, and the difficulties of detecting some flaws with some techniques are highlighted and the reasons considered.

Temperature distribution in IC plastic packages in the reflow soldering process. HIDEO MIURA, ASAO NtSHIMURA, SUEO KAWAI and WATARU NAKAYAMA. 1EEE Trans. Comp. Hybrids Manufacl. Tech. 11(4), 499 (December lqgS). The temperature distribution in IC plastic packages in the reflow soldering process was discussed by both an experimental method and an analytical method. The temperature sensor composed ofa p-n junction diode was embedded in a silicon chip and the chip was molded in an actual plastic package to measure the chip temperature in the soldering process. Temperature variations of the chip during the dip-coating process, the vapor phase reflow soldering and the infrared reflow soldering were obtained. The FEM (finite-element method) analysis was performed to develop an effective method for estimating the temperature distribution in the package. It is found that the combination of laboratory experiment, proper modeling of thermal boundary condition for the package, and FEM analysis is an effective scheme to find a satisfactory operative condition for a soldering process.

Highly accelerated life testing (HALT) for mnltilayer ceramic capacitor qualification. RAMACHANDRA MUNIKOT! and PULAKDHAR. IEEE Trans. Comp, lqvbrids Manufact. Tech. 11(4), 342 (December 1988). This paper describes a highly accelerated life test (HALT) method for rapid qualification testing of multilayer ceramic capacitors. This method is proposed as an alternative to the present time-consuming standard 1000-2000-h life testing. HALT was employed to life test nearly 20 vendor lots of 50-V rated COG, X7R, and Z5U chip capacitors at 400 V and 140:C stress. Their failure rates are compared with those observed in the standard 1000-h life test at 100V and 135~C stress. Acceptable correlation has been observed between the two methods. In addition to reducing the qualification time from months to a few days, HALT has the capability of ascribing the device failures to manufacturing process or material defects. It can greatly help users to quickly identify defective lots, determine mean time to failure (MTTF) of each lot at incoming or detect major changes in the vendor's processes~ On the other hand, it enables the manufacturers to rapidly detect and correct process or material problems and improve their device reliability by orders of magnitude.

Fiabilit6 des fibres optiques. J, GOMBERT. Re~. l~,ch, Thomson-CSF 19(3 and 4), 679 (September--Decenaber 1987). (In French.) Optical fiber sensors and fiber optic guided weapon systems require very strong special fibers operating in harsh environments. However polymer coated fibers weaken as a function of time due to the glass "static fatigue" phenomenon. Two major ways may be used to assure tiftetime of long length fibers: proof testing or hermetic coating. The proof test guarantees, at the time it is carried out, a minimum strength or a corresponding minimum lifetime. For a fiber that should withstand an important service stress after a long storage period in a harsh environment, the proof test level can be very high so that the fiber under test has a large probability to break many times. To avoid such a high proof test level, the fiber can be sealed on line in an hermetic coating that will drastically reduce the ageing phenomenon. Such a fiber is thus proof tested at a reasonable stress level

World Abstracts on Microelectronics and Reliability The present paper describes in detail the proof test method and reviews the different techniques and products leading to an hermetic coating. A comparison between the two methods for fibers that will be submitted to large service stress after a long storage period in a harsh environment, leads to the conclusion that both methods should be employed simultaneously.

Thermal characterization of plastic and ceramic surfacemount components. STEPHENS. FURKAY.IEEE Trans. Comp. Hybrids Manufact. Tech. 11(4), 521 (December 1988). Use of surface-mount technology (SMT) has dramatically increased in recent years, particularly in applications where the thermal environment can be severe. Accurate thermal characterization of silicon devices packaged with SMT is paramount to reliable operation. This paper considers the thermal performance of devices packaged with the 68-, 84-, 100-, and 124-lead members of the plastic and ceramic flatpack family of surface-mounted components (PFP and CPF, respectively). Experimental data were collected in both natural and forced convection conditions for individual components surface-mounted to small sections of epoxy circuit card. The test vehicles were vertically mounted in separate rectangular channels and positioned to experience hydrodynamically developing flow. A custom thermal chip was employed to both simulate device power and also sense bulk chip temperature. Average air velocity and chip power dissipation were the primary independent test variables, ranging from 0 to 3 m/s and 0.2 to 2.0 W, respectively, for which internal and external thermal resistance data are presented. Two- and three-dimensional finite-element simulations were also performed in order to parametrically determine the effects of material and geometric variations on package thermal performance. Comparisons with empirical data were made where applicable.

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address how manufacturing contamination, materials selection, lubrication, and environmental protection impact all levels of interconnection. The information will be documented through discussion of actual field failures. Matching properties of linear MOS capacitors. R~J1NDER SINGH and A. B. BHATTACHARYYA.Solid-Sl. Electron. 32(4), 299 (1989). The matching property of MOS capacitors has been studied in accordance with well established statistical principles and on the basis of the experimentally generated data. Various random error mechanisms have been studied in a systematic manner. For edge-related errors, structures with approximately equal area but differing perimeters have been considered. Similarly, for corner-related errors, structures having approximately the same area and perimeter but a different number of corners have been studied. Some empirical relationships have been obtained. For the presently considered dimensions and technology, normalized random error in capacitor-ratio has been observed to have (i) an inverse square-root dependence upon the capacitor-area; (ii) a linear dependence upon the perimeter-toarea ratio; and (iii) a very weak dependence, n ~6, upon the capacitor-ration n. "Statistically highly significant" improvement in matching has been observed for hitherto unreported structure in which photolithographically defined corners are completely avoided. Application of the above "corner-less" configuration would result in a considerable saving of the capacitor-area in switched-capacitor, A/D and D/A converter applications. For realizing small real ratios, use of rectangular and ring-type structures is proposed. "Statistically significant" improvement in capacitor-matching has been obtained for such structures even though the perimeter-to-area ratio (P/A) of such structures is greater than the corresponding square-geometry ones. Finding board faults with thermal imaging. C. G. MASI. Test Measure. World 109 (March 1989). Military board-repair depots are streamlining their board diagnosis and repair operations with thermal analysis.

Experimental verification of a novel electrical test structure for measuring contact size. G. FREEMAN, W. LUKASZEK, T. W. EKSTEDTand D. W. PETERS. IEEE Trans. Semicond. Manufact. 2(1), 9 (February 1989). This paper presents a An electrically excited acoustic emission test technique for novel electrical test structure which measures contact size screening multilayer ceramic capacitors. NING-HUATCHAN without reliance upon contact resistivity measurements, A and BHARAT S. RAWAL. IEEE Trans. Comp. Hybrids comparison with scanning electron microscope (SEM) Manufact. Tech. 11(4), 358 (December 1988). An ac-voltagephotographs shows that the structure measures contact size induced acoustic emission test technique for screening physiin the range of 1.0 #m with a resolution close to 0.02 #m. cal flaws, particularly delaminations, in various Z5U and Results are shown for measuring the size of contacts to poly, X7R/BX ceramic capacitors was extensively evaluated. The but the concept should also apply to measuring contacts to test results showed that the severity of delaminations active, or contacts between two metal layers. In addition to strongly coincided with the corresponding degree of severity the size of contacts to poly, the structure presented here also in the acoustic signal. This had led to a more than ten times measures linewidth and sheet resistance of the poly, and higher rejection rate against the ceramic capacitors with misalignment of contacts to poly. It consists of a digital delaminations in most of our screening tests. vernier of 72 samples and a linewidth structure, and is The source of acoustic wave was attributed to the partial implemented without active circuitry in a 2 by 12 pad array discharge in delaminations, cracks, and pores due to using three masking levels. the field intensification by the high-K dielectric materials. Almost identical patterns of behavior were found between lnterconnection reliability. BARBARA T. REAGOR. IEEE acoustic emission and partial discharge with respect to the Trans. Comp. Hvbrid~ Manufact. Tech. 11(4), 390 (Decem- application of voltage and the change of dielectric material. ber 1988). The telecommunications industry has evolved from electromechanical analog systems to the current world Accelerated life tests of ceramic capacitors. BORIS M. of the digital-fiber/electronic switch. As technology conMOGILEVSKY and GEORGE A. SHIRN. IEEE Trans. Comp. tinues to advance, we are even beginning to catch a glimpse Hybrids Manufact. Tech. 11(4), 351 (December 1988). of the electronic/photonic world of tomorrow. In all these Multilayer capacitors prepared from three different ceramics systems, interconnection reliability is key to long-term operwere tested under highly accelerated conditions of both ation. In the past, the connections in our telecommuni- voltage and temperature. Three types of breakdown were cations networks were hard-wired and the systems were encountered: avalanche, fast thermal degradation, and large in size, Today, these systems are becoming smaller, diffusion or wearout. The goal was to determine whether more compact, and essentially modularized. As we multidata from highly accelerated life tests could be used to plot plex more and more of our signals onto a single wire or fiber, failure curves that would match those made at rated voltage the stability at every interconnection point becomes increasand temperature conditions. Thus the emphasis was on the ingly critical for long-term reliable operation. Here we wearout mode. present a summary of some of the key features that can The voltage accelerations were as high as 80 percent of the impact interconnection reliability. In particular, we will electric breakdown, and yielded voltage exponents between