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HfSiO gate stack and TaN metal gate
Microelectronic Engineering 86 (2009) 1–3
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Hot carrier effects in n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate Isodiana Crupi * MATIS CNR-INFM, University of Catania, Department of Physics and Astronomy, Via Santa Sofia 64, 95123 Catania, Italy
a r t i c l e
i n f o
Article history: Received 6 May 2008 Received in revised form 24 July 2008 Accepted 21 August 2008 Available online 8 September 2008 Keywords: High-k dielectrics Hot carrier stress Constant voltage stress
a b s t r a c t Charge trapping and trap generation in field-effect transistors with SiO2/HfO2/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case. Ó 2008 Elsevier B.V. All rights reserved.
The continuous trend of thinning the gate dielectric and shrinking the gate length in advanced complementary metal-oxide-semiconductor (CMOS) technologies leads to excessive gate tunneling leakage and reliability problems. To meet the International Technology Roadmap for Semiconductors specifications, materials with higher electrical permittivity than conventional SiO2 are extensively being investigated for future CMOS generations [1–7]. These dielectrics suffer from several issues, including threshold voltage instability, dielectric reliability, trap generation and charging effects [8,9]. As a result, there has been an intense effort to characterize and understand the properties of these materials to improve the device performance and reliability. After many years of research, the Hf-based high-k materials emerge as the most promising candidates to replace SiO2 gate dielectrics [10–12]. In conventional MOS field-effect transistors (MOSFETs), hot carrier effects, recognized as one of the major constraints in device scaling, have been widely researched. As is well known, under hot carrier injection, a high lateral electric field between source and drain heats the electrons sufficiently to gain enough energy to overcome the Si/SiO2 potential barrier, causing damage in this region and leading to the degradation of current–voltage characteristics. Traditionally, the highest hot carrier degradation occurs at the gate voltage which produces the maximum substrate current condition (VG VD/2). For a short channel device with highk dielectric, the most severe degradation under hot carrier stress (HCS) was reported to occur at the maximum gate current condition (VG VD) [13]. It is a well known fact that with respect to con* Tel.: +39 095 3785289; fax: +39 095 3785231. E-mail address: [email protected] 0167-9317/$ - see front matter Ó 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2008.08.009
stant voltage stress (CVS) during HCS both hot (close to the drain side) and cold (close to the source side) carriers can be injected in the dielectric, as sketched in Fig. 1, and mixed degradation mechanism occurs [14–17]. Even if the contribution of hot carriers cannot be quantified in a straightforward way, the purpose of this work is to differentiate between the filling of pre-existing defects and the generation of new charge trap sites. MOSFETs used in these experiments are n-channel with 1 nm HfO2/1.5 nm HfSiO (60% silicate) stack film grown by atomic layer deposition (ALD) on top of 1 nm chemically grown SiO2, formed by an O3-based oxidation of the Si substrate surface (IMEC clean). The dielectric stack has an equivalent oxide thickness (EOT), extracted by fitting the C–V curves with the CVC model [18], of 1.72 nm. The devices were subjected to post deposition annealing (PDA) at 600 °C in O2. The metal gate, physical vapor deposited (PVD) TaN layer, is capped with 100 nm of polysilicon. The measurements reported in this paper were performed on transistors with 10 lm gate width and 0.35 lm gate length at room temperature by using a Keithley 4200 semiconductor characterization system. The degradation behaviour of these transistors was evaluated by uniform and non-uniform charge injection along the channel, by applying CVS and hot carrier stress, respectively. In order to investigate the effects of the two stress conditions, the devices were biased with positive VG, source and body grounded and VD = 0 V or VD = VG during CVS or HCS, respectively. Initially, drain current, ID, and transconductance, Gm, were monitored as a function of gate bias, VG, on fresh device. Then the transistor was stressed for 100 s at various CVS, VG ranging from 2 to 3 V, and hot carrier stress, VG = VD ranging from 2 to 3 V. After each stress,
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I. Crupi / Microelectronic Engineering 86 (2009) 1–3
Fig. 1. Schematic picture representing the cold and hot carriers injection during hot electron stressing on n-MOSFET.
and successive sensing, a non-destructive negative gate bias (VG = 2 V, 100 s) with all other terminals grounded was applied to allow electron detrapping. After CVS, Fig. 2a, ID–VG, and corresponding Gm–VG, curves indicate that electrons can be reversible trapped and detrapped on preexisting defects. When the same gate bias is simultaneously
applied to the drain electrode, HCS leads not only to an irreversible shift of both sets of curves but also to their degradation, Fig. 2b. During HCS both cold and hot carriers can be injected in the dielectric stack and contribute to the degradation of transistor performance. Even, it is not easy to separate the effects of the two types of carriers, these results show that the cold carrier contribution is reversible, after the detrapping process the ID–VG curve returns to the expected value (dotted lines in Fig. 2a), while hot carrier effect damage is permanent, it cannot be reversed by application of the detrapping bias after the stress (dotted lines in Fig. 2b). Fig. 3 shows the difference in the average gate current, IG, during the cold (VG = Voltage) and hot (VG = VD = Voltage) stressing conditions discussed in Fig. 2. As can be seen, the gate current is always higher in the HCS case. This result is expected due to the hot carrier contribution that is added to the cold carrier one. In the CVS regime, IG increases with the applied voltage due to a smaller barrier height for cold electrons. Under hot stressing conditions, the average gate current initially increases strongly respect to the CVS case and then slightly decreases. In such a situation, new traps are generated in the system, as experimentally confirmed by the
Fig. 3. Average gate current, IG, during 100 s of cold (VG = V) and hot (VG = VD = V) stressing conditions.
Fig. 2. ID–VG and corresponding Gm–VG curves measured, with VD = 50 mV, before and after 100 s of: (a) CVS, VG ranging from 2 to 3 V with 0.2 V step, (b) HCS, VG = VD ranging from 2 to 3 V with 0.2 V step. The curves shift toward larger VG values by increasing the bias stress. The dotted lines are measured after the de-trapping process, 100 s with VG = 2 V, applied after each stress cycle.
Fig. 4. Maximum transconductance, GmMAX, and the subthreshold swing, S, degradations after the CVS (close and open circles, respectively) and the HCS (close and open triangles, respectively) of Fig. 3.
I. Crupi / Microelectronic Engineering 86 (2009) 1–3
degraded ID–VG characteristic measured immediately after the HCS. In fact, even after detrapping event, a given amount of the injected electrons remains trapped in these new sites, repels further incident electrons and causes reduction in IG as the voltage increases. Hot carriers generate significant damage on the device, while cold carriers do not. These conclusions are supported by the variation of the maximum transconductance, GmMAX, and the subthreshold swing, S, shown in Fig. 4. The data are extracted from the curves reported in Fig. 2a and b. The difference between CVS and HCS effects is evident. The curves slightly increase with the bias in the CVS case. The absence of significant degradation in the cold stressing experiments indicates that only electrons trapping in pre-existing defects play a role. In contrast under hot stressing conditions, significant and irreversible change in both the transconductance and the subthreshold swing of the devices was measured. The above results reflect the generation of new charge trap sites. Moreover, in order to explore the position of generated traps during channel hot carrier stress, the transfer characteristics of the device were even measured in the reverse (source and drain interchanged) mode of operation. There was no asymmetry in the threshold voltage values read at the two sides of the channel region indicating that, even after hot carrier stress, the damaged region is not confined to the drain corner but is expanded to the source region. In conclusion, charge injection and new traps generation under constant gate voltage and HCS were investigated on n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate electrode. Electrical data show the filling of pre-existing traps during CVS and the generation of new charge trap sites in the dielectric or at the interface during HCS. In all the cases, a quasi identical threshold voltage value was read at the source and at the drain side of the transistor suggesting that the damaged region is not localized but is expanded along the entire channel.
3
Acknowledgments The author would like to gratefully thank G. Groeseneken and IMEC high-k team for the sample provision and useful discussion. References [1] International Technology Roadmap for Semiconductors, see
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Hot carrier effects in n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate Isodiana Crupi * MATIS CNR-INFM, University of Catania, Department of Physics and Astronomy, Via Santa Sofia 64, 95123 Catania, Italy
a r t i c l e
i n f o
Article history: Received 6 May 2008 Received in revised form 24 July 2008 Accepted 21 August 2008 Available online 8 September 2008 Keywords: High-k dielectrics Hot carrier stress Constant voltage stress
a b s t r a c t Charge trapping and trap generation in field-effect transistors with SiO2/HfO2/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case. Ó 2008 Elsevier B.V. All rights reserved.
The continuous trend of thinning the gate dielectric and shrinking the gate length in advanced complementary metal-oxide-semiconductor (CMOS) technologies leads to excessive gate tunneling leakage and reliability problems. To meet the International Technology Roadmap for Semiconductors specifications, materials with higher electrical permittivity than conventional SiO2 are extensively being investigated for future CMOS generations [1–7]. These dielectrics suffer from several issues, including threshold voltage instability, dielectric reliability, trap generation and charging effects [8,9]. As a result, there has been an intense effort to characterize and understand the properties of these materials to improve the device performance and reliability. After many years of research, the Hf-based high-k materials emerge as the most promising candidates to replace SiO2 gate dielectrics [10–12]. In conventional MOS field-effect transistors (MOSFETs), hot carrier effects, recognized as one of the major constraints in device scaling, have been widely researched. As is well known, under hot carrier injection, a high lateral electric field between source and drain heats the electrons sufficiently to gain enough energy to overcome the Si/SiO2 potential barrier, causing damage in this region and leading to the degradation of current–voltage characteristics. Traditionally, the highest hot carrier degradation occurs at the gate voltage which produces the maximum substrate current condition (VG VD/2). For a short channel device with highk dielectric, the most severe degradation under hot carrier stress (HCS) was reported to occur at the maximum gate current condition (VG VD) [13]. It is a well known fact that with respect to con* Tel.: +39 095 3785289; fax: +39 095 3785231. E-mail address: [email protected] 0167-9317/$ - see front matter Ó 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2008.08.009
stant voltage stress (CVS) during HCS both hot (close to the drain side) and cold (close to the source side) carriers can be injected in the dielectric, as sketched in Fig. 1, and mixed degradation mechanism occurs [14–17]. Even if the contribution of hot carriers cannot be quantified in a straightforward way, the purpose of this work is to differentiate between the filling of pre-existing defects and the generation of new charge trap sites. MOSFETs used in these experiments are n-channel with 1 nm HfO2/1.5 nm HfSiO (60% silicate) stack film grown by atomic layer deposition (ALD) on top of 1 nm chemically grown SiO2, formed by an O3-based oxidation of the Si substrate surface (IMEC clean). The dielectric stack has an equivalent oxide thickness (EOT), extracted by fitting the C–V curves with the CVC model [18], of 1.72 nm. The devices were subjected to post deposition annealing (PDA) at 600 °C in O2. The metal gate, physical vapor deposited (PVD) TaN layer, is capped with 100 nm of polysilicon. The measurements reported in this paper were performed on transistors with 10 lm gate width and 0.35 lm gate length at room temperature by using a Keithley 4200 semiconductor characterization system. The degradation behaviour of these transistors was evaluated by uniform and non-uniform charge injection along the channel, by applying CVS and hot carrier stress, respectively. In order to investigate the effects of the two stress conditions, the devices were biased with positive VG, source and body grounded and VD = 0 V or VD = VG during CVS or HCS, respectively. Initially, drain current, ID, and transconductance, Gm, were monitored as a function of gate bias, VG, on fresh device. Then the transistor was stressed for 100 s at various CVS, VG ranging from 2 to 3 V, and hot carrier stress, VG = VD ranging from 2 to 3 V. After each stress,
2
I. Crupi / Microelectronic Engineering 86 (2009) 1–3
Fig. 1. Schematic picture representing the cold and hot carriers injection during hot electron stressing on n-MOSFET.
and successive sensing, a non-destructive negative gate bias (VG = 2 V, 100 s) with all other terminals grounded was applied to allow electron detrapping. After CVS, Fig. 2a, ID–VG, and corresponding Gm–VG, curves indicate that electrons can be reversible trapped and detrapped on preexisting defects. When the same gate bias is simultaneously
applied to the drain electrode, HCS leads not only to an irreversible shift of both sets of curves but also to their degradation, Fig. 2b. During HCS both cold and hot carriers can be injected in the dielectric stack and contribute to the degradation of transistor performance. Even, it is not easy to separate the effects of the two types of carriers, these results show that the cold carrier contribution is reversible, after the detrapping process the ID–VG curve returns to the expected value (dotted lines in Fig. 2a), while hot carrier effect damage is permanent, it cannot be reversed by application of the detrapping bias after the stress (dotted lines in Fig. 2b). Fig. 3 shows the difference in the average gate current, IG, during the cold (VG = Voltage) and hot (VG = VD = Voltage) stressing conditions discussed in Fig. 2. As can be seen, the gate current is always higher in the HCS case. This result is expected due to the hot carrier contribution that is added to the cold carrier one. In the CVS regime, IG increases with the applied voltage due to a smaller barrier height for cold electrons. Under hot stressing conditions, the average gate current initially increases strongly respect to the CVS case and then slightly decreases. In such a situation, new traps are generated in the system, as experimentally confirmed by the
Fig. 3. Average gate current, IG, during 100 s of cold (VG = V) and hot (VG = VD = V) stressing conditions.
Fig. 2. ID–VG and corresponding Gm–VG curves measured, with VD = 50 mV, before and after 100 s of: (a) CVS, VG ranging from 2 to 3 V with 0.2 V step, (b) HCS, VG = VD ranging from 2 to 3 V with 0.2 V step. The curves shift toward larger VG values by increasing the bias stress. The dotted lines are measured after the de-trapping process, 100 s with VG = 2 V, applied after each stress cycle.
Fig. 4. Maximum transconductance, GmMAX, and the subthreshold swing, S, degradations after the CVS (close and open circles, respectively) and the HCS (close and open triangles, respectively) of Fig. 3.
I. Crupi / Microelectronic Engineering 86 (2009) 1–3
degraded ID–VG characteristic measured immediately after the HCS. In fact, even after detrapping event, a given amount of the injected electrons remains trapped in these new sites, repels further incident electrons and causes reduction in IG as the voltage increases. Hot carriers generate significant damage on the device, while cold carriers do not. These conclusions are supported by the variation of the maximum transconductance, GmMAX, and the subthreshold swing, S, shown in Fig. 4. The data are extracted from the curves reported in Fig. 2a and b. The difference between CVS and HCS effects is evident. The curves slightly increase with the bias in the CVS case. The absence of significant degradation in the cold stressing experiments indicates that only electrons trapping in pre-existing defects play a role. In contrast under hot stressing conditions, significant and irreversible change in both the transconductance and the subthreshold swing of the devices was measured. The above results reflect the generation of new charge trap sites. Moreover, in order to explore the position of generated traps during channel hot carrier stress, the transfer characteristics of the device were even measured in the reverse (source and drain interchanged) mode of operation. There was no asymmetry in the threshold voltage values read at the two sides of the channel region indicating that, even after hot carrier stress, the damaged region is not confined to the drain corner but is expanded to the source region. In conclusion, charge injection and new traps generation under constant gate voltage and HCS were investigated on n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate electrode. Electrical data show the filling of pre-existing traps during CVS and the generation of new charge trap sites in the dielectric or at the interface during HCS. In all the cases, a quasi identical threshold voltage value was read at the source and at the drain side of the transistor suggesting that the damaged region is not localized but is expanded along the entire channel.
3
Acknowledgments The author would like to gratefully thank G. Groeseneken and IMEC high-k team for the sample provision and useful discussion. References [1] International Technology Roadmap for Semiconductors, see