Hot-carrier injections in SiO2

PII:

Microelectron. Reliab., Vol. 38, No. 1, pp. 7±22, 1998 # 1998 Elsevier Science Ltd All rights reserved. Printed in Great Britain 0026-2714/98 $19.00 + 0.00 S0026-2714(97)00179-0

REVIEW PAPER HOT-CARRIER INJECTIONS IN SiO2 D. VUILLAUME Institut d'Electronique et de Micro-eÂlectronique du Nord (IEMN)-CNRS, ISEN-Dept of Physics, Avenue PoincareÂ, BP69, F-59652 cedex, Villeneuve d'Ascq, France

A. BRAVAIX and D. GOGUENHEIM Laboratoire d'Etude en MicroeÂlectronique et MateÂriaux de l'ISEM (LEMMI), Institut SupeÂrieur d'Electronique de la MeÂditerraneÂe (ISEM), Maison des Technologies, Place Georges Pompidou, F-83000, Toulon, France (Received 9 June 1997) AbstractÐWe review the hot-carrier injection phenomena in gate-oxide and the related degradation in silicon MOSFETs. We discuss the basic degradation mechanisms and the nature of the created defects by carrier injections through the gate-oxide. Emphasis is put on the discussion of dynamic hot-carrier injections in MOSFETs and on the stress induced leakage currents in very thin (<05 nm) gate-oxide. # 1998 Elsevier Science Ltd.

oxide and at the silicon±silicon dioxide interface. Section 6 focuses on the important topic of stress induced leakage current (SILC) and Section 7 is a brief discussion of hot-carrier degradation in sub100 nm MOSFETs.

INTRODUCTION

The hot-carrier reliability of silicon MOSFETs has been the subject of intense investigations for a long time. With the scaling down of FET device dimensions and corresponding decrease in supply voltages, this interest has not been denied since new technological processes or design rules (e.g. nitrided oxide, new drain architecture, etc.) have been investigated. As we gained more and more understanding of DC carrier injections, more complicated dynamic AC carrier injections were also conducted to more closely predict hot-carrier reliability in real digital MOSFET circuits. Decreasing the gate-oxide thickness has also led to new phenomena such as stress induced leakage current (SILC) which may be more detrimental than usual phenomena (e.g. gateoxide breakdown) in sub-250 nm E2PROM memory. In this paper, we review the hot-carrier injections in gate-oxide and the related degradation in silicon MOSFETs. We discuss the basic degradation mechanisms and the nature of the created defects by carrier injections through the gate-oxide. Emphasis is put on the discussion of dynamic AC hot-carrier injections in MOSFETs and of the stress induced leakage currents in very thin (<05 nm) gate-oxide. Sections 2 and 3 describe the basic degradation phenomena in n- and p-channel MOSFETs, respectively. In Section 4, we review the recent results concerning AC hot-carrier injections in both n- and p-channel MOSFETs. Section 5 deals with a discussion of the basic mechanisms of hot-carrier induced defect creation and of the microscopic nature of the created defects in the

HOT-CARRIER INJECTIONS IN N-MOSFETS

The damage induced in n-channel MOSFET is maximum when hot-carrier injections (HCI) are done at the maximum of the substrate current ISUB, i.e. for gate (VG) and drain (VD) biasing conditions satisfying VG1[VD/3 ÿ VD/2] [1±4]. In the gate voltage range VG
8

D. Vuillaume et al.

tron traps are created (vide infra), which complicates the interpretation. Recently, Doyle et al. have shown that a unique power law (regardless of the stress voltage condition) with an exponent of about 0.5 is observed when the degradation is measured as a function of the injected charge instead of time [6]. This is true at low VG if the oxide trap (both positive and negative) contribution alone is extracted out from the rest of the degradation [6]. A short electron injection (SEI) (typically 10± 100 s at VG=VD) applied after a long-time HCI is sucient to induce a signi®cant new degradation of VT or Gm [2, 4, 7]. However, the same SEI applied on an unstressed MOSFET is unable to induce the same shift. Thus, this post-aging e€ect is clearly related to the damage already induced in the MOSFET by the previously performed long-time aging. This additional degradation revealed by the SEI can be erased by a short hole injection (SHI) (at VG=VD/4, for instance) which returns the ID± VG curve to its post-aging value. Bourcerie et al. have shown that a monochromatic light, with photon energies greater than about 3 eV, or a suciently high ®eld through the oxide, are also able to restore the post-aging situation [8]. Figure 1 shows that this SEI e€ect is only observed when HCI has been performed at low VG [4]. For HCI performed at maximum ISUB, the slope n 1 0.5±0.7 of the power law is clearly due to the creation of fast interface states. The oldest model relates this slope to the creation of interface states by electrons having energies (relative to the bottom of silicon conduction band) of 3.7 eV and above [1]. This threshold energy and the observed time dependence have been explained by a model involving the breaking of Si±H bonds by hot-carriers [1]. Another approach [3, 9] suggests a process in which holes and electrons are both and successively involved, via the so-called ``two-step process'' [10]. In this model, the holes are trapped very close to the interface (typically within less than 3 nm), and the subsequent electron trapping on previously trapped holes triggers the generation of interface states (vide

Fig. 1. The threshold voltage shift measured immediately after the HCI and after a subsequent short electron injection phase (SEI) are compared. HCI conditions are: VD=8.5 V during 4  104 s. SEI conditions are: VG=VD=8.5 V during 100 s.

infra, Section 5). However, this ``two-step'' model was neither clearly con®rmed nor clearly invalidated from hot-carrier experiments in MOSFET. Thus, a physical model to explain the time power law exponent of 0.5 is not ®rmly established. From charge pumping (CP) measurements, the generation rates of interface states (number of interface states per injected carrier) were found to be Git,e110ÿ7±10ÿ6 and Git,h110ÿ3±10ÿ2 for a generation by hot electrons and hot holes, respectively [2]. These values should only be considered as an order of magnitude, and they should depend on the injected charge at which they are measured, albeit the general trend, Git,h>>Git,e, is always true. At low VG, the hot holes which are injected into the oxide, lead to hole trapping on pre-existing donor-like oxide traps. The hole trapping probabilities have been estimated to be about 0.1±0.5 from CP measurements [2]. The resulting positive charge inside the oxide reduces the e€ective VT shift induced by the interface states. According to this model, the additional positive VT shift observed after a subsequent SEI (Fig. 1) is due to the whole interface state density because the positive charges have been neutralized by the SEI. However, other groups have also suggested that the largest positive VT shifts measured after the SEI could also be due to electron trapping on acceptor-like oxide traps generated during the previous HCI at low VG [4, 11, 12]. In some technologies, it was observed that the generation rates (number of traps per number of injected carriers) for these electron traps are as high as 10ÿ3±10ÿ2, i.e. of the same order of magnitude as for interface states [7]. For HCI at high VG (i.e. VG1VD) only electrons are injected into the oxide [3], thus the interface state creation is weak. However, some groups have also reported a large degradation induced by this hot electron injection (HEI) [6, 13±16]. The VT shift observed after HEI could be of the same order of magnitude (or even larger for some technologies) as after an aging at low±medium VG range. This degradation comes from electron trapping on oxide defects which either pre-existed or which are created by the HEI itself. This degradation is also characterized by a time power law Atn where n is typically equal to 0.2±0.3. Again, Doyle et al. have recently observed [6] an exponent of 0.5 in this case, when the degradation is analyzed versus the injected charge instead of time as usual. In this latter case, they explain the reduced time exponent as due to Coulombic repulsion induced by the trapped electrons. From CP technique [7, 12] the generation rates (number of traps per injected carrier) under HEI at VG=VD are found to be of the order of 10 ÿ9±10ÿ8 [7]. Due to this low rate, longer stress durations are needed to observe them. Even more signi®cant is the fact that the electron gate current IG decreases with this electron trapping as revealed by measuring the whole IG±VG characteristic

Hot-carrier injections in SiO2

9

Fig. 2. Behavior of the gate current measured by the ¯oating gate technique for di€erent stress times (0, 10, 102, 103, 104). (a) HCI at VG=VD/2 (mainly creation of interface states); (b) HCI at VD=VG (mainly electron trapping).

(Fig. 2) using the very sensitive ``¯oating gate'' technique [17±20]. The main deformation is a decrease of the whole IG±VG curve with a maximum gate current always peaking at the same VG value [21]. This behavior has been ascribed to an increase in the amount of negative charges in the oxide, acting as a repulsive barrier for a further injection of electrons. In the case of the creation of interface states alone, it was shown that the deformation of the IG± VG curve is only a decrease of IG in the saturation part of the curve (VG>VD), while the linear part is una€ected (Fig. 2). This is because the charge stored on the interface states varies as a function of the Fermi level position during the FG measurement [19, 20]. Shrinking the device dimension, MOSFETs still operate at high lateral ®eld conditions scaling down the channel length and gate-oxide thickness even with reducing the supply voltage from 5 to 2.5 V [22]. A great number of design innovations has been proposed to account for the trade-o€ required between transistor performances and hot-carrier reliability. Lightly Doped Drain (LDD) devices are largely used in the 1±0.35 mm range to reduce the lateral ®eld (Elat). An nÿ region underneath a spacer oxide connects the channel to the highly doped (n+) junction. This structure requires a precise optimization of the nÿ concentration and overlap length between the channel and the n+ junction to reduce Elat while maintaining a high current drivability. Regarding the HCI problem, it is known that the LDD structure is damaged by a combination of an increase in the series resistance in the LDD region and a reduction of the carrier mobility in the channel and subdi€usion region [23, 24]. In LDD

devices the degradation behavior is extremely dependent on the doping of the nÿ region where, for a highly doped nÿ region, the lateral ®eld is not suciently decreased leading to a close correlation between the interface trap generation and the I±V shifts in a similar way to that in conventional devices. In contrast, for the low doped nÿ region, the device su€ers from the increase in series resistance due to the negative trapped charges and/or interface trap generation above the nÿ region in gate to drain overlap region. These e€ects lead to a strong saturation in the time-dependence of the degraded I±V parameters where the n-exponent becomes dependent on the stressing Elat and measurement conditions VG, VD [23]. The LDD degradation behavior is also strongly dependent on the type of induced damage, especially when the build-up of negative charge occurs (at VG=VD) in the spacer [7] which leads to an enhanced series resistance increase and drive current degradation. To avoid these limitations numerous alternative device structures have been proposed as LATID [25], inverse-T gate [26], DDD [27] and GOLD [28] in which the gate overlaps the nÿ region. For these novel technologies, complex processing is required and the hot-carrier degradation is not totally suppressed [29] while important drawbacks appear as increased gate overlap capacitance, channelling or shadowing e€ects [25]. A new fully overlap device (FOND) structure has recently been proposed [30] showing similar current drivability and a higher hot-carrier resistance than in LDD devices. Although a 10% loss is observed in speed performance for these 0.25 mm length devices, they exhibit many more improvements in device lifetime than

10

D. Vuillaume et al.

standard LDD devices. Thus, this process is a promising technology for deep-submicrometer devices.

HOT-CARRIER INJECTION IN P-CHANNEL MOSFETS

With the down-scaling of CMOS technologies, the hot-carrier reliability of p-channel MOSFET has also drawn considerable attention [2, 3, 31±53] with the strong reduction of the channel length and gate-oxide thickness. As in n-channel MOSFETs, the substrate current is maximum at around VG1VD/3, but is now made up of the electrons generated by impact ionization near the drain. The gate current in p-channel MOSFETs is the counterpart of that in n-channel MOSFETs. The electron gate current is maximum at low negative voltage VG, around VG=VD/4, for which the vertical oxide ®eld favors electron injection. In principle, the hole injection is maximized at higher negative VG values (i.e. for vVGv r vVDv), albeit a hole gate current was never measured in this range of gate bias in devices with channel lengths down to 0.5 mm, even by the very sensitive ¯oating gate technique. At low gate voltages (around the peak gate current) a large amount of electrons are injected in the oxide and the main degradation is electron trapping in the oxide [2, 32, 34, 41, 48±53]. The growth of this net negative charge induces an increase in the absolute value of the drain current and in the transconductance. Interface states are also generated as shown by CP measurements, but their e€ects on device parameters are masked by the large amount of trapped electrons. Consequently, the time-dependent laws for DVT, DID/ID or DGm/Gm never match that of interface state creation [2]. For all stress gate voltages, IG decreases due to this electron trapping and due to the electric ®eld reduction. Figure 3 shows that the degradation is correlated with the peak gate current instead of being correlated with the substrate current as is the case in nchannel MOSFETs [33, 37, 41, 47]. Several degra-

Fig. 3. Correlation between the amount of degradation in p-MOSFET and the gate current. Degradation has been monitored through Vt shift, and increase in the charge pumping current.

Fig. 4. Logarithmic time-dependence for p-MOFETs DC stressed at the condition of maximum gate-current (VG/ VD10.2) which can be modeled as a function of the time constants tVD expressed as DGm/Gm0C1 ln(t0/tVD) ln(t/ tVD) with t0 extracted from the insert and the constant C1 a technology-dependent factor (Le€=0.3 mm, Tox=7 nm).

dation models have been presented [43, 48, 50, 51] to analyze the main degradation mechanism in pMOSFETs as the trapping of negative charges extending from the drain. This electron trapping induced a channel shortening e€ect also leading to a reduced punchthrough voltage which was initially called the Hot Electron Induced Punchthrough (HEIP) mechanism [48]. Most of the results agree with a logarithmic time-dependence (Fig. 4) for the growth of the damage region [43, 50±52] which can be described by the spatial occupation of pre-existing traps at relatively low oxide ®elds and low amounts of injected charge. In contrast to the degradation in n-channel devices, the worst-case of degradation in a p-channel device is closely correlated to the electronic gate current at low VG. Taking into account the spatial dependence of the gate current density and its change during DC stress, a question remains as to whether the negative oxide charge formation saturates including electron detrapping [43, 50], or does not saturate taking into account the integration of the charges and their distribution along the channel [51, 52]. The ®rst approach [43, 50] pointed out that on the one hand, one cannot neglect the electron detrapping mechanism in p-MOSFETs because not all existing traps can be occupied through the exponential decrease of the injection current with distance from the drain, and on the other hand, one has to distinguish the oxide ®eld dependence between the ®lling of pre-existent traps from the generation of new traps induced by the impact ionization mechanism, as these created traps can only be occupied during an additional phase at low oxide ®elds [43]. The second approach [51, 52] pointed out that the oxide charge formation exhibits a square-root dependence with the channel-shortening with no saturation e€ect. Using charge-pumping measurements, this latter result has been modeled by the spatial dependence of the damage with the amount of injected

Hot-carrier injections in SiO2

Fig. 5. Time-dependence at the voltage condition of holeinjection (VG=VD) corresponding to the interface trap generation which induces a net reduction of DGm/Gm. The degradation follows a time power law with an exponent 0.46 at high lateral ®eld.

charge assuming an oxide-charge trapping limited by Coulomb repulsion [51]. At VG1VD, the hole injections should in principle be favored, albeit a hole gate current has never been measured in transistors down to 0.5 mm. At this stress condition, a weak generation of interface states has been observed using charge pumping measurements [2, 47]. However, with scaling down the device dimension and the gate-oxide thickness, the generation of interface states becomes much more signi®cant [2, 40, 42, 47] as shown in Fig. 5. This causes a decrease of Gm and a reduction of the absolute value of the drain current. The build-up of positive charge due to hot hole injections has also been revealed in 0.4±0.25 mm channel length pdevices with 6±10 nm thick gate-oxides [36, 52]. The in¯uence of both degradation mechanisms is strongly dependent on the electric ®eld but also on the device processing as the positive trapped charges have been observed only in surface-channel p-MOSFETs with standard gate-oxide or with nitrided (N2O) gate-oxide used to improve the gate dielectric against oxide damage. Surface-channel (SC) MOSFETs with a p+ polysilicon gate have been introduced [40, 53] to circumvent short-channel e€ects, punchthrough and the need of the threshold voltage implant as in n+ polysilicon gate pMOSFETs [called buried channel (BC) MOSFETs]. SC p-devices are generally more resistant to hotcarrier induced degradation than BC p-devices [40, 41] which makes this type of p-MOSFETs the best candidate for reliable deep-submicron technologies.

DYNAMIC HOT-CARRIER INJECTIONS

In digital circuits, MOSFETs no longer operate in DC conditions. Therefore dynamic hot-carrier injection e€ects are also of great interest [54±76]. A basic question is whether the AC degradation can or cannot be predicted from DC experiments. If the

11

answer is yes (quasi-static case, QS) the reliability under AC conditions can be correctly analyzed by a set of DC experiments, provided that all static degradation e€ects are taken into account in the appropriate way. The task is not straightforward because in AC operation mode the waveforms applied to the gate, drain and source electrodes continuously switch the transistor between con®gurations in which hot holes or hot electrons or both are injected into the oxide, leading to a repetitive succession of di€erent degradation mechanisms (the precise voltage conditions depend on whether we work on p- or n-MOSFET) [69]. Thus, we must analyze a large number of DC stress con®gurations to be able to correctly predict the AC degradation. Moreover, several speci®c questions must also be answered. First, what happens when holes have been injected and got trapped in the oxide, and when electrons are then injected and can recombine with the trapped holes? From earlier studies in MOS capacitors, we know that this can lead (or not) to the creation of additional interface states depending on the location of the trapped holes (vide infra). Another question is the in¯uence of detrapping (homogeneous or localized) and cold periods that may occur during the subsequent AC periods, only taken into account in DC experiments by poststress e€ects. What happens when these detrapping e€ects occur during the stress [70]? Moreover, some con®gurations may lead to a bidirectional degradation (at both drain and source side) which may have severe in¯uence, as the channel shortening e€ect in p-MOSFETs [49]. The QS scheme [69, 70, 76] assumes that, if no transient e€ect does occur, the damage under dynamic stress conditions can be completely described as being the sum of the degradations induced independently by each degradation mechanism occuring repetitively during the period T. This can be roughly interpreted in the calculation of the QS lifetime tQS by multiplying the DC damage (represented by the inverse of the DC lifetime tDC,i) for each mechanism i by a duty cycle factor taking into account the e€ective period Ti during which the ith mechanism is e€ective at each cycle. The total QS lifetime being inversely proportional to the damage is obtained by summing individual lifetimes in the following way (Mathiessenlike rule): X 1 Ti 1 ˆ : …1† tQS tDC-i T i A series of careful DC experiments for bias conditions corresponding to each identi®ed degradation mechanism is required to extract the DC lifetimes tDC,i from lifetime plots: 1 tDC-i

ˆ

…mi † 1 I SUB …m Ci w I D i ÿ1†

…2†

12

D. Vuillaume et al.

where the substrate current ISUB is used to monitor the hot-carrier degradation. In some cases, however (like in electron injection conditions), the gate current IG will be a better monitor and will replace the substrate current in Equation (2). Using a careful extrapolation technique, we also extract with minimal scattering for each degradation mechanism the constant and exponent (Ci, mi), and we attribute closely each value to the di€erent voltage regions. The transistor parameter used to follow the degradation (drain current, transconductance, threshold voltage, charge-pumping current) may also in¯uence the values of (Ci, mi) and must be chosen for their sensitivity regarding the expected damage induced by the bias conditions related to each degradation mechanism. From the measured ID(VG, VD) and ISUB(VG, VD) values, and the determination of VD(t) and VG(t) curves during the AC stress sequence, we can extract the ID(t), ISUB(t) and IG(t) curves. Figure 6 shows the AC stress sequences corresponding to the inverter-like [Fig. 6(a)] and SRAM-like cases [Fig. 6(b) and (c)] and the corresponding curves of ID, ISUB or IG versus time. For the inverter-like case, Fig. 6 shows that the hot-carrier degradation is almost entirely concentrated during the rising edge of VG(t), and for the SRAM-like case, a clear enhanced hump in ISUB appears when the drain delay increases, corresponding to the electron injection period. A more precise QS evaluation of the lifetime tQS is then possible by calculating the avermi ÿ1 i † for each period age value of …1=Ci w†…I m SUB =I D Ti corresponding to the ith degradation mechanism, and is given by: ! … …mi † X 1 I SUB 1 1 ˆ dt : …3† i ÿ1† tQS Ci w T Ti I …m i D A practical way to check the validity of the QS approach is to perform ``constant pulse shape'' experiments, which means that when the period of the pulse is varied, the rise and fall times are changed proportionally to maintain a constant duty cycle ratio for each mechanism. In these conditions, the monitoring of the damage will be essentially independent of the frequency used provided that QS requirements are satis®ed [70]. Several results have been reported which have led to several controversies. Typically, it was often observed that AC injections induce a more pronounced degradation than DC injection [55±62]. However, precautions (use of external capacitances and extra grounding as close as possible to the device under test) must be taken for the measurement set-up in order to avoid an abnormally enhanced degradation resulting from extra transient voltages on the drain or the gate, because of capacitive and inductive overshoots [63]. Using these precautions, no transient e€ect on hot-carrier formation and injection during voltage edges has

been observed for frequencies up to 100 MHz and rise/fall times down to 3 ns in MOSFETs with channel length down to 0.5 mm [49, 68±71]. This does mean that device-related dynamic e€ects can be neglected for the interpretation of dynamic stress data, and cannot account for any enhanced AC hot-carrier degradation. On the other hand, some research groups have found that AC injection does not induce a more pronounced degradation [55, 57, 64], or even cause a reduced

Fig. 6. Drain and gate voltage waveforms used during AC stress to mimic the biasing conditions encountered by nchannel MOSFETs in inverter (a) and SRAM (b, c) circuits and the resulting drain, substrate (a, b) and gate (c) currents.

Hot-carrier injections in SiO2

degradation [65]. Some basic phenomena have been investigated [58, 66]. After holes have been injected into the SiO2 during the low gate voltage part of the AC stress waveforms (see in Fig. 6 the inverterlike waveform), they move slowly by hopping between neighboring oxygen atoms, with a mobility of the order of 2  10ÿ5 cm2 Vÿ1 sÿ1 [77]. Consequently, they require 10 ns to drift over 1 nm at a ®eld of 0.5 MV/cm across the oxide. In the inverter-like case, the degradation is almost entirely concentrated during the rising and falling edges of the waveform, and more precisely during the rising edge of the gate voltage, the drain voltage being high. So, if the frequency is high enough (rise or fall times less than 10 ns) and then if the holes do not have time to drift and get trapped by deep hole traps in the oxide, they are pushed back to the interface during the period corresponding to the high gate voltage and low drain voltages [see the waveform in Fig. 6(a)]. Thus, they no longer contribute to the device degradation. On the contrary, during SRAM-like conditions, the positive VD [see Fig. 6(b)] pushes the holes towards the gate. The holes could be eciently trapped in the oxide leading to an enhanced degradation. After being injected and trapped in the oxide, carriers can be detrapped either by tunneling back into the silicon [58] or by ®eld-enhanced emission [8]. This occurs when a gate voltage is applied with the drain voltage equal to zero (the inverter-like waveform is a typical example). Such e€ects have been clearly observed in the case of hole injection/trapping in nchannel MOSFETs and electron injection/trapping in p-channel MOSFETs at low gate voltages [66]. The detrapping of trapped electrons seems a very ecient mechanism in prolonging the lifetime of pMOSFET under AC stress. In n-channel MOSFETs, the AC degradation for transfer gate con®guration (SRAM-like) ®rst showed no enhanced degradation compared to the inverter-like con®guration, provided that the same gate frequency was used and although the degradation is bidirectional in the transmission gate con®guration and unidirectional in the inverter-like one [49]. In the transfer gate, the degradation is essentially symmetrical at drain and source sides, leading to approximately equal degradations for linear- and saturation-mode parameters. It means that in nchannel MOSFETs, half of the induced damage at the drain and half the induced damage at the source in the transfer gate con®guration have almost the same e€ect as the whole damage at the drain in the inverter-like con®guration. Anyway, an enhanced AC hot-carrier stress damage was further evidenced with respect to damage under DC stress conditions [69, 70] and it was shown that in the transfer gate mode, the device degradation may exhibit in some cases a strong dependence with the propagation delay, clearly di€ering from the simple case of inverter operation [76]. To explain this enhanced

13

damage during AC stress, it was often observed that a brief electron injection following a period of hole injection resulted in an increased degradation in a non-quasi-static way (vide supra, Section 2), i.e. di€ering from the simple sum of the independent degradation induced by both mechanisms [2, 4, 7]. Such a situation is typically encountered during the AC stress (see the inverter-like and SRAM-like waveforms in Fig. 6). Two models can explain this behavior. In the ®rst model [66], the injected electrons neutralize the previously trapped holes. Since the positive charges in the oxide reduce the longitudinal electric ®eld and slow down further hole injection, when the trapped holes are neutralized by electron injection during AC stress, the longitudinal ®eld is restored, and a further hole injection at low gate voltage is possible again during the next period. In the case of DC stress this neutralization does not occur. This e€ect leads to an increased AC degradation. The second model states that neutral electron traps are created by the hole injection [4, 7, 11, 45] (vide supra, Section 2). These neutral traps are then ®lled during the electron injection at high gate voltages, which could explain the observed enhanced degradation. The overall AC degradation is then dependent on the sequence in which the di€erent degradation conditions are applied. Taking into account the three mechanisms: the creation of interface states at low and medium gate voltages, the creation of oxide electron traps at high gate voltages and the creation of oxide electron traps at low gate voltages, the AC stress degradation under various waveforms (SRAM, inverter) has been fully predicted from DC stress experiments [67, 69]. However, it is pointed out that alternating stress conditions are required for some of the damage to be exposed, which cannot be predicted by a quasi-static approach. An apparently nonquasi-static behavior in n-channel MOSFETs which are dynamically stressed with conditions that favor hot hole injection was also further observed [70]. This has been ascribed to a ``post-stress'' e€ect occurring during the cold or detrapping periods between the pulses, and related to the presence of a net positive trapped charge. It was argued that even this behavior could be predicted on the basis of static degradation, provided it was followed by a poststress period. It can also be concluded that, taking into account these speci®c DC experiments, the QS approach provides in many cases for n-channel MOSFETs an accurate estimate for AC stress lifetimes [69, 70]. The AC degradation in p-channel MOSFETs has recently gained new interests, especially for advanced LDD CMOS technologies [49, 53, 71]. Some studies reported a quasi-static degradation behavior taking into account detrapping e€ects [49, 70], while other studies found non-quasi-static degradation results [72] partly explained by transient e€ects [73]. On the one hand, the quasi-static

14

D. Vuillaume et al.

behavior can ®rst be checked when no excess substrate current occurs during overlap time between VGS and VDS pulses or using constant pulse shape experiments [70]. On the other hand, the quasi-static behavior (i.e. AC results independent of the frequency) is primarily dependent on the measurement criterion, that means if charge-pumping or I±V parameters are chosen to monitor the distinct degradation mechanisms during AC operation. Indeed, as in n-channel MOSFETs, post-stress degradation has a net in¯uence in p-channel MOSFETs where not only the interface trap generation still increases when VG, VD are switched o€ after stress [70], but also where the charge detrapping mechanisms contribute to much less impact of the usual electron trapping induced channel shortening and improve the lifetime of the transistor [70, 74]. Because this latter e€ect represents a critical problem for the hot-carrier reliability of p-MOSFETs, the degradation of transmission gate has been investigated [49, 71] as it represents the worst-case of hot-carrier degradation during digital operation. In that case, the bidirectional degradation, i.e. at each terminal, induces a severe channel-shortening e€ect leading to an enhanced AC degradation compared to DC results. Although design modi®cations may relax this hot-carrier problem in pass-transistors (of SRAM cells) or in complementary switches, the charge detrapping and interface trap generation will have a larger impact on the transistor with very thin gate-oxide [74]. During the detrapping of ®xed negative charges, the interface trap generation still increases which leads to Gm and ID reductions observed during pass-transistor operation as a function of the delay (Fig. 7). For constant rise time, i.e. for a ®xed build-up of negative charge, the period for interface trap generation increases roughly with the delay inducing a reduction of the

detrapping phase. For short delay, the detrapping eciency remains large enough during the subsequent phase to suppress the in¯uence of electron trapping in thin gate-oxide leaving the interface trap in¯uences at long term [75]. The resulting AC degradation is thus strongly dependent on the competing in¯uences of these distinct degradation mechanisms [74, 75]. Based on this knowledge, the evaluation of the lifetime for p-channel MOSFETs can be obtained once the waveform is known for a given AC operation. Each digital functioning has to be considered, where for most of them (inverter-, DRAM-, ROM-like) the overall AC degradation is composed of the di€erent contributions at the conditions of maximum degradation (duty cycle calculation) [71]. For some speci®c cases (pass transistor, diode-connected transistor), charge detrapping and post-stress e€ects have to be taken into account for the determination of the hot-carrier reliability in pMOSFETs. For future technologies with very thin gate-oxide, the detrapping will be a combination of both ®eld assisted thermal discharge of ®lled traps and of detrapping by a tunneling mechanism which will be of much more importance than the detrapping of holes in n-MOSFETs. Attempts have already been made to introduce a QS-like approach in reliability simulators to predict by simulation the circuit speed degradation from a given set of DC stress data [71]. For more complex circuits, the degradation is generally monitored by a shift in frequency (in ring oscillators) or in increase in the propagation delay (in a latch or a multiplexor). The accuracy of the AC prediction remains very dependent on the pertinence of the monitor used to follow the degradation in DC experiments, from which all parameters used in the AC simulation are extracted. Of course, in CMOS circuits, both n- and p-MOSFETs have to be considered simultaneously and some empirical rules can be established to roughly predict speed degradation and AC lifetime only depending on a few parameters of the AC waveform like rise/fall times and their ratio [71]. This can in¯uence design rules allowing a very early evaluation of the overall hotcarrier reliability of the circuit.

MICROSCOPIC NATURE AND CREATION MECHANISMS OF DEFECTS INDUCED BY HOTCARRIER INJECTIONS

Defects created at the Si±SiO2 interface Fig. 7. Linear transconductance change during Tpass stressing for 0.25 mm (Vhigh= ÿ 5.25 V) and 0.5 mm (Vhigh= ÿ 6 V) p-devices. The frequency (fAC=1 MHz) and the rise/fall time (50 ns) are kept constant and the delay is varied leading to a constant hot-electron injection period (TNox120 ns) and to the increase in the interface trap generation period (TNit when VG=VDS=Vhigh) and the corresponding reduction of the detrapping phase (TDet when VGS=Vhigh, VS=VD=0).

The basic intrinsic defect at the h111iSi±SiO2 interface is the so-called Pb center, a three-fold coordinated Si dangling bond defect noted Si3/Si. [78]. At the h100iSi±SiO2 interface the picture is complicated by the existence of two Pb centers which are physically and chemically di€erent [79]. According to Poindexter's model [78], the microscopic model for the so-called Pb0 center is Si3/Si.,

Hot-carrier injections in SiO2

and that of the Pb1 center is Si2O/Si. [79]. However, this structural identi®cation of the h100iPb centers has been criticized [80, 81]. In state of the art devices, these defects are passivated by hydrogen. Thus the main question is: ``do the hotcarrier injections depassivate the Pb centers or do they create new types of defects?'' Most of the results reported so far have been obtained using homogeneous HCI in large size MOS capacitors or transistors (avalanche injection, Fowler±Nordheim injection), because the most powerful technique which unambiguously allows us to determine the microscopic nature of the defect is the electron spin resonance (ESR) technique which needs large area devices. The determination of the nature of the created defects by any electrical technique alone is a very dicult task [82]. Recently, a variation of this ESR technique has been successfully applied to small geometry MOSFETs [83±86]. This technique, named Spin-Dependent Recombination (SDR) or Electrically Detected Magnetic Resonance (EDMR) [87±96], has shown that Pb centers are indeed created in small transistors by HCI at low VG [84, 95] and in some cases by homogeneous electron injections, depending on the mechanisms (vide infra) of interface state creation [85, 86, 93]. Positive charges also appear at the Si±SiO2 interface upon electron injection when the oxide ®eld is suciently large (over 7 MV/cm) [97, 98]. These positive charges are mainly located within the ®rst 3 nm from the Si±SiO2 interface [99]. These positive charges have been related to donor-like defects located in the oxide close to the Si±SiO2 interface. Since they can exchange carriers with the Si substrate via a tunnelling mechanism, they are also called slow interface states (or border traps [100]). Their capture and emission time constants range from a few milliseconds to a few hundred seconds. These border traps can be characterized by various techniques derived from those used for the fast states: Tunnel-Deep Level Transient Spectroscopy (Tunnel-DLTS) [101, 102], and charge pumping [103]. A linear correlation has been found between the concentration of the slow and the fast interface states created by HCI [104]. This suggests that there exists a similarity in the physico-chemical nature of these defects and in their creation mechanisms. Two basic models have been devised to explain the creation of defects at the Si±SiO2 interface upon carrier injection. The role of hydrogen species (hydrogen-related species di€usion, HRS model) has been clearly established [104±109]. Hot electrons entering the oxide gain sucient energy, accelerated by the oxide ®eld, to release some hydrogen species present in the oxide or at the anode±oxide interface. These species (especially protons) di€use across the oxide and when they pile up at the Si±SiO2 interface, they create interface defects according to the following type of chemical reactions: PbH + [H] 4 Pb+[H*], where PbH represents a

15

hydrogen-passivated Pb center, [H] any form of hydrogen species (H, H+, OH, etc.), and [H*] any form of a combination of [H] with the atomic hydrogen released from the Pb center [110]. More elaborate chemical reactions have also been suggested [111], and the previous relation has to be considered as the general framework. This model is ecient as soon as the oxide ®eld Fox exceeds about 1.5±2 MV/cm [107]. In the second model, historically the oldest one, the degradation is related to the generation of holes by impact ionization (II model) across the 9 eV of the SiO2 band gap [112]. Later this II model was ruled out since the average energy of hot electrons in SiO2 never exceeds 5± 6 eV [113]. More recently, a high energy tail (in the 9±12 eV range) was observed in the energy distribution of the hot electrons in thick oxide (more than 120 nm) at high ®eld (above 7 MV/cm) [97] and the relationship between defect creation and impact ionization was revisited both theoretically and experimentally [97, 114]. It was proved that this model fully accounts for the formation of positive charges and the creation of interface states [97, 98] in oxide thicker than 120 nm. The holes generated by impact ionization in the oxide can be trapped at the Si±SiO2 interface, and when the injected electrons recombine with these trapped holes, interface states are created if the trapped holes are located close to the interface (<3 nm) [10, 115]. The exact nature of this transformation mechanism is not yet clear. This model requires a high electric ®eld in the oxide because hole generation is only possible when the injected carriers have reached the threshold energy for intra-band impact ionization. On the contrary, in the ®rst model, the energy required to depassivate the Pb center is almost the binding energy of the Si±H bond. This energy varies from 10.8 eV to 3.1 eV [116, 117], the lowest value accounting for possible bond weaknesses induced by the local disorder at the interface. Many experiments have been performed to check the respective role of these two mechanisms dealing with the e€ects of injected ¯uences, oxide ®elds, oxide thicknesses and temperature at which injections have been performed [97, 98, 104, 107, 108, 114]. Table 1 summarizes the basic behaviors observed for the HRS model and for the II model. The HRS mechanism is active regardless of the oxide thickness. The II mechanism requires a thicker oxide to allow the electrons to acquire a suciently high energy (Er9 eV) to generate electron±hole pairs [97, 98, 114]. Thus, this latter mechanism requires a large oxide ®eld (Foxr7.5 MV/cm), while the HRS mechanism occurs as soon as the oxide ®eld is larger than about 1.5 MV/cm, leading to electrons with energy larger than about 2 eV at the anode [97, 107]. It was also observed that trap creation by the HRS mechanism is temperature-dependent, activation energies in the range 50 meV to 0.2 eV, while trap creation by the II mechanism is either weakly

16

D. Vuillaume et al.

Table 1. Dependence of the two main degradation mechanisms on oxide thickness, oxide ®eld, injected ¯uences and on that temperature at which the carrier injections are performed. This table should be viewed as a ``road map'' to recognize a degradation mechanism when studying the reliability of oxide ®lms

Oxide thickness Temperature Injected ¯uence Oxide ®eld

Hydrogen-related species (HRS) mechanism

Impact ionization (II) mechanism

No Strong r10ÿ3±10ÿ2 C/cm2 r1.5 MV/cm (or energy larger than 12 eV

Yes (larger than 120 nm) Weak or independent R10ÿ3 ±10ÿ2 C/cm2 r7.5 MV/cm (or energy larger than 19 eV

temperature dependent or independent of temperature [97, 98, 104, 107, 108]. The II mechanism dominates at low injected ¯uences (typically less than 10ÿ3±10ÿ2 C/cm2) and the HRS mechanism appears to be the dominant mechanism responsible for trap creation at higher injected ¯uences [97, 98]. However, this critical injected ¯uence depends on the technology, and a lower value is expected with aluminium gate (as compared to polysilicon gate) since the Al-gate process is known to introduce much more hydrogen into the gate-oxide. It has recently been shown (using EDMR) that only the Pb0 center is created when the trap creation by HRS mechanism dominates [85]. However, the number of created Pb0 centers is too low to account for the whole interface state density measured by electrical techniques (C±V or charge pumping techniques). At ¯uences lower than about 10ÿ3 C/cm2, for which trap creation is dominated by the II mechanism, no paramagnetic signal has been observed while electrical techniques show the ecient creation of interface states. The creation of the other defect, the Pb1 center, has not yet been observed, even when performing the EDMR measurements in a large range of temperatures [86] in an attempt to take into account the di€erence in the carrier capture properties of the two defects, Pb0 and Pb1 [118]. Thus, it is not completely clear at the moment whether the Pb1 center is not created or not observable by the EDMR technique.

dangling bonds) should be created by HCI at low gate voltage [84], in agreement with the conclusions of the electrical experiments. However, more complete EDMR experiments are required to con®rm this E' center creation.

STRESS INDUCED LEAKAGE CURRENT

When the oxide thickness reaches the 5 nm range and below (as is the case in the sub-100 nm devices), electron ¯uences greater than 104 C/cm2 can ¯ow through the gate-oxide without signi®cant charge trapping, or destructive breakdown [120]. This is also illustrated by the fact that a roughly linear relationship (in a log±log scale) was observed between the decrease in the oxide thickness and the increase in the number of injected electrons needed to create a given concentration of defects (Fig. 8) [121]. This is due to the fact that in such thin oxides, carrier transport is mostly ballistic. But in devices with oxide ranging from 3.5 nm to 10 nm, another phenomenon has become more and more detrimental for the reliability and increasingly important for Flash memory ULSI technologies. A huge increase in the pre-tunneling low and very-low ®eld (4±8 MV/cm and 2±4 MV/cm) leakage current was observed through the gate-oxide after the injections under high-®eld stress (>9 MV/cm), the socalled stress induced leakage current (SILC) (see

Defects created in the bulk oxide In Section 2, we discussed the capture of electrons by the oxide traps created by HCI during the long-time aging of MOSFETs. For HCI at low VG (in n-MOSFETs), the created oxide traps exhibit large capture cross-sections, ranging from 10ÿ14 to 10ÿ15 cm2 [119]. Combining photodepopulation spectroscopy and ®eld-enhanced emission time constant measurements, the energy level of these defects has been found between 1.7 and 3 eV [119]. It was also found that the oxide traps created by the hot electron injections at high VG exhibit the same electrical properties, suggesting a similar nature [8, 119]. By comparison with theoretical results, they have been related to the several possible forms of Si dangling bond defects which have been identi®ed in the bulk oxide or near the interface [119]. EDMR measurements have shown that an E' center (an oxygen vacancy, O3/Si..Si/O3, with two silicon

Fig. 8. Number of injected electrons needed to create the same amount of interface state defects as a function of the oxide thickness. Assuming a ®rst order creation kinetic, this quantity is de®ned as the number of injected electrons needed to reach a level of defects of 1/e (with e the Naperian) times the number of defects at saturation.

Hot-carrier injections in SiO2

Fig. 9. Increase in the low ®eld gate voltage current measured for negative gate bias voltages in a MOS capacitor during a high ®eld stress (VG= ÿ 6 V) for an oxide thickness of 5 nm and a gate area of 4  10ÿ4 cm2.

Figs 9±10) [122±154]. Since such high ®elds are present during program/erase operations in Flash memory cells, SILC may have severe consequences on data retention (a 10 year charge retention criterion is generally required), resulting in excessive charge loss from the ¯oating gate, and may be the most limiting factor to tunneling oxide down-scaling below 8 nm [136]. As the comprehension and removing of SILC may be one of the most important issues for ULSI down-scaling, it is crucial to understand the physical mechanisms responsible for these excess leakage currents and their link to the damage induced by the stress within the oxide and at the Si/SiO2 interface. Moreover conventional voltage-ramped time-zero-breakdown (TZB) and time to breakdown under constant current stress (TBD) tests are unable to detect SILC as they operate in the high-®eld or high-current regime [124]. Let us ®rst point out the main features of SILC. SILC has been generated in oxides with thicknesses ranging from 3.5 nm [131, 132] up to 10 nm [136, 138] after di€erent kinds of high-®eld stresses in the Fowler±Nordheim regime using constant-cur-

Fig. 10. Increase in the low ®eld gate voltage current measured for positive gate bias voltages in a MOS capacitor during a high ®eld stress (VG= + 5 V) for an oxide thickness of 5 nm and a gate area of 4  10ÿ4 cm2.

17

rent experiments [141, 146, 151], constant-voltage experiments [127, 154] or repetitive voltage ramps [124, 126]. But, even if an increase in SILC is found over a wide range of gate-oxide thicknesses, the nature of the total excess current may be of di€erent nature in the thinnest ones (DC component) and the thickest ones (AC component) [124, 136]. The possibility that SILC would only be the transient current due to the charging and discharging of traps previously generated by the high-®eld stress in the oxide [134] has been further ruled out [136], a DC component being de®nitely identi®ed. It appears that whatever the stressing polarity is, SILC increases for both measurement polarities [127, 131, 154] with essentially similar kinetics. In contrast, some authors point out that SILC is higher when the J±V measurement voltage is opposite to the polarity of the stress voltage than when the two polarities are the same [127, 136]. As one might expect, SILC increases as oxide thickness is reduced (see Fig. 11), even if a turn-around e€ect is observed in N2O oxides scaled below 5.3 nm [149]. The evolution of SILC versus the injected charge is well described by a power law with a slope of approximately 0.5 (see Fig. 12) [141, 154]. The in¯uence of the stressing voltage polarity seems to be more complicated: SILC increase is clearly ®elddependent (see Fig. 12), and most studies ®nd relations in SILC generation [124, 136], between SILC and injected electron energy [131] or between SILC and trap oxide density [141], essentially independent of the stressing polarity. Other studies indicate that negative gate polarities are more favorable to SILC increase than positive gate voltages in 5 nm thick oxides for similar oxide ®eld and injected charge (see Fig. 12) [154]. No saturation behavior is found in SILC increase below ¯uences up to 10 C/cm2 [127, 131, 141, 154], but it seems to saturate beyond ¯uences of 100 C/cm2 [124]. No clear threshold ®eld is required for SILC generation. It may be correlated to the fact that electrons generate defects even when their average energy is below the 2 eV threshold usually observed for trap creation in the oxide [131]. SILC is found to decrease by annealing

Fig. 11. Oxide thickness dependence of SILC induced by FN stresses with the same oxide stressing ®eld.

18

D. Vuillaume et al.

Fig. 12. Increase kinetics in SILC versus the injected charge Qinj during high ®eld stresses on capacitors, showing the power law dependence ISILC %Qninj with n1 0.5, the ®eld dependence of SILC for a given Qinj, and the most ecient SILC generation when the FN stress is performed with negative gate voltages than when the FN stress is performed with positive gate voltages (here the ¯at-band voltage is ÿ1 V).

at temperatures higher than 2508C [123, 139], but the initial low ®eld current is never recovered even for long baking times. Only few works focused on the temperature dependence of SILC. SILC increases with temperature more rapidly than the tunneling current before stress when measurements are achieved in the range for 77 K±2008C to 2508C [124]. In the initial paper of Maserjian and Zamani [122], it was shown that wet/annealed oxides were more sensitive to defect and SILC generation than dry oxides, suggesting the in¯uence of water related traps. More recently, it was observed that SILC in a nitrided oxide was slightly higher than in a conventional one [141], and that this e€ect had to be attributed to an enhanced trap assisted conduction process. Another study points out that the suppression of hole injection from the substrate into the oxide in N2O nitrided oxides may enhance the oxide reliability and lower SILC [145]. This trend seems to be con®rmed in N2O annealed oxides after FN stress [149] and by the fact that nitridation causes a signi®cant decrease of the oxide trap generation [144]. Recently, few works have reported on the generation of SILC after HCI: Substrate Hot Hole Injections (SHH) [137, 139, 145, 147] or Channel Hot-Carrier Injections (CHI) [154]. It was found that localized channel hole injections in 5 nm devices led to the same order of magnitude of SILC as homogeneous injections from the gate for the same stress time (VG= ÿ 6V), while localized channel electron injections did not induce SILC [154]. From some similarities between the excess currents induced by FN and SHH, it was suggested that the excess currents induced by FN were caused by the injected holes produced by high-energy electrons generated in the oxide and injected at the anode [137, 139]. The centroid of defects induced by SHH is determined to be located around 3 nm from the

Si/SiO2 interface and it seems that in 6 nm thick oxides SILC is composed of a transient component due to the ®lling of the trap centers and a DC leakage through the oxide [139]. Another work has established that the voltage dependence of SHH-related SILC was steeper than for the FN-related SILC, with a generation rate versus the injected charge about 1000 times larger for SHH than for FN related SILC [147]. As SHH-related SILC is reduced both by a post-stress hot electron injection or by UV irradiation, and as none of these e€ects has ever been observed in FN-related SILC, it is proposed that the conduction mechanism and its microscopic origin may be di€erent though both would be caused by hot hole injection [139, 147]. Several conduction mechanisms have been proposed since the ®rst attempt to explain SILC. It was ®rst proposed that the build-up of positively charged states in the region of the oxide near the anode induced a barrier lowering for the tunneling current [122]. On the basis of many further experimental results [124, 126, 154], the possibility of a localized positive charge as being fully responsible for SILC could be ruled out. It was then proposed that SILC was resulting from the local lowering of the tunneling barrier due to the generation of local defects inducing a thermally assisted tunneling through a barrier of about 1 eV [124], or resulted from FN tunneling through an oxide barrier of reduced height (0.9±1.1 eV) [146]. In any case, it is found that SILC is proportional to the density of bulk oxide traps [146]. On the other hand, the voltage dependence of SILC was found to match a Schottky emission law [127] or to match a Frenkel± Poole process [123]. It was shown that the induced traps were not only generated near the anode but throughout the oxide [127, 130]. A direct correlation can be established between the SILC increase and the build-up of the interface state density [126, 154], a direct linear relation is obtained between SILC and neutral trap oxide density [127] and even a oneto-one correlation between DC SILC and bulk oxide electron trap density is found [141]. As these di€erent defects have the same microscopic origin (the interface state density being just the part of the oxide trap density located very close to the Si/SiO2 interface), it has been proposed that SILC would result from a homogeneous neutral oxide trap assisted tunneling mechanism. The energy location of these neutral traps has been estimated to ®t experimental results at Et=2.3±2.4 eV below the oxide conduction band and their capture cross-section given by s = 101501016 cm2 [137]. Concerning the microscopic nature of these traps, EDMR studies on SILC show that it does not correspond to either of the two previously identi®ed families in the Si/SiO2 system, i.e. the Pb center or E' center (Si dangling bonds in the oxide), but that the g-tensor values would be in the right range for oxygen dangling bonds [135]. This single trap assisted tunneling

Hot-carrier injections in SiO2

mechanism has been identi®ed to be inelastic rather than elastic to reproduce the oxide thickness and voltage dependence of SILC [150], accompanied by a large energy loss of around 1.5 eV [143]. Only recently, the possible in¯uence of the positive oxide charge due to the trapped holes injected from the anode in SHH experiments has reappeared [140], stating that the presence of both holes and neutral oxide traps is a necessary condition for the SILC or supposing that the most promising mechanism for SILC is sequential tunneling via trapped holes. As is shown through this review, many processes are still competing to explain SILC, which remains a major issue for data retention in Flash memories. Anyway, the role of hot holes in the generation process seems well established. The necessity to design memory cells in a way to minimize the hot hole injection whatever the writing/erasing process is will be one of the main issues in down-scaling oxide thickness below 8 nm.

DEGRADATION IN SUB-100 NM FET, PERSPECTIVES

Since the demonstration of the feasibility of 0.1 mm MOSFETs [22, 155±158], their hot-carrier reliability has become a subject of interest. In the case of deep-submicrometer MOSFET (R0.1 mm) operating at drain voltage VD lower than 3 V (typically 1.5 V), one would expect that the carriers in the channel cannot acquire an energy larger than the Si±SiO2 potential barrier, thus turning o€ the hot-carrier injections. In 0.15 mm n-MOSFETs, it was observed that a substrate current is generated when VD exceeds 0.7 V, and that a gate current is measurable for VD values as low as 1.8 V [22]. A large increase in the interface state density was also observed after stressing a 0.15 mm transistor with VD values comprised between 2.2 and 2.7 V (VG=1 V). It seems that the behaviors of the substrate and gate currents, as well as the degradation behaviors, look like those of longer channel devices [22, 157]. For example, the dependence of the degradation on the gate voltage is identical to that of micrometer MOSFETs, i.e. with a maximum correlating the gate voltage at the maximum of the substrate current [22]. Several possible mechanisms have been suggested to explain that the carriers can acquire an energy larger than qVD in the case of low drain voltages [22]. Heating due to thermionic emission over the barrier in the presence of a vertical electric ®eld can explain the injection of carriers in the gate [159]. Auger recombination where an electron±hole pair recombines, transferring its energy to another electron closer to the top of the potential barrier, can also lead to injections in the gate-oxide [160, 161]. In conclusion, it seems that the basic hot-carrier concepts can be further used in low voltage deep-submicrometer MOSFETs, even if

19

the physical mechanisms responsible for the hotcarrier generation are not clearly established, and need to be further investigated. For instance, degradation of 0.1 mm MOSFETs has been investigated at room temperature (injections performed at maximum substrate current), and it was observed that a signi®cant interface state generation takes place. This degradation tends to be uniform, i.e. the degraded zone tends to extend to the channel length instead of being strongly located near the drain as in larger devices [162]. On the other hand, deep submicrometer MOSFETs (gate area smaller than 1 mm2) open the door to study Si±SiO2 interface defects at their ultimate level: capture and emission of a single carrier by a single trap [163]. In such devices, an interface state density of 1010 cmÿ2 eVÿ1 leads to less than 100 traps present under the gate and only a few of them are active if they are located near the Fermi level at a given bias condition. Any ¯uctuation in the occupancy of an individual defect generates a discrete switching in the drain current. This peculiar instability is known as random telegraph signal (RTS) and its amplitude (easily observable) is typically of the order of 0.1% of the channel current. RTS measurements have been used to analyze single traps induced by hot-carrier injections [164]. Charge pumping has also been used to study single trap after HCI [Saks + IMEC]. Futhermore, reducing the size of both active gate area and gate dielectric of the devices also leads to opportunities for new devices as pioneered by works on single electron devices (SED) [163±168]. These devices are based on the e€ect known as Coulomb blockade. In devices with gate area less than 0.1  0.1 mm2 and gate dielectric thickness lower than 5 nm, the gate capacitance is so large that the Coulomb energy associated with the transfer of an elementary carrier charge through the capacitance is of the order of a few tens of millivolts. In the ®rst studies at low temperatures (down to a few Kelvin), this energy is sucient to prevent the transfer of further charges leading to the concept of SED. Recently, single electron transistor memory working at room temperature has been demonstrated by several groups [169, 170]. In the same direction toward smaller devices and to overcome the inherent limitation of ultra-thin SiO2, which is highly leaky at thicknesses below about 3 nm, monolayers of organic material have been proposed and demonstrated as a possible alternative for gate insulators [171±173]. However, the reliability issues of these devices (SED and organic monolayer based devices) have not been so far studied, and thus should be possible subjects of future investigations. REFERENCES 1. Hu, C., Tam, S. T., Hsu, F., Ko, P., Chan, T. and Terril, K. W. IEEE Trans. Electron Dev., 1985, ED32, 375.

20

D. Vuillaume et al.

2. Heremans, P., Bellens, R., Groeseneken, G. and Maes, H. E. IEEE Trans. Electron Dev., 1988, 35, 2194. 3. Schwerin, A., HaÈnsch, W. and Werner, W. IEEE Trans. Electron Dev., 1987, ED-34, 2493. 4. Doyle, B. S., Bourcerie, M., Bergonzoni, C., Benechi, R., Bravaix, A., Mistry, K. R. and Boudou, A. IEEE Trans. Electron Dev., 1990, 37, 1869. 5. Takeda, E. and Suzuki, N. IEEE Electron Dev. Lett., 1983, EDL-4, 111. 6. Doyle, B. S., Mistry, K. R. and Faricelli, J. IEEE Electron Dev. Lett., 1997, 18, 51. 7. Vuillaume, D., Marchetaux, J. C., Lippens, P. E., Bravaix, A. and Boudou, A. IEEE Trans. Electron Dev., 1993, 40, 773. 8. Bourcerie, M., Marchetaux, J. C., Boudou, A. and Vuillaume, D. Appl. Phys. Lett., 1989, 55, 2193. 9. Hofmann, K. R., Werner, C., Weber, W. and Dorda, G. IEEE Trans. Electron Dev., 1985, ED-32, 691. 10. Lai, S. K., Appl. Phys. Lett., 1981, 39, 58; J. Appl. Phys., 1983, 54, 2540. 11. Tsuchiya, T., Kobayashi, T. and Nakajima, S. IEEE Trans. Electron Dev., 1987, ED-34, 386. 12. Vuillaume, D., Marchetaux, J. C. and Boudou, A. IEEE Electron Dev. Lett., 1991, EDL-12, 60. 13. Doyle, B., Bourcerie, M., Marchetaux, J.-C. and Boudou, A. IEEE Trans. Electron Dev., 1990, ED-37, 744. 14. Annunzianta, R., Dalla Libera, G., Ghio, E. and Maggia, A. In Proc. ESSDERC'87, eds A. Heuberger, H. Ryssel and P. Lange. Springer-Verlag, Berlin, 1987, p. 715. 15. Reimbold, G., Paviet-Salomon, F., Haddara, H., Guegan G. and Cristoloveanu, S. In Proc. ESSDERC'88, eds J. P. Nougier and D. Gasquet. Les eÂditions de Physique, Paris, 1988, p. 665. 16. Acovic, A., Dutoit, M. and Ilegems, M. IEEE Trans. Electron Dev., 1990, ED-37, 1467. 17. Gaensslen, F. H. and Aitken, J. M. IEEE Electron Dev. Lett., 1980, EDL-1, 231. 18. Saks, N. S., Heremens, P. L., Van den Hove, L., Maes, H. E., DeKeersmaecker, R. F. and Declerck, G. J. IEEE Trans. Electron Dev., 1986, ED-33, 1529. 19. Vuillaume, D. and Doyle, B. S. Solid-State Electron., 1992, 35, 1099. 20. Doyle, B. S., Faricelli, J., Mistry, K. R. and Vuillaume, D. IEEE Electron Dev. Lett., 1993, 14, 63. 21. Marchetaux, J. C., Bourcerie, M., Boudou, A. and Vuillaume, D. Electron Dev. Lett., 1990, 11, 406. 22. Chung, J. E., Jeng, M., Moon, J. E., Ko, P. and Hu, C. IEEE Trans. Electron Dev., 1990, 37, 1651. 23. Chan, V.-H. and Chung, J.-E. IEEE Trans. Electron Dev., 1995, 42, 957. 24. Raychaudhuri, A., Deen, M.-J., Kwan, W. S. and King, M. I. H. IEEE Trans. Electron Dev., 1996, 43, 1114. 25. Hori, T., Hirase, J., Odake, Y. and Yasui, T. IEEE Trans. Electron Dev., 1992, 39, 2312. 26. Huang, T.-Y., Yao, W. W., Martin, R. A., Lewis, A. G., Koyanagi, M. and Chen, J. Y. IEDM Tech. Dig., 1986, 742. 27. Hieda, K., Sunouchi, K., Takato, H., Nitayama, A., Horiguchi, F. and Masuoka, F. IEEE Trans. Electron Dev., 1992, 39, 671. 28. Izawa, R., Kure, T. and Takeda, E. IEEE Electron Dev. Lett., 1988, 35, 2088. 29. Bravaix, A. and Vuillaume, D. Solid-State Electron., in press. 30. Bellens, R., Bosch, G. V. D., Habas, P., MieÂville, J.P., Badenes, G., Clerix, A., Groeseneken, G., Deferm, L. and Maes, H. E. IEEE Trans. Electron Dev., 1996, 43, 1407.

31. Ng, K. K. and Taylor, G. W. IEEE Trans. Electron Dev., 1983, ED-30, 871. 32. Tsou, J. J., Yao, C. C., Cheung, R. and Chan, H. W. IEEE Electron Dev. Lett., 1986, EDL-7, 5. 33. Weber, W. and Lau, F. IEEE Electron Dev. Lett., 1987, EDL-8, 208. 34. Hiruta, Y., Maeguchi, K. and Kanzaki, K. IEDM Tech. Dig., 1986, 718. 35. Mizuno, T., Kumagai, J., Matsumoto, Y., Sawada, S. and Shinozaki, S. IEDM Tech. Dig., 1986, 726. 36. Tang, Y., Kim, D. M., Lee, Y. and Sabi, B. IEEE Electron Dev. Lett., 1990, EDL-11, 203. 37. Doyle, B. S. and Mistry, K. R. IEEE Trans. Electron Dev., 1990, ED-37, 1301. 38. Reimbold, G., Saint-Bonnet, P. and Gautier, J. IEEE/IRPS, 1990, 270. 39. Doyle, B. S. and Mistry, K. R. IEEE Electron Dev. Lett., 1990, EDL-11, 547. 40. Matsuoka, F., Iwai, H., Hayashida, H., Hama, K., Toyoshima, Y. and Maeguchi, K. IEEE Trans. Electron Dev., 1990, ED-37, 1487. 41. Ong, T., Ko, P. and Hu, C. IEEE Trans. Electron Dev., 1990, ED-37, 1658. 42. Tsuchiya, T., Okazaki, Y., Miyake, M. and Kobayashi, T. IEEE Trans. Electron Dev., 1992, ED39, 404. 43. Wang, Q., Brox, M., Krautschneider, W. H. and Weber, W. IEEE Electron Dev. Lett., 1991, 12, 218. 44. Bravaix, A. and Vuillaume, D. Microelectron. Eng., 1992, 19, 469. 45. Bellens, R., Groeseneken, G., Heremans, P. and Maes, H. E. Microelectron. Eng., 1992, 19, 465. 46. Ong, T., Ko, P. and Hu, C. Electron Dev. Lett., 1987, EDL-8, 413. 47. Bravaix, A. Ph.D. Thesis, University of Paris VII, 1990. 48. Koyanagi, M., Lewis, A. G., Zhu, J., Martin, R. A., Huang, T. Y. and Chen, J. Y. In Proc. IEDM'86, p. 722. 49. Weber, W., Brox, M., KuÈnemund, T., MuÈhlho€, H. M. and Landsiedel, D. S. IEEE Trans. Electron Dev., 1991, 38, 1859. 50. Brox, M., Schwerin, A., Wang, Q. and Weber, W. Trans. Electron Dev., 1994, 41, 1184. 51. Woltjer, R. and Paulzen, G. M. Trans. Electron Dev., 1994, 41, 1639. 52. Woltjer, R., Paulzen, G. M., Pomp, H. G., Lifka, H. and Woerlee, P. H. Trans. Electron Dev., 1995, 42, 109. 53. Hu, C. Semiconduct. Sci. Technol., 1992, 7, 555. 54. Parillo, L. C., Hillenius, S. J., Field, R. L., Hu, E. L., Fichtner, W. and Chen, M. IEDM Tech. Dig., 1984, 418. 55. Weber, W., Werner, C. and Dorda, G. IEEE Electron Dev. Lett., 1984, EDL-5, 518. 56. Chen, K., Saller, S. and Shah, R. IEEE Trans. Electron Dev., 1986, ED-33, 424. 57. Choi, J. Y., Ko, P. K. and Hu, C. IEEE Electron Dev. Lett., 1987, EDL-8, 333. 58. Weber, W. IEEE Trans. Electron Dev., 1988, 35, 1476. 59. Bellens, R., Heremans, P., Groeseneken, G. and Maes, H. E. IEDM Tech. Dig., 1988, 212. 60. Mistry, K. R. and Doyle, B. IEEE Electron Dev. Lett., 1990, 11, 267. 61. Subrahmaniam, R., Chen, J. Y. and Johnston, A. H. IEEE Electron Dev. Lett., 1990, 11, 21. 62. Revil, N., Cristoloveanu, S. and Mortini, P. Microelectron. Eng., 1992, 19, 461. 63. Bellens, R., Heremans, P., Groseneken, G., Maes, H. E. and Weber, W. IEEE Trans. Electron Dev., 1990, 37, 310.

Hot-carrier injections in SiO2 64. Choi, J. Y., Ko, P. K. and Hu, C. In Proc. VLSI Symp., 1987, p. 45. 65. Doyle, B. S. and Dunn, G. J. IEEE Electron Dev. Lett., 1991, 12, 63. 66. Brox, M. and Weber, W. IEEE Trans. Electron Dev., 1991, 38, 1852. 67. Mistry, K. and Doyle, B. IEEE Electron Dev. Lett., 1991, EDL-12, 492. 68. HaÈnsch, W. and Weber, W. Electron Device Lett., 1989, EDL-10, 252. 69. Mistry, K. and Doyle, B. IEEE Trans. Electron Dev., 1994, ED-40, 96. 70. Bellens, R., Groeseneken, G., Heremans, P. and Maes, H. E. IEEE Trans. Electron Dev., 1994, ED41, 1421. 71. Quader, K. N., Fang, P. F., Yue, J. T., Ko, P. K. and Hu, C. IEEE Trans. Electron Dev., 1994, ED-41, 681. 72. Bergonzoni, C., Benecchi, R., Libera, G. D. and Nannini, A. Trans. Electron Dev., 1992, 39, 1144. 73. Ong, T., Ko, P. K. and Hu, C. IEEE Trans. Electron Dev., 1990, ED-37, 1658. 74. Bravaix, A., Vuillaume, D., Goguenheim, D., Laserre, V. and Haond, M. IEDM Tech. Dig., 1996, 873. 75. Bravaix, A., Goguenheim, D., Vuillaume, D., Revil, N., Varrot, M. and Mortini, P. Microelectron. Eng., 1997, 36, 305. 76. Goguenheim, D., Bravaix, A., Vuillaume, D., Varrot, M., Revil, N. and Mortini, P. In ESSDERC'96 Proc., 1996, p. 987. 77. Hughes, R. C. Phys. Rev. B, 1977, 15, 2012. 78. Poindexter, E. H. and Caplan, P. J., Progr. Surf. Sci., 1983, 14, 201; Poindexter, E. H., Caplan, P. J. and Gerardi, G. J. In Physics and Chemistry of SiO2 and its Interface, eds C. R. Helms and B. E. Deal. Plenum Press, New York, 1988, p. 299; Johnson, N. M. In Physics and Chemistry of SiO2 and its Interface, eds C. R. Helms and B. E. Deal. Plenum Press, New York, 1988, p. 319. 79. Gerardi, G. J., Poindexter, E. H., Caplan, P. J. and Johnson, N. M. Appl. Phys. Lett., 1986, 49, 348. 80. Stathis, J. H. and Dori, L. Appl. Phys. Lett., 1991, 58, 1641. 81. Vuillaume, D., Goguenheim, D. and Bourgoin, J. C. Appl. Phys. Lett., 1991, 58, 490. 82. Vuillaume, D. Microelectron. Eng., 1993, 22, 201. 83. Vranch, R. L., Henderson, B. and Pepper, M. Appl. Phys. Lett., 1988, 52, 1161. 84. Krick, J. T., Lenahan, P. M. and Dunn, G. J. Appl. Phys. Lett., 1991, 59, 3437. 85. Stathis, J. and DiMaria, D. J. Appl. Phys. Lett., 1992, 61, 2887. 86. Vuillaume, D., Deresmes, D. and StieÂvenard, D. Appl. Phys. Lett., 1994, 64, 1690. 87. Lepine, D. J. Phys. Rev. B, 1972, 6, 436. 88. Solomon, I. Solid State Commun., 1976, 20, 215. 89. Rong, F. C., Poindexter, E. H., Harmatz, M., Buchwald, W. R. and Gerardi, G. J. Solid State Commun., 1990, 76, 1083. 90. Kaplan, D. and Pepper, M. Solid State Commun., 1980, 34, 803. 91. Henderson, B. Appl. Phys. Lett., 1984, 44, 228. 92. Jupina, M. A. and Lenahan, P. M. IEEE Trans. Nucl. Sci., 1989, 36, 1800. 93. Stathis, J. H. Microelectron. Eng., 1993, 22, 191. 94. Henderson, B., Pepper, M. and Vranch, R. L. Semicond. Sci. Technol., 1989, 4, 1045. 95. Gabrys, J. W., Lenahan, P. M. and Weber, W. Microelectron. Eng., 1993, 22, 273. 96. Lannoo, M., Vuillaume, D., Deresmes, D. and Stievenard, D. Microelectron. Eng., 1993, 22, 143.

21

97. DiMaria, D. J., Arnold, D. and Cartier, E., Appl. Phys. Lett., 1992, 60, 2118; 61, 2329; J. Appl. Phys., 1993, 73, 3367. 98. Mir, A. and Vuillaume, D., Appl. Phys. Lett., 1993, 62(10), 1125; Microelectron. J., 1993, 24, 361. 99. Chang, S. T. and Lyon, S. A. Appl. Phys. Lett., 1986, 48, 136. 100. Fleetwood, D. M., Winokur, P. S., Reber, R. A., Meisenheimer, T. L., Schwank, J. R., Shaneyfelt, M. R. and Riewe, L. C. J. Appl. Phys., 1993, 73, 5058. 101. Vuillaume, D., Bourgoin, J. C. and Lannoo, M. Phys. Rev. B, 1986, 34, 1171. 102. Lakhdari, H., Vuillaume, D. and Bourgoin, J. C. Phys. Rev. B, 1988, 38, 13124. 103. Paulsen, R. E., Siergiej, R. R., French, M. L. and White, M. H. IEEE Electron Dev. Lett., 1992, 13, 627. 104. Vuillaume, D., Mir, A., Bouchakour, R., Jourdain, M., El-Hdiy, A. and Salace, G. J. Appl. Phys., 1993, 73, 277. 105. Young, D. R., Irene, A. E., DiMaria, D. J., DeKeersmaecker, R. F. and Massoud, H. Z. J. Appl. Phys., 1979, 50, 6366. 106. Gale, R., Feigl, F. J., Magee, C. W. and Young, D. R. J. Appl. Phys., 1983, 54, 6938. 107. DiMaria, D. J. and Stasiak, J. W. J. Appl. Phys., 1989, 65, 2342. 108. Vuillaume, D. Appl. Phys. Lett., 1991, 59, 3118. 109. Cartier, E., Buchanan, D. A. and Dunn, G. J. Appl. Phys. Lett., 1994, 64, 901. 110. Griscom, D. L., Appl. J. Phys., 1985, 58, 2524; Reed, M. L. and Plummer, J. D., J. Appl. Phys., 1988, 63, 5776. 111. Gerardi, G. J., Poindexter, E. H., Caplan, P. J., Harmatz, M. and Buchwald, W. R. J. Electrochem. Soc., 1989, 136, 2609. 112. Solomon, P. J. Vac. Sci. Technol., 1977, 14, 1122. 113. Fischetti, M. V., DiMaria, D. J., Brorson, S. D., Theis, T. N. and Kirtley, J. R. Phys. Rev. B, 1985, 31, 8124. 114. Arnold, D., Cartier, E. and DiMaria, D. J. Phys. Rev. B, 1992, 45, 1477. 115. Wang, S. J., Sung, J. M. and Lyon, S. A. Appl. Phys. Lett., 1988, 52, 1431. 116. Gerardi, G. J., Poindexter, E. H., Harmatz, M., Warren, W. L., Nicollian, E. H. and Edwards, A. H. J. Electrochem. Soc., 1991, 138, 3765. 117. Sah, C. T. Solid-State Electron., 1990, 33, 147. 118. Vuillaume, D., Goguenheim, D. and Vincent, G. Appl. Phys. Lett., 1990, 57, 1206. 119. Vuillaume, D. and Bravaix, A. J. Appl. Phys., 1993, 73, 2559. 120. Farmer, K. R., Andersson, M. O. and EngstroÈm, O. Appl. Phys. Lett., 1991, 58, 2666. 121. El-Hdiy, A., Salace, G., Petit, C., Jourdain, M. and Vuillaume, D. J. Appl. Phys., 1993, 74, 1124. 122. Maserjian, J. and Zamani, N. J. Appl. Phys., 1982, 53, 559. 123. Naruke, K., Taguchi, S. and Wada, M. In Proc. IEDM'88, p. 424. 124. Olivo, P., Nguyen, T. N. and Ricco, B. IEEE Trans. Electron Dev., 1988, 35, 2259. 125. Kassmi, K., Prom, J. L. and Sarrabayrouse, G. Solid-State Electron., 1991, 34, 509. 126. Rofan, R. and Hu, C. IEEE Electron Dev. Lett., 1991, 12, 632. 127. Dumin, D. J. and Maddux, J. R. IEEE Trans. Electron Dev., 1993, 40, 986. 128. Aritome, S., Shirota, R., Hemink, G., Endoh, T. and Masuoka, F. Proc. IEEE, 1993, 81, 776. 129. Dumin, D. J., Cooper, J. R., Maddux, J. R., Scott, R. S. and Wong, D. P. J. Appl. Phys., 1994, 76, 319.

22

D. Vuillaume et al.

130. Dumin, D. J. and Vanchinathan, S. IEEE Trans. Electron Dev., 1994, 41, 936. 131. Buchanan, D. A., Dimaria, D. J., Chang, C. A. and Taur, Y. Appl. Phys. Lett., 1994, 65, 1820. 132. Dimaria, D. J. Microelectron. Eng., 1995, 28, 63. 133. Dumin, D. J., Mopuri, S., Vanchinathan, S., Scott, R. S., Subramoniam, R. and Lewis, T. G. In Proc. IRPS'94, p. 143. 134. Scott, R. S. and Dumin, D. J. IEEE Trans. Electron Dev., 1996, 43, 130. 135. Stathis, J. H. Appl. Phys. Lett., 1996, 68, 1669. 136. Runnion, E. F., Gladstone, S. M., Scott, R. S., Dumin, D. J., Lie, L. and Mitros, J. In Proc. IRPS'96, p. 93. 137. Sakakibara, K., Ajika, N., Hatanaka, M. and Miyoshi, H. In Proc. IRPS'96, p. 100. 138. Yamada, S., Amemiya, K., Yamane, T., Hazama, H. and Hashimoto, K. In Proc. IRPS'96, p. 108. 139. Teramoto, A., Kobayashi, K., Matsui, Y., Hiramaya, M. and Yasuoka, A. In Proc. IRPS'96, p. 113. 140. Hemink, G. J., Shimizu, K., Aritome, S. and Shirota, R. In Proc. IRPS'96, p. 117. 141. de Blauwe, J., Degraeve, R., Bellens, R., Van Houdt, J., Roussel, Ph., Groeseneken, G. and Maes, H. E. In Proc. ESSDERC'96. Editions FrontieÁres, 1996, p. 361. 142. Hu, C. In Proc. IEDM'96, p. 319. 143. Tagaki, S., Yasuda, N. and Toriumi, A. In Proc. IEDM'96, p. 323. 144. Lin, C., Chou, A. I., Kumar, K., Chowdhury, P. and Lee, J. C. In Proc. IEDM'96, p. 331. 145. Kobayashi, K., Teramoto, A., Nakamura, T., Watanabe, H., Kurokawa, H., Matsui, Y. and Hiramaya, M. In Proc. IEDM'96, p. 335. 146. de Blauwe, J., Van Houdt, J., Wellekens, D., Degraeve, R., Roussel, Ph., Haspeslagh, L., Deferm, L., Groeseneken, G. and Maes, H. E. In Proc. IEDM'96, p. 343. 147. Matsukawa, N., Yamada, S., Amemiya, K. and Hazama, H. IEEE Trans. Electron Dev., 1996, 43(11), 1924. 148. Yamada, S., Yamane, T., Amemiya, K. and Naruke, K. IEEE Trans. Electron Dev., 1996, 43, 1937. 149. Kafai, L., Chen, W. M., Hao, M. Y., Lee, J., Gardner, M. and Fulford, J. Appl. Phys. Lett., 1995, 67, 673. 150. Rosenbaum, E. and Register, L. F. IEEE Trans. Electron Dev., 1996, 44, 317. 151. Degraeve, R., de Blauwe, J., Roussel, Ph., Groeseneken, G. and Maes, H. E. In Proc. IEDM'96, p. 327.

152. Dimaria, D. J. Appl. Phys. Lett., 1996, 68, 3004. 153. Dimaria, D. J., Cartier, E. and Arnold, D. J. Appl. Phys., 1993, 73, 3367. 154. Goguenheim, D., Bravaix, A., Vuillaume, D., Mondon, F., Candelier, Ph., Jourdain, M. and Meinertzhagen, A. Microelectron. Eng., 1997, 36, 141. 155. Shahidi, G. G., Antoniadis, D. A. and Smith, H. I. IEEE Electron Dev. Lett., 1988, EDL-9, 94. 156. Sai-Halasz, G. A., Wordeman, M. R., Kern, D. P., Rishton, S. and Ganin, E. IEEE Electron Dev. Lett., 1988, EDL-9, 464. 157. Shahidi, G. G., Antoniadis, D. A. and Smith, H. I. IEEE Electron Dev. Lett., 1988, EDL-9, 497. 158. Mieville, J. P., Barrier, J., Shi, Z., Dutoit, M., Oppliger, Y., Moret, J. M. and Perret, A. Microelectron. Eng., 1991, 13, 189. 159. Brennan, K. and Hess, K. IEEE Electron Dev. Lett., 1986, EDL-7, 86. 160. Sangiorgi, E., Ricco, B. and Olivo, P. IEEE Electron Dev. Lett., 1985, EDL-6, 513. 161. Shirota, R. and Yamaguchi, T. IEDM Tech. Dig., 1991, 123. 162. Revil, N., MieÂville, J.-P., Cristoloveanu, S., Dutoit, M. and Mortini, P. Microelectron. Eng., 1993, 22, 293. 163. Kirton, M. J. and Uren, M. J. Adv. Phys., 1989, 38, 367. 164. Shi, Z. M., MieÂville, J.-P. and Dutoit, M. IEEE Trans. Electron. Dev., 1994, 41, 1161. 165. Likharev, K. K. IBM J. Res. Dev., 1987, 32, 144. 166. Fulton, T. A. and Dolan, G. J. Phys. Rev. Lett., 1987, 59, 109. 167. Van Bentum, P. J. M., Van Kempen, H., Van de Leemput, L. E. C. and Teunissen, P. A. A. Phys. Rev. Lett., 1988, 60, 369. 168. Pothier, H., Lafarge, P., Urbina, C., Esteve, D. and Devoret, M., Europhys. Lett., 1992, 17, 249; Devoret, M., Esteve, D. and Urbina, C., Nature, 1992, 360, 547. 169. Guo, L., Leobandung, E. and Chou, S. Y. Science, 1997, 275, 649. 170. Nakajima, A., Futatsugi, T., Kosemura, K., Fukano, T. and Yokoyama, N. Appl. Phys. Lett., 1997, 70, 1742. 171. Boulas, C., Davidovits, J. V., Rondelez, F. and Vuillaume, D. Phys. Rev. Lett., 1996, 76, 4797. 172. Vuillaume, D., Boulas, C., Collet, J., Davidovits, J. V. and Rondelez, F. App. Phys. Lett., 1996, 69, 1646. 173. Vuillaume, D. Mat. Res. Soc. Proc., 1997, 996, 79.