- Email: [email protected]
Hungarian cellprocessor project
Update Hungarian cellprocessor project After 10 years of research, cellprocessors - - microprocessor building blocks for parallel systems - - are n o w available commercially
A universal building block for massively parallel processors, or "cellprocessors" the Hungarian designed Densicell SPP chip is now commercially available together with a demonstration board and development system to support applications. Each chip has 64 identical computing cells in an 8 x 8 matrix, and is manufactured using 1.5 pm HCMOS technology. All I / 0 is TTL compatible. The processor bridges the gap between cellular automata applications and systolic systems, and constitutes the basis of a non-von Neumann computer. Used with a microcontroller, suitable applications are image processing and image recognition, vector and matrix multiplication, and associative processing and fixed-point arithmetic. microprocessors parallelprocessing cellprocessors
Cellular processor research began more than ten years ago at Jozsef Attila University Szeged and the Hungarian Academy of Sciences. The goal of the research was to construct hardware homogeneous, highly parallel, very high speed cellular processors. Based on the microcell concept (80-250 transistors), cells, cellular fields and full cellprocessor architectures have been designed, simulated, and a 256-cell TTL model has been built. Cellular algorithms have been designed and simulated, and a new sophisticated cellular programming methodology has been developed with the benefit of accumulated experience. The work grew between 1983 and 1986 into DM 1M development project, covering all aspects of custom LSI and VLSI chip design, architecture and hardware design, cellular programming and microprogramming, host software and application case studies. Results include: a full custom validated sorting chip has been prototyped; in the main thrust of the project a universal-purpose microprogrammable LSI chip has been designed and fabricated, another universal VLSI chip has been
designed; cellular assembly and microassembly languages have been developed; a set of cellular microprograms have been written and tested, and development systems have been implemented; several cellprocessor architectures based on custom and standard devices have been worked out, and prototypes of an LSI ASIC and a memon/-based cellprocessor realized; a programmable gate array-based accelerator processor has been built. As the main research centre for this project Jozsef Attila University contracted several industrial and governmental companies and was funded by state grants. Based on the results of the project, Jozsef Attila University, Sz malk Computing Applications and Service Company, the Industrial Development Bank (Hungary) and Tradecoop IndustrialCooperative Trading House founded Cellware Microelectronics Ltd in October 1987. The result of this project, the Densicell SPP (SP1) chip, is available from Densitron Computers, UK who collaborated with Cellware.
Jozsef Attila University, H-6720 Szeged, Hungary Densitron Computers Ltd, Unit 4, Airport Trading Estate, Biggin Hill, Kent TN 16 3BW, U K
'Cellprocessor' refers to the fundamental structure of meshconnected identical microcells
CELLPROCESSOR
DEVICE
operating concurrently on a piece of data (Figure 1). Chips can also be connected regularly forming a cellular field. Input data enters into the field at its edges, ripples through it and the resultant data can be obtained at the opposite edges. From the scientific/engineering point of view cellprocessors are hardware homogeneous, spatiotemporal inhomogeneously microprogrammable, highly parallel systems, i.e. they form a universal programmable systolic array with microinstruction broadcasting. From the point of view of production, marketing and users they can be used as special array processors. Advantages of the cellprocessor approach include on-chip regularity that implies low cost and quick design. Thousand(s) of identical chips in the system make mass production, testing, diagnostics and self repair easier. Bit-level parallelism allows flexible, economic and highspeed parallel bit-pipelined programs. The microcell concept improves the computing power/silicon area ratio and m a k e s feasible megacell machines and waferscale-integrated processors. The main application areas of cellprocessors are: picture processing, enhanced graphics, finite element analysis and CAD/CAE, digital signal processing including filtering and codec, large system simulation, process control, matrix processing, and neurocomputing. The main features of the device are: • 64 identical computing cells in an 8 X 8 matrix • 9000 gates equivalent • 1.5 pm HCMOS technology • Gate speed equivalent to ECL 1Ok; faster than 74 STTL • TTL-compatible I/O • 44-pin standard plastic J-bend chip carrier package
0141-9331/90/02119-03 © 1990 Butterworth & Co. (Publishers) Ltd Vol 14 No 2 March 1990
119
Update
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plug-in boards is to give an introduction to these systems as well as to make it possible to evaluate them at affordable cost. DDB is supplied with a PC-based software system consisting of a bit-level simulator, a c extension, and a simple run-time system.
• Cellular assembler. Input: cellular assembly program; output: synchronized microassembly code. Cellular assembler is a high complexity program involving path generation, Boolean function optimization, etc. • Microassembler. Input: microassembly program; output: synchronized microassembly code. • Linkage editor. Input: one or more s y n c h r o n i z e d microassembly coded modules; output: executable object module. • Simulator. Simulates the work of cellprocessor hardware and host control program. Initially an executable object module should be loaded, and its running can be observed in an interactive and menu controlled way. • Run-time system. It ensures loading and execution of a cellular program (executable object code) on the cellprocessor. The run-time system can be used in a (: environment.
CELLULAR PROGRAMS A cellular program solves a given problem, e.g. matrix multiplication, using a cellprocessor. It consists of two components:
DEVELOPMENT SYSTEM Cellular programs can be described in two languages:
Cellprocessor chip block diagram and photograph Figure 1.
• 20 MHz maximal operating frequency • 100 mW dissipation at 5 MHz • True two-phase clocking, eliminating clock skew problems • Fully static construction
D E M O N S T R A T I O N BOARD Demonstration hardware (DDB) is available for Densicell systems. The aim of the IBM PC or compatible
120
• Cellular assembly language uses a cell-state transition level description of the cellular program. Cell transition functions can be defined in the FUNDEF language. (FUNDEFis a machine independent language for transition function description, originally developed for the CELLAS cellular automata simulation system.) • Microassembly language ensures direct description of SP1 microprograms. The development system can be used in an IBM PC/XT, AT environment. It has the following components (Figure 2):
J
x
/ x
~
/
ichronized microassembly code)
]=. . . . .
--m
_
i linkage ~ditor i J J
| \executable ebject code ) /
:; . m ' ~ n t o ,
1
;]q !
Figure 2. Cellprocessor ment path
I develop-
Microprocessors and Microsystems
Update A control program, which runs on the host computer and organizes the cooperation between the host and the cellprocessor. a CCU program that runs on the cellprocessor and controls the work of the cellular array. The run-time system of the cellprocessor ensures that a cellular program can be reached from c using the following c functions: SPl LOAD (programname) loads the given cellular program, SPl RUN (programname, parameters) executes the loaded cellular program with the given parameters. The cellprocessor is provided with a basic library of cellular programs (for example: sorting, convolution, etc.). These cellular programs can be reached with the above cfunctions. If the user wants to create further cellular programs, the development system can be used.
Cellular
assembly
language
The language is architectureindependent in the sense that different types of cellprocessors can be programmed using this language. A cellular assembly program has different sections: l ARCH determines
the parameters of the given cellprocessor (size of the array, type of cells, etc.). ARCH
Vol 74 No 2 March 7990
informs the compiler how to translate the instructions of the program. INIT initial describes the configuration of the cellular array. INIT is transformed by the compiler into a loader CCU program module and into a data file to be loaded. CP gives the CCU program on state-transition-step level. Cell transition functions should be defined by the CELLAWUNDEF language and stored in CELLAS libraries. These libraries can be reached in the cellular assembly program. INPADDR and OUTADDR formulate the I/O processes between the host computerand the cellular array. HOST contains the description of the control program component of the cellular program.
Microassembly
language
This language is suitable for programming cellprocessors which differ only in the size of cellular array, number of I/O buffers, etc. The structure of the language is similar to that of cellular assembly language: ARCH determines the cellprocessor architecture CP contains the microinstruction level description of the CCU program. INPADDR, OUTADDR and HOST give a lower level description than
similar sections of assembly language.
the
cellular
SIMULATOR The menu controlled system offers simulation of complete cellular programs (including the host control program) so that it simulates the hardware on the one hand and the run-time system on the other. Its main functions are: Loading a cellular program Host control program simulation Hardware simulation on microstep level Editor for data files, to generate test data for cellular programs. Watching cellular array, registers, variables, etc. Every bit of the SPl hardware can be traced. Saving the state of simulation, and restoring a saved state.
SELECTED
REFERENCES
Legendi, T and Toth, J ‘A full custom Lsl based architecture for a megacell machine’ Proc. Int. Conf, Parallel Computing (1985) pp 503-507 Legendi, T and Zsoter, A ‘A 16-state cellprocessor’ Proc. Int. Conf. Parallel Computing (1985) pp 509-514
Legendi, T, Katona, E, Toth, J and Zsoter, A ‘Megacell machine’ Parallel Comput 199
(1988)
pp 195-
121
A universal building block for massively parallel processors, or "cellprocessors" the Hungarian designed Densicell SPP chip is now commercially available together with a demonstration board and development system to support applications. Each chip has 64 identical computing cells in an 8 x 8 matrix, and is manufactured using 1.5 pm HCMOS technology. All I / 0 is TTL compatible. The processor bridges the gap between cellular automata applications and systolic systems, and constitutes the basis of a non-von Neumann computer. Used with a microcontroller, suitable applications are image processing and image recognition, vector and matrix multiplication, and associative processing and fixed-point arithmetic. microprocessors parallelprocessing cellprocessors
Cellular processor research began more than ten years ago at Jozsef Attila University Szeged and the Hungarian Academy of Sciences. The goal of the research was to construct hardware homogeneous, highly parallel, very high speed cellular processors. Based on the microcell concept (80-250 transistors), cells, cellular fields and full cellprocessor architectures have been designed, simulated, and a 256-cell TTL model has been built. Cellular algorithms have been designed and simulated, and a new sophisticated cellular programming methodology has been developed with the benefit of accumulated experience. The work grew between 1983 and 1986 into DM 1M development project, covering all aspects of custom LSI and VLSI chip design, architecture and hardware design, cellular programming and microprogramming, host software and application case studies. Results include: a full custom validated sorting chip has been prototyped; in the main thrust of the project a universal-purpose microprogrammable LSI chip has been designed and fabricated, another universal VLSI chip has been
designed; cellular assembly and microassembly languages have been developed; a set of cellular microprograms have been written and tested, and development systems have been implemented; several cellprocessor architectures based on custom and standard devices have been worked out, and prototypes of an LSI ASIC and a memon/-based cellprocessor realized; a programmable gate array-based accelerator processor has been built. As the main research centre for this project Jozsef Attila University contracted several industrial and governmental companies and was funded by state grants. Based on the results of the project, Jozsef Attila University, Sz malk Computing Applications and Service Company, the Industrial Development Bank (Hungary) and Tradecoop IndustrialCooperative Trading House founded Cellware Microelectronics Ltd in October 1987. The result of this project, the Densicell SPP (SP1) chip, is available from Densitron Computers, UK who collaborated with Cellware.
Jozsef Attila University, H-6720 Szeged, Hungary Densitron Computers Ltd, Unit 4, Airport Trading Estate, Biggin Hill, Kent TN 16 3BW, U K
'Cellprocessor' refers to the fundamental structure of meshconnected identical microcells
CELLPROCESSOR
DEVICE
operating concurrently on a piece of data (Figure 1). Chips can also be connected regularly forming a cellular field. Input data enters into the field at its edges, ripples through it and the resultant data can be obtained at the opposite edges. From the scientific/engineering point of view cellprocessors are hardware homogeneous, spatiotemporal inhomogeneously microprogrammable, highly parallel systems, i.e. they form a universal programmable systolic array with microinstruction broadcasting. From the point of view of production, marketing and users they can be used as special array processors. Advantages of the cellprocessor approach include on-chip regularity that implies low cost and quick design. Thousand(s) of identical chips in the system make mass production, testing, diagnostics and self repair easier. Bit-level parallelism allows flexible, economic and highspeed parallel bit-pipelined programs. The microcell concept improves the computing power/silicon area ratio and m a k e s feasible megacell machines and waferscale-integrated processors. The main application areas of cellprocessors are: picture processing, enhanced graphics, finite element analysis and CAD/CAE, digital signal processing including filtering and codec, large system simulation, process control, matrix processing, and neurocomputing. The main features of the device are: • 64 identical computing cells in an 8 X 8 matrix • 9000 gates equivalent • 1.5 pm HCMOS technology • Gate speed equivalent to ECL 1Ok; faster than 74 STTL • TTL-compatible I/O • 44-pin standard plastic J-bend chip carrier package
0141-9331/90/02119-03 © 1990 Butterworth & Co. (Publishers) Ltd Vol 14 No 2 March 1990
119
Update
WI
//t
¢/)
// / /
e~
•
I
/ /
/
/ r r
/ •
/
/
/
#
/
programmable, switching J • • i . f d'
#
,,
.
df
.,
•
/
•
#
•
#
O cO o
/
networkA
plug-in boards is to give an introduction to these systems as well as to make it possible to evaluate them at affordable cost. DDB is supplied with a PC-based software system consisting of a bit-level simulator, a c extension, and a simple run-time system.
• Cellular assembler. Input: cellular assembly program; output: synchronized microassembly code. Cellular assembler is a high complexity program involving path generation, Boolean function optimization, etc. • Microassembler. Input: microassembly program; output: synchronized microassembly code. • Linkage editor. Input: one or more s y n c h r o n i z e d microassembly coded modules; output: executable object module. • Simulator. Simulates the work of cellprocessor hardware and host control program. Initially an executable object module should be loaded, and its running can be observed in an interactive and menu controlled way. • Run-time system. It ensures loading and execution of a cellular program (executable object code) on the cellprocessor. The run-time system can be used in a (: environment.
CELLULAR PROGRAMS A cellular program solves a given problem, e.g. matrix multiplication, using a cellprocessor. It consists of two components:
DEVELOPMENT SYSTEM Cellular programs can be described in two languages:
Cellprocessor chip block diagram and photograph Figure 1.
• 20 MHz maximal operating frequency • 100 mW dissipation at 5 MHz • True two-phase clocking, eliminating clock skew problems • Fully static construction
D E M O N S T R A T I O N BOARD Demonstration hardware (DDB) is available for Densicell systems. The aim of the IBM PC or compatible
120
• Cellular assembly language uses a cell-state transition level description of the cellular program. Cell transition functions can be defined in the FUNDEF language. (FUNDEFis a machine independent language for transition function description, originally developed for the CELLAS cellular automata simulation system.) • Microassembly language ensures direct description of SP1 microprograms. The development system can be used in an IBM PC/XT, AT environment. It has the following components (Figure 2):
J
x
/ x
~
/
ichronized microassembly code)
]=. . . . .
--m
_
i linkage ~ditor i J J
| \executable ebject code ) /
:; . m ' ~ n t o ,
1
;]q !
Figure 2. Cellprocessor ment path
I develop-
Microprocessors and Microsystems
Update A control program, which runs on the host computer and organizes the cooperation between the host and the cellprocessor. a CCU program that runs on the cellprocessor and controls the work of the cellular array. The run-time system of the cellprocessor ensures that a cellular program can be reached from c using the following c functions: SPl LOAD (programname) loads the given cellular program, SPl RUN (programname, parameters) executes the loaded cellular program with the given parameters. The cellprocessor is provided with a basic library of cellular programs (for example: sorting, convolution, etc.). These cellular programs can be reached with the above cfunctions. If the user wants to create further cellular programs, the development system can be used.
Cellular
assembly
language
The language is architectureindependent in the sense that different types of cellprocessors can be programmed using this language. A cellular assembly program has different sections: l ARCH determines
the parameters of the given cellprocessor (size of the array, type of cells, etc.). ARCH
Vol 74 No 2 March 7990
informs the compiler how to translate the instructions of the program. INIT initial describes the configuration of the cellular array. INIT is transformed by the compiler into a loader CCU program module and into a data file to be loaded. CP gives the CCU program on state-transition-step level. Cell transition functions should be defined by the CELLAWUNDEF language and stored in CELLAS libraries. These libraries can be reached in the cellular assembly program. INPADDR and OUTADDR formulate the I/O processes between the host computerand the cellular array. HOST contains the description of the control program component of the cellular program.
Microassembly
language
This language is suitable for programming cellprocessors which differ only in the size of cellular array, number of I/O buffers, etc. The structure of the language is similar to that of cellular assembly language: ARCH determines the cellprocessor architecture CP contains the microinstruction level description of the CCU program. INPADDR, OUTADDR and HOST give a lower level description than
similar sections of assembly language.
the
cellular
SIMULATOR The menu controlled system offers simulation of complete cellular programs (including the host control program) so that it simulates the hardware on the one hand and the run-time system on the other. Its main functions are: Loading a cellular program Host control program simulation Hardware simulation on microstep level Editor for data files, to generate test data for cellular programs. Watching cellular array, registers, variables, etc. Every bit of the SPl hardware can be traced. Saving the state of simulation, and restoring a saved state.
SELECTED
REFERENCES
Legendi, T and Toth, J ‘A full custom Lsl based architecture for a megacell machine’ Proc. Int. Conf, Parallel Computing (1985) pp 503-507 Legendi, T and Zsoter, A ‘A 16-state cellprocessor’ Proc. Int. Conf. Parallel Computing (1985) pp 509-514
Legendi, T, Katona, E, Toth, J and Zsoter, A ‘Megacell machine’ Parallel Comput 199
(1988)
pp 195-
121