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Hybrid circuit analysis of a suspended gate silicon nanodot memory (SGSNM) cell
Microelectronic Engineering 87 (2010) 1284–1286
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Hybrid circuit analysis of a suspended gate silicon nanodot memory (SGSNM) cell M.A. Garcia-Ramirez a,*, Yoshishige Tsuchiya a,b, Hiroshi Mizuta a,b a b
Nano Group, School of Electronics and Computer Sciences, University of Southampton, SO17 1BJ, United Kingdom SORST JST (Japan Science and Technology), Japan
a r t i c l e
i n f o
Article history: Received 14 September 2009 Accepted 19 October 2009 Available online 25 October 2009 Keywords: Non-volatile memory Nano-electromechanical systems (NEMS) Suspended gate structure Electron tunnelling process Hybrid circuit simulation
a b s t r a c t We report a hybrid numerical analysis of the suspended gate silicon nanodot memory (SGSNM) which cointegrates nano-electromechanical systems (NEMS) with silicon MOSFET technology. We propose a new hybrid equivalent circuit model for the SGSNM, in which a parallel-connected variable gate capacitance and variable tunnel resistance model the suspended gate pull-in/pull-out operation and the electron tunnelling process through the tunnelling oxide layer. The signals for the programming, erasing and reading processes are successfully achieved in the circuit level simulation. The programming/erasing speed is found 2.5 ns which is a combination between the mechanical SG pull-in (0.8 ns) and the tunnelling process (1.7 ns). Those characteristics and the fact that the SGSNM does not use exotic materials but Si-based materials, makes the SGSNM a serious candidate for non-volatile random access memory applications. Ó 2009 Elsevier B.V. All rights reserved.
1. Introduction For the last two decades the non-volatile memory market has been driven by Flash memory which is used for a wide variety of devices and systems, from personal pen drives or MP3 players to large systems in planes or satellites. However, the conventional floating-gate memory technology in use for the Flash memory is facing a serious scalability issue, the oxide layer cannot be reduced smaller than 7 nm as manifested in ITRS2007 [1]. As one of promising candidates for a scalable non-volatile memory, we proposed a new suspended gate silicon nanodot memory (SGSNM) by co-integrating nano-electromechanical systems (NEMS), silicon nanodots (SiNDs), and MOSFETs [2]. The SGSNM can be manufactured within the conventional silicon technology and may achieve fast programming/erasing (P/E) operation as well as long data retention time without introducing any exotic materials. In this paper, we present a new hybrid circuit simulation to analyse the SGSNM cell and estimate the P/E times quantitatively. 2. SGSNM operation and modelling Fig. 1 shows a schematic of the SGSNM, which consists of a MOSFET as readout, SiNDs as a floating-gate (FG), and a movable suspended gate (SG) isolated from the FG by an air gap and a thin oxide layer. The advantages of the SGSNM cell over the typical Flash memory include high speed programming/erasing operations, virtually no gate leakage current and therefore a serious non-volatility, thanks to the presence of the air gap except for the program/erase processes. For programming the SGSNM cell, a * Corresponding author. Tel.: +44 (0) 23 8059 3126. E-mail address: [email protected] (M.A. Garcia-Ramirez). 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.10.019
negative voltage is applied to the SG. It is pulled-in on the tunnel oxide layer, resulting in the electrons injection from the SG into the FG through the tunnelling process. Note that the SG remains attached to the oxide layer until the applied voltage is reduced lower than the pull-out voltage due to the stiction caused by electrostatic, van der Waals and Casimir forces [3]. When the SG is pulled-out, the electron tunnelling process is stopped and the electrons remain stored in the FG which is isolated by an air gap from the SG. For erasing the cell, a positive voltage is applied, and the stored electrons are extracted from the FG. A basic fabrication process of the SGSNM is the following. After the thermal gate oxide is formed on the Si substrate, the Si-nanodots are deposited by using the VHF plasma CVD technique [4]. The upper thin gate oxide is then deposited, and a sacrificial layer of poly-Si is then deposited. Finally, a thin gate metal is deposited over the stacked layers. After patterning the top gate by using electron beam lithography, the sacrifice layer is selectively etched out, and the air gap is formed between the SG and the FG layer. In the present paper, we propose a hybrid equivalent circuit model for the SGSNM as shown in Fig. 2. It features a parallel-connected variable gate capacitance and variable tunnel resistance which are defined as a function of voltage between the SG and the FG. A compact model for the variable gate capacitance is extracted from the 3D finite element method (FEM) analysis conducted by using CoventorWare [5] to obtain the full pull-in/ pull-out characteristics for the doubly-clamped control gate. A compact model for the variable tunnel resistance is implemented based on the numerical simulation of quantum-mechanical tunnelling current through the top oxide layer [6]. The developed models are implemented into SmartSpice [7] by using an analog hardware description language (AHDL) such as Verilog-A.
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20
Displacement (nm)
Suspended control gate Air gap SiNDs Oxide layer
0
N+ bstra
N+
te
x 10
Capacitance (F)
P-Su
10
Fig. 1. Schematic diagram for the suspended gate silicon nanodot memory (SGSNM) cell.
4
2 0 2
0
6
4
8
10
MOSFET Fig. 4. Pull-in/pull-out characteristic curves for a 30-nm-thick SG and at 20-nmthick air gap, where (a) represents a hysteresis curve for D–V and (b) for C–V.
Vd Vg
We calculated the SG displacement–voltage (D–V) and capacitance–voltage (C–V) hysteresis curves by sweeping the SG voltage. Fig. 4 shows a full pull-in and pull-out characteristic for the 30nm-thick SG with the 20-nm-thick air gap when the positive gate voltage is applied. It shows a voltage window over which the SG remains in contact to the tunnel oxide – called stiction. The C–V curve is modelled by using a simple algebraic function in order to implement it as a compact model. The same processes are conducted for the negative gate voltage.
Memory node Fig. 2. Equivalent circuit model for the SGSNM cell.
3. Results and discussion 3.1. Suspended gate analysis Table 1 summarises a set of structural parameters which are carefully chosen in order to keep the programming voltage lower than 10 V. Fig. 3 shows the displacement of the beams calculated for all the structures in Table 1 as a function of the SG voltage.
Table 1 Parameters used to calculate the pull-in voltage. Material SG
Suspended gate (nm)
Air gap (nm)
Dimensions (lm nm)
Al Al Al Al
30 30 20 20
30 20 20 15
1 300 1 300 1 300 1 300
3.2. Tunnel barrier analysis Next a compact model for the variable tunnel resistance is constructed based on the numerical simulation of quantum-mechanical tunnelling current through the top gate oxide. The current density–voltage (J–V) characteristics are calculated for various tunnel oxide thicknesses by solving the 1D Schrödinger equation and Poisson’s equation self-consistently [6]. Fig. 5 shows the J–V characteristic curves for the SiO2 layer in thicknesses from 4 nm to 8 nm. As mentioned above, the SG stages (pull-in/pull-out window) are linked with the electron injection/ejection processes. In order to calculate the absolute values of the tunnel current, the
10
30 25
Current Density (A/cm2)
10
20 15
tair
10
SG
(nm)
5
10
0
−10
10
4 nm 5 nm 6 nm 7 nm 8 nm
−20
10
−30
10
0 −40
-5 0
10
1
2
3
4
5
6
7
0
2
4
6
8
10
Voltage (V) Fig. 3. Pull-in analysis for several air gaps and SG thicknesses.
Fig. 5. Current density–voltage FEM analysis for 4–8 nm SiO2 layer.
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Readout MOS Memory node Readout MOS VN (V) VSD (mV) current IDS (uA)
SG Voltage VSG (V)
PR E R . . .
(a)
10 0 -10
(b)
10
respectively. By assuming a 7-nm-thick top oxide layer, the results shown that the SGSNM cell achieves the tunnel charging for P/E times as short as 1.7 nsec. We also analyzed a mechanical switching time to pull-in the suspended gate by conducting transient 3D simulation and estimated the pull-in time of 0.8 nsec. From these results, we obtained a total program time of less than 3 nsec, suitable for fast and non-volatile memory applications.
5 0
Tunnel discharging 1.7 nsec
2
( c)
0 -2 0.4 0.2 0 0
Tunnel charging 1.7 nsec
(d)
‘1’ ‘0’
20
40
60
80
100
Time (ns) Fig. 6. Programming (P), erasing (E) and reading (R) waveform signals for the control gate (a), and the drain terminal of the readout MOSFET (b). The transient memory node voltage (c) and the MOSFET readout current (d).
current density is multiplied by the SG area in contact with the tunnel oxide which is obtained from the 3D FEM calculation as a function of the gate voltage. The tunnel current density increases by approximately five orders of magnitude in the low voltage (0– 2 V) region by decreasing the tunnel oxide thickness by 1 nm. In contrast, at high bias (9–10 V) current density variation drops to less than three magnitude orders. This is because the tunnelling current is dominated by the FN tunnelling in the high bias region while that in low bias region is governed by the direct tunnelling. Obviously the thinner the gate oxide, the larger the tunnel current and therefore the faster the P/E operations on the SGSNM. Once the J–V characteristic curve for 7 nm has been obtained, the data is implemented in AHDL in the same way for the C–V characteristics. 3.3. SGSNM cell implementation By using the developed hybrid modelling, the program (P)/erase (E)/read (R) processes are successfully analyzed as shown in Fig. 6. For the full SGSNM cell analysis a piece-wise linear (PWL) source is used as a gate voltage, Vg and a pulse source is used at the drain terminal of the MOSFET while the substrate and source terminals are grounded. The SG voltage and drain voltage waveforms are shown in Fig. 6a and b and the transient memory node voltage and the MOSFET readout current are shown in Fig. 6c and d,
4. Conclusions We analysed numerically a new hybrid non-volatile memory structure which co-integrates NEMS with MOS technology. The suspended gate was analysed through a double-clamped beam structure, where the parameters for pull-in, pull-out and stiction window were obtained. The tunnelling process was analysed by solving the 1D Schrödinger equation and Poisson’s equation selfconsistently so that the current density characteristic curve was obtained. In the circuit level cell implementation, the signals for the programming, erasing and reading processes were successfully achieved. The P/E speed found (2.5 ns) was a combination between the mechanical SG pull-in (0.8 ns) and the tunnelling process (1.7 ns). Those characteristics and the fact that the SGSNM does not use exotic materials but Si-based materials, makes the SGSNM a serious candidate for non-volatile random access memory applications. Acknowledgments The authors wish to thank Profs. S. Oda and K. Uchida and their laboratory members of Tokyo Institute of Technology, Dr. Z. Moktadir of University of Southampton, Prof. A. Sarmiento-Reyes, L.A. Sánchez-Gaspariano and V.R. González-Díaz of INAOE for valuable discussions. M.A. García-Ramírez also acknowledges the support from the National Science and Technology Council CONACyT México, under the scholarship 181944 in the UK. References [1] http://www.itrs.net/links/2007itrs/home2007.htm. [2] M.A. Garcia-Ramirez, H. Yoshimura, Y. Tsuchiya, H. Mizuta, Suspended gate silicon nanodot memory, in: ESSDERC/CIRC Fringe, P19, 2008. [3] B. Pruvost, H. Mizuta, S. Oda, 3-D Desing and analysis of functional nemsgate MOSFET and SETs, IEEE Transactions on Nanotechnology 6 (2) (2007) 218–224. [4] S. Oda, NeoSilicon materials and silicon nanodevices, Materials Science and Engineering B (2003) 19–23. [5] CoventorWare, CoventorWare MEMS reference manual 2008 (2008). [6] H. Mizuta, T. Tanoue, The Physics and Applications of Resonant Tunnelling Diodes, Cambridge Studies in Semiconductor Physics and Microelectronic Engineering, 1995. [7] http://www.silvaco.com/products/presentation/tcad/GuideTCAD.pdf.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Hybrid circuit analysis of a suspended gate silicon nanodot memory (SGSNM) cell M.A. Garcia-Ramirez a,*, Yoshishige Tsuchiya a,b, Hiroshi Mizuta a,b a b
Nano Group, School of Electronics and Computer Sciences, University of Southampton, SO17 1BJ, United Kingdom SORST JST (Japan Science and Technology), Japan
a r t i c l e
i n f o
Article history: Received 14 September 2009 Accepted 19 October 2009 Available online 25 October 2009 Keywords: Non-volatile memory Nano-electromechanical systems (NEMS) Suspended gate structure Electron tunnelling process Hybrid circuit simulation
a b s t r a c t We report a hybrid numerical analysis of the suspended gate silicon nanodot memory (SGSNM) which cointegrates nano-electromechanical systems (NEMS) with silicon MOSFET technology. We propose a new hybrid equivalent circuit model for the SGSNM, in which a parallel-connected variable gate capacitance and variable tunnel resistance model the suspended gate pull-in/pull-out operation and the electron tunnelling process through the tunnelling oxide layer. The signals for the programming, erasing and reading processes are successfully achieved in the circuit level simulation. The programming/erasing speed is found 2.5 ns which is a combination between the mechanical SG pull-in (0.8 ns) and the tunnelling process (1.7 ns). Those characteristics and the fact that the SGSNM does not use exotic materials but Si-based materials, makes the SGSNM a serious candidate for non-volatile random access memory applications. Ó 2009 Elsevier B.V. All rights reserved.
1. Introduction For the last two decades the non-volatile memory market has been driven by Flash memory which is used for a wide variety of devices and systems, from personal pen drives or MP3 players to large systems in planes or satellites. However, the conventional floating-gate memory technology in use for the Flash memory is facing a serious scalability issue, the oxide layer cannot be reduced smaller than 7 nm as manifested in ITRS2007 [1]. As one of promising candidates for a scalable non-volatile memory, we proposed a new suspended gate silicon nanodot memory (SGSNM) by co-integrating nano-electromechanical systems (NEMS), silicon nanodots (SiNDs), and MOSFETs [2]. The SGSNM can be manufactured within the conventional silicon technology and may achieve fast programming/erasing (P/E) operation as well as long data retention time without introducing any exotic materials. In this paper, we present a new hybrid circuit simulation to analyse the SGSNM cell and estimate the P/E times quantitatively. 2. SGSNM operation and modelling Fig. 1 shows a schematic of the SGSNM, which consists of a MOSFET as readout, SiNDs as a floating-gate (FG), and a movable suspended gate (SG) isolated from the FG by an air gap and a thin oxide layer. The advantages of the SGSNM cell over the typical Flash memory include high speed programming/erasing operations, virtually no gate leakage current and therefore a serious non-volatility, thanks to the presence of the air gap except for the program/erase processes. For programming the SGSNM cell, a * Corresponding author. Tel.: +44 (0) 23 8059 3126. E-mail address: [email protected] (M.A. Garcia-Ramirez). 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.10.019
negative voltage is applied to the SG. It is pulled-in on the tunnel oxide layer, resulting in the electrons injection from the SG into the FG through the tunnelling process. Note that the SG remains attached to the oxide layer until the applied voltage is reduced lower than the pull-out voltage due to the stiction caused by electrostatic, van der Waals and Casimir forces [3]. When the SG is pulled-out, the electron tunnelling process is stopped and the electrons remain stored in the FG which is isolated by an air gap from the SG. For erasing the cell, a positive voltage is applied, and the stored electrons are extracted from the FG. A basic fabrication process of the SGSNM is the following. After the thermal gate oxide is formed on the Si substrate, the Si-nanodots are deposited by using the VHF plasma CVD technique [4]. The upper thin gate oxide is then deposited, and a sacrificial layer of poly-Si is then deposited. Finally, a thin gate metal is deposited over the stacked layers. After patterning the top gate by using electron beam lithography, the sacrifice layer is selectively etched out, and the air gap is formed between the SG and the FG layer. In the present paper, we propose a hybrid equivalent circuit model for the SGSNM as shown in Fig. 2. It features a parallel-connected variable gate capacitance and variable tunnel resistance which are defined as a function of voltage between the SG and the FG. A compact model for the variable gate capacitance is extracted from the 3D finite element method (FEM) analysis conducted by using CoventorWare [5] to obtain the full pull-in/ pull-out characteristics for the doubly-clamped control gate. A compact model for the variable tunnel resistance is implemented based on the numerical simulation of quantum-mechanical tunnelling current through the top oxide layer [6]. The developed models are implemented into SmartSpice [7] by using an analog hardware description language (AHDL) such as Verilog-A.
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20
Displacement (nm)
Suspended control gate Air gap SiNDs Oxide layer
0
N+ bstra
N+
te
x 10
Capacitance (F)
P-Su
10
Fig. 1. Schematic diagram for the suspended gate silicon nanodot memory (SGSNM) cell.
4
2 0 2
0
6
4
8
10
MOSFET Fig. 4. Pull-in/pull-out characteristic curves for a 30-nm-thick SG and at 20-nmthick air gap, where (a) represents a hysteresis curve for D–V and (b) for C–V.
Vd Vg
We calculated the SG displacement–voltage (D–V) and capacitance–voltage (C–V) hysteresis curves by sweeping the SG voltage. Fig. 4 shows a full pull-in and pull-out characteristic for the 30nm-thick SG with the 20-nm-thick air gap when the positive gate voltage is applied. It shows a voltage window over which the SG remains in contact to the tunnel oxide – called stiction. The C–V curve is modelled by using a simple algebraic function in order to implement it as a compact model. The same processes are conducted for the negative gate voltage.
Memory node Fig. 2. Equivalent circuit model for the SGSNM cell.
3. Results and discussion 3.1. Suspended gate analysis Table 1 summarises a set of structural parameters which are carefully chosen in order to keep the programming voltage lower than 10 V. Fig. 3 shows the displacement of the beams calculated for all the structures in Table 1 as a function of the SG voltage.
Table 1 Parameters used to calculate the pull-in voltage. Material SG
Suspended gate (nm)
Air gap (nm)
Dimensions (lm nm)
Al Al Al Al
30 30 20 20
30 20 20 15
1 300 1 300 1 300 1 300
3.2. Tunnel barrier analysis Next a compact model for the variable tunnel resistance is constructed based on the numerical simulation of quantum-mechanical tunnelling current through the top gate oxide. The current density–voltage (J–V) characteristics are calculated for various tunnel oxide thicknesses by solving the 1D Schrödinger equation and Poisson’s equation self-consistently [6]. Fig. 5 shows the J–V characteristic curves for the SiO2 layer in thicknesses from 4 nm to 8 nm. As mentioned above, the SG stages (pull-in/pull-out window) are linked with the electron injection/ejection processes. In order to calculate the absolute values of the tunnel current, the
10
30 25
Current Density (A/cm2)
10
20 15
tair
10
SG
(nm)
5
10
0
−10
10
4 nm 5 nm 6 nm 7 nm 8 nm
−20
10
−30
10
0 −40
-5 0
10
1
2
3
4
5
6
7
0
2
4
6
8
10
Voltage (V) Fig. 3. Pull-in analysis for several air gaps and SG thicknesses.
Fig. 5. Current density–voltage FEM analysis for 4–8 nm SiO2 layer.
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Readout MOS Memory node Readout MOS VN (V) VSD (mV) current IDS (uA)
SG Voltage VSG (V)
PR E R . . .
(a)
10 0 -10
(b)
10
respectively. By assuming a 7-nm-thick top oxide layer, the results shown that the SGSNM cell achieves the tunnel charging for P/E times as short as 1.7 nsec. We also analyzed a mechanical switching time to pull-in the suspended gate by conducting transient 3D simulation and estimated the pull-in time of 0.8 nsec. From these results, we obtained a total program time of less than 3 nsec, suitable for fast and non-volatile memory applications.
5 0
Tunnel discharging 1.7 nsec
2
( c)
0 -2 0.4 0.2 0 0
Tunnel charging 1.7 nsec
(d)
‘1’ ‘0’
20
40
60
80
100
Time (ns) Fig. 6. Programming (P), erasing (E) and reading (R) waveform signals for the control gate (a), and the drain terminal of the readout MOSFET (b). The transient memory node voltage (c) and the MOSFET readout current (d).
current density is multiplied by the SG area in contact with the tunnel oxide which is obtained from the 3D FEM calculation as a function of the gate voltage. The tunnel current density increases by approximately five orders of magnitude in the low voltage (0– 2 V) region by decreasing the tunnel oxide thickness by 1 nm. In contrast, at high bias (9–10 V) current density variation drops to less than three magnitude orders. This is because the tunnelling current is dominated by the FN tunnelling in the high bias region while that in low bias region is governed by the direct tunnelling. Obviously the thinner the gate oxide, the larger the tunnel current and therefore the faster the P/E operations on the SGSNM. Once the J–V characteristic curve for 7 nm has been obtained, the data is implemented in AHDL in the same way for the C–V characteristics. 3.3. SGSNM cell implementation By using the developed hybrid modelling, the program (P)/erase (E)/read (R) processes are successfully analyzed as shown in Fig. 6. For the full SGSNM cell analysis a piece-wise linear (PWL) source is used as a gate voltage, Vg and a pulse source is used at the drain terminal of the MOSFET while the substrate and source terminals are grounded. The SG voltage and drain voltage waveforms are shown in Fig. 6a and b and the transient memory node voltage and the MOSFET readout current are shown in Fig. 6c and d,
4. Conclusions We analysed numerically a new hybrid non-volatile memory structure which co-integrates NEMS with MOS technology. The suspended gate was analysed through a double-clamped beam structure, where the parameters for pull-in, pull-out and stiction window were obtained. The tunnelling process was analysed by solving the 1D Schrödinger equation and Poisson’s equation selfconsistently so that the current density characteristic curve was obtained. In the circuit level cell implementation, the signals for the programming, erasing and reading processes were successfully achieved. The P/E speed found (2.5 ns) was a combination between the mechanical SG pull-in (0.8 ns) and the tunnelling process (1.7 ns). Those characteristics and the fact that the SGSNM does not use exotic materials but Si-based materials, makes the SGSNM a serious candidate for non-volatile random access memory applications. Acknowledgments The authors wish to thank Profs. S. Oda and K. Uchida and their laboratory members of Tokyo Institute of Technology, Dr. Z. Moktadir of University of Southampton, Prof. A. Sarmiento-Reyes, L.A. Sánchez-Gaspariano and V.R. González-Díaz of INAOE for valuable discussions. M.A. García-Ramírez also acknowledges the support from the National Science and Technology Council CONACyT México, under the scholarship 181944 in the UK. References [1] http://www.itrs.net/links/2007itrs/home2007.htm. [2] M.A. Garcia-Ramirez, H. Yoshimura, Y. Tsuchiya, H. Mizuta, Suspended gate silicon nanodot memory, in: ESSDERC/CIRC Fringe, P19, 2008. [3] B. Pruvost, H. Mizuta, S. Oda, 3-D Desing and analysis of functional nemsgate MOSFET and SETs, IEEE Transactions on Nanotechnology 6 (2) (2007) 218–224. [4] S. Oda, NeoSilicon materials and silicon nanodevices, Materials Science and Engineering B (2003) 19–23. [5] CoventorWare, CoventorWare MEMS reference manual 2008 (2008). [6] H. Mizuta, T. Tanoue, The Physics and Applications of Resonant Tunnelling Diodes, Cambridge Studies in Semiconductor Physics and Microelectronic Engineering, 1995. [7] http://www.silvaco.com/products/presentation/tcad/GuideTCAD.pdf.