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IAPDL-based low-power adiabatic programmable logic array
Microelectronics Journal Microelectronics Journal 31 (2000) 235–238 www.elsevier.com/locate/mejo
IAPDL-based low-power adiabatic programmable logic array K.T. Lau*, F. Liu Microelectronics Centre, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore Accepted 3 June 1999
Abstract A novel low power programmable logic array structure based on adiabatic switching is presented. Simulation results using HSPICE with 0.8 mm technology designs show that the power savings of the proposed adiabatic programmable logic array (PLA) circuit is up to 60%, compared to the dynamic PLA circuit. Compared to APDL (Adiabatic Pseudo-Domino Logic) PLA, the power saving is about 15% and the device count savings is about 20%. The power saving is improved further at lower supply voltages. At 2 V Vdd and 200 MHz clock frequency, the power saving is about 25% compared to APDL PLA. Compared to static PLA, the power saving is even more significant. HSPICE simulations also show that the proposed PLA can function correctly up to 1 GHz at 5 V Vdd, and the supply voltage can be scaled down to 2 V at 200 MHz. q 2000 Elsevier Science Ltd. All rights reserved. Keywords: Adiabatic pseudo-domino logic; Programmable logic array; HSPICE
1. Introduction When implementing complex control logic in CMOS, a designer can generally fall back on two options, i.e. to map the multilevel Boolean function into a network of individual CMOS logic gates after optimizing the logic function either for area or delay and to bring the logic function into a canonical format called the two-level sum-of-products representation. This representation can be mapped onto a very regular implementation, using the programmable logic array (PLA) circuit structure [1]. The general arrangement of a PLA consists of a programmable two-level AND/OR structure. However, for MOS fabrication, AND and OR gates are neither as simple nor as suitable as the NOR gate, and also due to the relatively slow speed of a large fan-in NAND gate, the NOR–NOR structure is preferred in general. However, although this NOR–NOR structure is compact and fast, its power dissipation makes it unattractive for larger PLAs where a dynamic approach is better [1]. By using the proposed adiabatic PLA structure, a direct cascade of the dynamic planes is possible. This is not always true for conventional dynamic implementations. In addition, the power dissipation for the proposed adiabatic PLA structure is further reduced with no considerable increase in circuit complexity. An adiabatic PLA structure has been proposed in Ref. [2]. In this paper, a new * Corresponding author. Tel.: 00-65-790-5420; fax: 00-65-791-2687. E-mail address: [email protected] (K.T. Lau)
adiabatic PLA structure is proposed that has better power performance and fewer devices than that proposed in Ref. [2]. 2. Circuit description In this paper, the IAPDL (Improved APDL) structure [3] is used to substitute the APDL structure [4] for input isolation and low power in the PLA AND array in [2]. Fig. 1 shows the basic circuit structure for the IAPDL AND array to generate each product term (Pn). The two non-overlapping triangular-like clock supplies, VCLK_AND and VCLK_OR, and the corresponding auxiliary clock, CA_AND, are shown in Fig. 2. CA_AND and CA_OR have three phases each, i.e. precharge (P), evaluate (E) and hold (H). The auxiliary clock CA_AND is held high during the precharge and evaluates phases of VCLK_AND, and low during the hold phase. During the precharge phase of VCLK_AND, when VCLK_AND ramps up, each product term (Pn) is precharged to high. As CA_AND is held high during the precharge and evaluate phases of VCLK_AND, the isolation NMOS transistor mn1 as in Fig. 1, which is controlled by the auxiliary clock CA_AND, is switched on during the precharge and evaluate phases. Thus, during the evaluate phase, when VCLK_AND ramps down, the product term (Pn) evaluates the corresponding value according to the input signals. If all inputs are low, then the product term is held high. If one of the inputs is high, then the product term is discharged to low,
0026-2692/00/$ - see front matter q 2000 Elsevier Science Ltd. All rights reserved. PII: S0026-269 2(99)00105-6
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K.T. Lau, F. Liu / Microelectronics Journal 31 (2000) 235–238 Zn
VCLK_AND D1
P1
P2
P3
D1
Pn
mn2
D2 CL
Pn VCLK_OR IN1
IN2
IN3
INn
Fig. 3. Basic structure in the IAPDL-based OR array.
mn1
CA_AND
VCLK_AND
Fig. 1. Basic structure in the IAPDL-based AND array for each product term.
i.e. logic NOR operation is achieved. During the hold phase of VCLK_AND, CA_AND is held low, the isolation NMOS transistor, mn1, is switched off. Therefore, during the hold phase of VCLK_AND, the product output (Pn) is isolated from the input signals and retains the evaluated value. This input for the OR array is then kept stable during the precharge and evaluate phases of VCLK_OR. For the OR array, the ADL structure [5] is used as shown in [2]. The basic circuit structure of the OR array as shown in Fig. 3 is similar to the AND array except for the isolation transistor. The cascaded inverter formed by mn2-D2 is designed to implement logic OR operation, and to prevent the output state of Zn from being changed by Pn during the hold phase of VCLK_OR. The operation of the OR array is similar to the AND array.
3. Simulation results and discussion As shown in Fig. 1, as the isolation NMOS transistor mn1 is controlled by the auxiliary clock, CA_AND, instead of the complement of the product output as in APDL PLA [2], the complementary part of the AND array is absent, thus, saving two devices for each product term. For a large PLA, a 2N reduction in devices is achieved, where N is the number of product terms. Additionally, power dissipation is reduced correspondingly, as can be seen from HSPICE simulation results. Various 5 × 8 × 4 PLAs (static PLA, dynamic PLA,
APDL PLA and IAPDL PLA) were designed, HSPICEsimulated and compared. For the 5 × 8 × 4 PLA designs, IAPDL PLA uses 62 devices while APDL PLA uses 78 devices. Sixteen devices N 8 including eight transistors and eight diodes are saved. The device count saving of IAPDL PLA is about 20% compared to APDL PLA. The simulations are based on 0.8 mm CMOS N-well technology. The logic equations [6] implemented in the simulation are as follows: Z1 abde 1 abcde 1 bc 1 de Z2 ace Z3 bd 1 cde 1 bc 1 de Z4 ace 1 ce where Zn are the outputs and a, b, c, d and e are the inputs. There are five input variables for the PLA, and the simulations covered all the possible combinations of the input states. Fig. 4 shows the simulation waveforms of IAPDL PLA at 200 MHz clock frequency. All the clock signals were assumed to be generated externally for the various designs, and the power dissipation data for generating the Table 1 Power dissipation for various PLAs at different clock frequencies (units: mW) Clock frequencies (MHz)
50
100
200
250
Static PLA Dynamic PLA APDL PLA IAPDL PLA
15.28 0.76 0.36 0.31
15.46 1.35 0.80 0.66
15.78 2.56 2.02 1.72
15.95 3.22 2.63 2.26
Table 2 Power dissipation for various PLAs with voltage supply scaling from 5 to 2 V (units: mW; clock frequency 200 MHz) Power dissipation
Fig. 2. Clock supplies used in IAPDL PLA circuit.
Static PLA Dynamic PLA APDL PLA IAPDL PLA
Vdd (V) 5.0
4.0
3.0
2.5
2.0
15.78 2.56 2.02 1.72
8.39 1.62 1.30 1.14
3.50 0.85 0.82 0.61
1.92 0.53 0.50 0.36
0.86 0.28 0.23 0.17
K.T. Lau, F. Liu / Microelectronics Journal 31 (2000) 235–238
237
Fig. 4. Simulation waveforms of IAPDL PLA at 200 MHz clock frequency. (a) Input variables. (b) Clock supplies and output waveforms of the IAPDL PLA.
0.28 mW. At 200 MHz and the lowest operating voltage supply, 2 V, the power saving of the IAPDL PLA is about 40% compared to the dynamic PLA, and is about 25% compared to the APDL PLA. To display the results more clearly, the power dissipation data of dynamic PLA, APDL PLA and IAPDL PLA at 200 MHz with voltage scaling are reproduced in Fig. 6. 3.5
Dynamic PLA APDL PLA
3
Power dissipation (mW)
clock signals were not taken into account. The static PLA uses the same input patterns as other PLAs at the corresponding frequencies. The average power dissipation data for the various PLAs (static PLA, dynamic PLA, APDL PLA and IAPDL PLA) at different clock frequencies are shown in Table 1. The power dissipation of the IAPDL PLA is about 85% that of the APDL PLA at different clock frequencies. Compared to the dynamic PLA, the power saving ranges from 30 to 60% for the operating frequency varying from 50 to 250 MHz. Compared to the power dissipation of the static PLA, which is about 15 mW at different frequencies, the power saving of IAPDL PLA is even more significant. The power dissipation data of dynamic PLA, APDL PLA and IAPDL PLA are also reproduced in Fig. 5. HSPICE simulations also show that the IAPDL PLA can function up to 1 GHz. Simulations were also performed with voltage supply scaling. The power dissipation data at 200 MHz clock frequency are shown in Table 2. It can be seen that all the PLAs can function properly till the voltage supply scales down to 2 V at 200 MHz clock frequency. With the voltage supply scaling from 5 to 2 V, the power dissipation of the IAPDL PLA reduces from 1.72 to 0.17 mW, and the power dissipation of the dynamic PLA reduces from 2.56 to
IAPDL PLA
2.5
2
1.5
1
0.5
0 0
50
100
150
200
250
300
Frequency (MHz) Fig. 5. Power dissipation for various PLAs at different clock frequencies.
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K.T. Lau, F. Liu / Microelectronics Journal 31 (2000) 235–238
(IAPDL PLA) with a simple clock supply is presented. HSPICE simulation results show that up to 60% power saving can be achieved compared to CMOS dynamic PLA. Compared to APDL PLA, the power saving is about 15% and device count is reduced. For the 5 × 8 × 4 PLA design, eight transistors and eight diodes are saved, the device count saving is about 20%. The power saving is even better at lower supply voltage. At 2 V Vdd and 200 MHz clock frequency, the power saving is about 40% compared to CMOS dynamic PLA, and is about 25% compared to APDL PLA. HSPICE simulations also show that the IAPDL PLA can function properly up to 1 GHz.
3 Dyn a m ic P LA 2.5
F=200 MHz
AP DL P LA
Power dissipation (mW)
IAP DL P LA 2
1.5
1
0.5
0 1.5
2.5
3.5
4.5
5.5
Vdd (V)
Fig. 6. Power dissipation for various PLAs with voltage supply scaling from 5 to 2 V.
In the simulations based on N-well process, PMOS transistors are used to form the diodes. A PMOS transistor in a separate N-well is used to form an equivalent junction diode. The source and drain of the PMOS transistor are connected to power clock, VCLK_AND or VCLK_OR. The body of the PMOS transistor is connected to the output. The gate of the PMOS transistor is connected to Vdd to prevent the channel from conducting. The typical value of the forward voltage drop of the PMOS-implemented diode is about 0.5 V. 4. Conclusion A novel implementation of a low power PLA circuit
References [1] J.M. Rabaey, Digital Integrated Circuits—A Design Perspective, Electronics and VLSI Series, Prentice-Hall, Englewood Cliffs, NJ, 1996. [2] K.T. Lau, W.Y. Wang, Low-power programmable logic array using energy recovery principles, Seventh International Symposium on IC Technology, Systems and Applications (ISIC-97), September 1997, Singapore, pp. 538–540. [3] K.T. Lau, F. Liu, An improved adiabatic pseudo-domino logic family, Electronics Letters 33 (25) (1997) 2113–2114. [4] W.Y. Wang, K.T. Lau, Adiabatic pseudo-domino logic, Electronics Letters 31 (23) (1995) 1982–1983. [5] A.G. Dickinson, J.S. Denker, Adiabatic dynamic logic, Proceedings of the Custom Integrated Circuits Conference, 1994, pp. 282–285. [6] D. Pucknell, K. Eshraghian, Basic VLSI Design, Prentice-Hall, Englewood Cliffs, NJ, 1994.
IAPDL-based low-power adiabatic programmable logic array K.T. Lau*, F. Liu Microelectronics Centre, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore Accepted 3 June 1999
Abstract A novel low power programmable logic array structure based on adiabatic switching is presented. Simulation results using HSPICE with 0.8 mm technology designs show that the power savings of the proposed adiabatic programmable logic array (PLA) circuit is up to 60%, compared to the dynamic PLA circuit. Compared to APDL (Adiabatic Pseudo-Domino Logic) PLA, the power saving is about 15% and the device count savings is about 20%. The power saving is improved further at lower supply voltages. At 2 V Vdd and 200 MHz clock frequency, the power saving is about 25% compared to APDL PLA. Compared to static PLA, the power saving is even more significant. HSPICE simulations also show that the proposed PLA can function correctly up to 1 GHz at 5 V Vdd, and the supply voltage can be scaled down to 2 V at 200 MHz. q 2000 Elsevier Science Ltd. All rights reserved. Keywords: Adiabatic pseudo-domino logic; Programmable logic array; HSPICE
1. Introduction When implementing complex control logic in CMOS, a designer can generally fall back on two options, i.e. to map the multilevel Boolean function into a network of individual CMOS logic gates after optimizing the logic function either for area or delay and to bring the logic function into a canonical format called the two-level sum-of-products representation. This representation can be mapped onto a very regular implementation, using the programmable logic array (PLA) circuit structure [1]. The general arrangement of a PLA consists of a programmable two-level AND/OR structure. However, for MOS fabrication, AND and OR gates are neither as simple nor as suitable as the NOR gate, and also due to the relatively slow speed of a large fan-in NAND gate, the NOR–NOR structure is preferred in general. However, although this NOR–NOR structure is compact and fast, its power dissipation makes it unattractive for larger PLAs where a dynamic approach is better [1]. By using the proposed adiabatic PLA structure, a direct cascade of the dynamic planes is possible. This is not always true for conventional dynamic implementations. In addition, the power dissipation for the proposed adiabatic PLA structure is further reduced with no considerable increase in circuit complexity. An adiabatic PLA structure has been proposed in Ref. [2]. In this paper, a new * Corresponding author. Tel.: 00-65-790-5420; fax: 00-65-791-2687. E-mail address: [email protected] (K.T. Lau)
adiabatic PLA structure is proposed that has better power performance and fewer devices than that proposed in Ref. [2]. 2. Circuit description In this paper, the IAPDL (Improved APDL) structure [3] is used to substitute the APDL structure [4] for input isolation and low power in the PLA AND array in [2]. Fig. 1 shows the basic circuit structure for the IAPDL AND array to generate each product term (Pn). The two non-overlapping triangular-like clock supplies, VCLK_AND and VCLK_OR, and the corresponding auxiliary clock, CA_AND, are shown in Fig. 2. CA_AND and CA_OR have three phases each, i.e. precharge (P), evaluate (E) and hold (H). The auxiliary clock CA_AND is held high during the precharge and evaluates phases of VCLK_AND, and low during the hold phase. During the precharge phase of VCLK_AND, when VCLK_AND ramps up, each product term (Pn) is precharged to high. As CA_AND is held high during the precharge and evaluate phases of VCLK_AND, the isolation NMOS transistor mn1 as in Fig. 1, which is controlled by the auxiliary clock CA_AND, is switched on during the precharge and evaluate phases. Thus, during the evaluate phase, when VCLK_AND ramps down, the product term (Pn) evaluates the corresponding value according to the input signals. If all inputs are low, then the product term is held high. If one of the inputs is high, then the product term is discharged to low,
0026-2692/00/$ - see front matter q 2000 Elsevier Science Ltd. All rights reserved. PII: S0026-269 2(99)00105-6
236
K.T. Lau, F. Liu / Microelectronics Journal 31 (2000) 235–238 Zn
VCLK_AND D1
P1
P2
P3
D1
Pn
mn2
D2 CL
Pn VCLK_OR IN1
IN2
IN3
INn
Fig. 3. Basic structure in the IAPDL-based OR array.
mn1
CA_AND
VCLK_AND
Fig. 1. Basic structure in the IAPDL-based AND array for each product term.
i.e. logic NOR operation is achieved. During the hold phase of VCLK_AND, CA_AND is held low, the isolation NMOS transistor, mn1, is switched off. Therefore, during the hold phase of VCLK_AND, the product output (Pn) is isolated from the input signals and retains the evaluated value. This input for the OR array is then kept stable during the precharge and evaluate phases of VCLK_OR. For the OR array, the ADL structure [5] is used as shown in [2]. The basic circuit structure of the OR array as shown in Fig. 3 is similar to the AND array except for the isolation transistor. The cascaded inverter formed by mn2-D2 is designed to implement logic OR operation, and to prevent the output state of Zn from being changed by Pn during the hold phase of VCLK_OR. The operation of the OR array is similar to the AND array.
3. Simulation results and discussion As shown in Fig. 1, as the isolation NMOS transistor mn1 is controlled by the auxiliary clock, CA_AND, instead of the complement of the product output as in APDL PLA [2], the complementary part of the AND array is absent, thus, saving two devices for each product term. For a large PLA, a 2N reduction in devices is achieved, where N is the number of product terms. Additionally, power dissipation is reduced correspondingly, as can be seen from HSPICE simulation results. Various 5 × 8 × 4 PLAs (static PLA, dynamic PLA,
APDL PLA and IAPDL PLA) were designed, HSPICEsimulated and compared. For the 5 × 8 × 4 PLA designs, IAPDL PLA uses 62 devices while APDL PLA uses 78 devices. Sixteen devices N 8 including eight transistors and eight diodes are saved. The device count saving of IAPDL PLA is about 20% compared to APDL PLA. The simulations are based on 0.8 mm CMOS N-well technology. The logic equations [6] implemented in the simulation are as follows: Z1 abde 1 abcde 1 bc 1 de Z2 ace Z3 bd 1 cde 1 bc 1 de Z4 ace 1 ce where Zn are the outputs and a, b, c, d and e are the inputs. There are five input variables for the PLA, and the simulations covered all the possible combinations of the input states. Fig. 4 shows the simulation waveforms of IAPDL PLA at 200 MHz clock frequency. All the clock signals were assumed to be generated externally for the various designs, and the power dissipation data for generating the Table 1 Power dissipation for various PLAs at different clock frequencies (units: mW) Clock frequencies (MHz)
50
100
200
250
Static PLA Dynamic PLA APDL PLA IAPDL PLA
15.28 0.76 0.36 0.31
15.46 1.35 0.80 0.66
15.78 2.56 2.02 1.72
15.95 3.22 2.63 2.26
Table 2 Power dissipation for various PLAs with voltage supply scaling from 5 to 2 V (units: mW; clock frequency 200 MHz) Power dissipation
Fig. 2. Clock supplies used in IAPDL PLA circuit.
Static PLA Dynamic PLA APDL PLA IAPDL PLA
Vdd (V) 5.0
4.0
3.0
2.5
2.0
15.78 2.56 2.02 1.72
8.39 1.62 1.30 1.14
3.50 0.85 0.82 0.61
1.92 0.53 0.50 0.36
0.86 0.28 0.23 0.17
K.T. Lau, F. Liu / Microelectronics Journal 31 (2000) 235–238
237
Fig. 4. Simulation waveforms of IAPDL PLA at 200 MHz clock frequency. (a) Input variables. (b) Clock supplies and output waveforms of the IAPDL PLA.
0.28 mW. At 200 MHz and the lowest operating voltage supply, 2 V, the power saving of the IAPDL PLA is about 40% compared to the dynamic PLA, and is about 25% compared to the APDL PLA. To display the results more clearly, the power dissipation data of dynamic PLA, APDL PLA and IAPDL PLA at 200 MHz with voltage scaling are reproduced in Fig. 6. 3.5
Dynamic PLA APDL PLA
3
Power dissipation (mW)
clock signals were not taken into account. The static PLA uses the same input patterns as other PLAs at the corresponding frequencies. The average power dissipation data for the various PLAs (static PLA, dynamic PLA, APDL PLA and IAPDL PLA) at different clock frequencies are shown in Table 1. The power dissipation of the IAPDL PLA is about 85% that of the APDL PLA at different clock frequencies. Compared to the dynamic PLA, the power saving ranges from 30 to 60% for the operating frequency varying from 50 to 250 MHz. Compared to the power dissipation of the static PLA, which is about 15 mW at different frequencies, the power saving of IAPDL PLA is even more significant. The power dissipation data of dynamic PLA, APDL PLA and IAPDL PLA are also reproduced in Fig. 5. HSPICE simulations also show that the IAPDL PLA can function up to 1 GHz. Simulations were also performed with voltage supply scaling. The power dissipation data at 200 MHz clock frequency are shown in Table 2. It can be seen that all the PLAs can function properly till the voltage supply scales down to 2 V at 200 MHz clock frequency. With the voltage supply scaling from 5 to 2 V, the power dissipation of the IAPDL PLA reduces from 1.72 to 0.17 mW, and the power dissipation of the dynamic PLA reduces from 2.56 to
IAPDL PLA
2.5
2
1.5
1
0.5
0 0
50
100
150
200
250
300
Frequency (MHz) Fig. 5. Power dissipation for various PLAs at different clock frequencies.
238
K.T. Lau, F. Liu / Microelectronics Journal 31 (2000) 235–238
(IAPDL PLA) with a simple clock supply is presented. HSPICE simulation results show that up to 60% power saving can be achieved compared to CMOS dynamic PLA. Compared to APDL PLA, the power saving is about 15% and device count is reduced. For the 5 × 8 × 4 PLA design, eight transistors and eight diodes are saved, the device count saving is about 20%. The power saving is even better at lower supply voltage. At 2 V Vdd and 200 MHz clock frequency, the power saving is about 40% compared to CMOS dynamic PLA, and is about 25% compared to APDL PLA. HSPICE simulations also show that the IAPDL PLA can function properly up to 1 GHz.
3 Dyn a m ic P LA 2.5
F=200 MHz
AP DL P LA
Power dissipation (mW)
IAP DL P LA 2
1.5
1
0.5
0 1.5
2.5
3.5
4.5
5.5
Vdd (V)
Fig. 6. Power dissipation for various PLAs with voltage supply scaling from 5 to 2 V.
In the simulations based on N-well process, PMOS transistors are used to form the diodes. A PMOS transistor in a separate N-well is used to form an equivalent junction diode. The source and drain of the PMOS transistor are connected to power clock, VCLK_AND or VCLK_OR. The body of the PMOS transistor is connected to the output. The gate of the PMOS transistor is connected to Vdd to prevent the channel from conducting. The typical value of the forward voltage drop of the PMOS-implemented diode is about 0.5 V. 4. Conclusion A novel implementation of a low power PLA circuit
References [1] J.M. Rabaey, Digital Integrated Circuits—A Design Perspective, Electronics and VLSI Series, Prentice-Hall, Englewood Cliffs, NJ, 1996. [2] K.T. Lau, W.Y. Wang, Low-power programmable logic array using energy recovery principles, Seventh International Symposium on IC Technology, Systems and Applications (ISIC-97), September 1997, Singapore, pp. 538–540. [3] K.T. Lau, F. Liu, An improved adiabatic pseudo-domino logic family, Electronics Letters 33 (25) (1997) 2113–2114. [4] W.Y. Wang, K.T. Lau, Adiabatic pseudo-domino logic, Electronics Letters 31 (23) (1995) 1982–1983. [5] A.G. Dickinson, J.S. Denker, Adiabatic dynamic logic, Proceedings of the Custom Integrated Circuits Conference, 1994, pp. 282–285. [6] D. Pucknell, K. Eshraghian, Basic VLSI Design, Prentice-Hall, Englewood Cliffs, NJ, 1994.