IC-internal logic verification using an integrated electron beam measurement system

Microelectronic Engineering 6 (1987) 661-666 North-Holland

661

I C - I N T E R N A L LOGIC V E R I F I C A T I O N USING A N ELECTRON BEAM MEASUREMENT SYSTEM S.G6rlich,

H.Harbeck,

INTEGRATED

P.Ke~ler

C o r p o r a t e R e s e a r c h and Development, Siemens O t t o - H a h n - R i n g 6, D-8000 M u n i c h 83, F.R.G.

AG

An integrated electron beam measurement system (IEMS), integrating the areas of design, t e s t i n g and electron beam testing, has been developed to support chip v e r i f i c a t i o n and failure analysis. The s y s t e m components are a CAD w o r k s t a t i o n , a verification tester and an automated e l e c t r o n b e a m tester. IEMS is a s o l u t i o n to verification problems a r i s i n g from the complexity of m o d e r n VLSI circuits. The m e t h o d o l g y and the procedure for I C - i n t e r n a l logic v e r i f i c a t i o n are d e m o n s t r a t e d . I. I N T R O D U C T I O N The d e v e l o p m e n t of i n t e g r a t e d circuits(IC) towards h i g h e r integration i n v o l v e s not o n l y the need to b e t t e r m a n u f a c t u r i n g t e c h n i q u e s but a l s o to b e t t e r v e r i f i c a t i o n techniques to a n a l y s e the e l e c t r i cal functioning. Since the n u m b e r of e x t e r n a l pins at w h i c h this testing is performed continues to d e c r e a s e in r e l a t i o n to the n u m b e r of i n t e r n a l gates, the only s o l u t i o n to d e t e c t , l o c a l i z e and understand internal w e a k n e s s e s is to m a k e internal measurements within the IC. The e l e c t r o n b e a m probe in particular has the following a d v a n t a g e s [i]: it is c o n t a c t l e s s and t h e r e f o r e nondestructive and nonloading, it allows I C - i n t e r n a l m e a s u r e m e n t s of logic states and w a v e f o r m s w i t h high spatial (
0167-9317/87/$3.50 © 1987, ElsevierSciencePublishers B.V. (North-Holland)

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Fig.2: P h o t o g r a p h of the IEMS: CAD-workstation (a), p r o c e s s computer (b), SEM-electronics (c), column and x-y-table (d), ICt e s t e r ( e ) , e l e c t r o n i c s of EBT (f)

A p h o t o g r a p h y of the r e a l i s e d i n t e g r a t e d e l e c t r o n b e a m m e a s u r e m e n t s y s t e m (IEMS) is shown in Fig.2. In c o n t r a s t to Fig.l a low cost I C - t e s t e r [6] n o r m a l y used for v e r i f i c a t i o n t e s t i n g is integrated within IEMS i n s t e a d of a high cost ATE. The s y s t e m (see blockdiagram, Fig.3) consists of a w o r k s t a t i o n of the same type used in the d e s i g n system, the I C - t e s t e r c o n t r o l l e d by a low cost w o r k s t a tion of the same type ,which enables test control and simulation w i t h i n the CAD o p e r a t i n g system, and the in house d e v e l o p e d AEBT [7]. Of special i m p o r t a n c e are the t u r n e d around column and the xy-table, e n a b l i n g a direct c o n n e c t i o n of the I C - T e s t e r to the DUT inside the A E B T (see Fig4.) and an a c c u r a t e p o s i t i o n i n g of the ebeam, respectively. The v e r i f i c a t i o n p r o c e d u r e and data t r a n s f e r using IEMS are the same as i n d i c a t e d in Fig.l. The IC is d e s i g n e d at a CAD system c o n s i s t i n g of w o r k s t a t i o n s of the same type. Logic vs. layout v e r i f i c a t i o n , Spice, logic and failure s i m u l a t i o n as well as test g e n e r a t i o n are p e r f o r m e d there, too. P r o d u c t i o n and p r o t o t y p e testing take place at an ATE outside of I E M S . B u t all data can e a s i l y be taken from CAD and ATE to IEMS. Details of the system and its components are d e s c r i b e d in [3]. Workstation Logic,layout, simulationdata

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S. G~rlich et al. / IC-internal log& verification

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Fig.4: Photographies of the c o n n e c t i o n of I C - T e s t e r to the A E B T w i t h v a c u u m c h a m b e r open (a) and closed (b), i.e r e a d y for test 3. V E R I F I C A T I O N

PROCEDURE

The chip v e r i f i c a t i o n is c a r r i e d out by the designer, w h o is familiar w i t h the d e s i g n of the chip and the w o r k s t a t i o n , a n d the operator, w h o is f a m i l i a r w i t h A E B T and IEMS. The m e t h o d o l o g y [2] is based on the idea of point p r o b i n g w i t h the e - b e a m inside the IC f o l l o w i n g the signals in the logic plan b e t w e e n the inputs and the f a u l t y outputs. The p r o c e d u r e is s u m m a r i z e d in Fig.5. A f t e r the d e t e c t i o n of a w e a k n e s s or failure of a n e w chip at ATE this IC is p r e p a r e d for the EBT. N o r m a l l y chips in c e r a m i c p a c k a g e without a p a s s i v a t i o n layer are used. The d e s i g n e r d e c i d e s w h i c h test data are s e l e c t e d and t r a n s f e r e d from A T E to IEMS. At the IC-tester these data are p r e p a r e d for the electron beam test t e c h n i q u e s by g e n e r a t i n g a test loop to drive the DUT. By e x t e r n a l t e s t i n g it is e x a m i n e d w h e t h e r this test loop r e a l l y causes the I~ [] D [] Fo, I each i [] woak.J [] nasa I [] [] i For each J ITP J I

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m a l f u n c t i o n to analyse. For an a u t o m a t e d p o s i t i o n i n g of the e - b e a m on i n t e r n a l nodes a chip a l i g n e m e n t in A E B T is a p r e c o n d i t i o n . By this the c o o r d i n a t e systems of the layout and of the X - Y - t a b l e are associated. The fault path is traced in the logic plan at the workstation, and ITP are defined. For d e t e r m i n i n g the actual internal data the ITP coordinates are e x t r a c t e d from the layout, t r a n s f e r e d to the AEBT, causing an a u t o m a t i c p o s i t i o n i n g of the ebeam on the ITP, and the IC-internal m e a s u r e m e n t is there done for the c h o s e n test loop. For d e t e r m i n i n g the n o m i n a l internal data the ITP are d e f i n e d in the logic simulation, the test loop is r e s i m u l a t e d and the i n t e r e s t i n g internal data are extracted. Actual and n o m i n a l data can be c o m p a r e d t o g e t h e r w i t h the external data at the I C - t e s t e r or workstation. This p r o b i n g along the fault path is c a r r i e d out till the point or reason for the malfunction is found. For u n d e r s t a n d i n g a r e s i m u l a t i o n (i.e. SPICE) at the host CAD s y s t e m m i g h t be n e c c e s s a r y for the right redesign. In the f o l l o w i n g o n l y three steps of this IC-internal logic verification are d e s c r i b e d in detail: the chip alignment, the posit i o n i n g and the c o m p a r i s o n of internal data. The chip a l i g n m e n t is p e r f o r m e d to bring the c o o r d i n a t e systems of the layout at the w o r k s t a t i o n and of the X - Y - t a b l e m o v i n g the DUT in coincidence. For this, two s i g n i f i c a n t r e f e r e n c e points are chosen in the layout and the X - Y - t a b l e is d r i v e n m e c h a n i c a l l y to the same p o i n t s . T h i s is d e m o n s t r a t e d in F i g . 6 . T h e p r o c e s s c o m p u t e r

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of the A E B T m e a s u r e s the table c o o r d i n a t e s a t t a c h e d to the coordinates. F r o m n o w on the A E B T is able to t r a n s f o r m the c o o r d i n a t e s into the n e c c e s s a r y data for the X-Y-table.

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The p o s i t i o n i n g of the e - b e a m onto the ITP of interest, n o r m a l l y a r a t h e r time c o n s u m i n g task, is n o w v e r y simple and quick. ITP are c h o s e n w i t h s u p p o r t of the layout e d i t o r being able to find cells, signal names etc. in the data base ; the c o o r d i n a t e s are transfered to A E B T and the e - b e a m is p o s i t i o n e d automatically. An i n t e r n a l bus of a m i c r o p r o c e s s o r was chosen in Fig.7. In the b e g i n n i n g of the v e r i f i c a t i o n p r o c e d u r e such buses are investigated to e n c i r c l e a faulty block of the DUT by s t u d y i n g the logic signals g o i n g into and out of blocks. This logic state m a p p i n g [i] is d o n e across the line m a r k e d in Fig.7b. The measured signals ("i" = dark, "0" = bright) of F i g . 8 b are d i r e c t l y c o m p a r a b l e with the t i m i n g d i a g r a m of Fig.8a p r e p a r e d from the logic simulation. Having l o c a l i z e d the b l o c k or cell of the m a l f u n c t i o n , ITP b e t w e e n the correct inputs and faulty outputs are chosen in the logic plan. In Fig.9 five ITP w e r e s e l e c t e d in an a r b i t e r circuitry. The designer searches the corresponding points in the layout (Fig.10), the c o o r d i n a t e s of w h i c h are used for p o s i t i o n i n g the ebeam. Fig.ll shows the m e a s u r e d w a v e f o r m s of those ITP, w h i c h are compared with the nominal signals from the logic simulation (Fig.12). U s i n g such a direct c o m p a r i s o n the f a u l t y b e h a v i o u r can be v e r y e a s i l y detected.

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4. C O N C L U S I O N The i n t e g r a t e d e l e c t r o n beam m e a s u r e m e n t system has i m p r o v e d the efficiency of IC-internal chip verification. The link to CAD and CAT makes a v a i l a b l e all data necessary, the d e f i n i t i o n of and the e - b e a m p o s i t i o n i n g onto internal test points is q u i c k , a n d the comparison of actual and nominal internal logic data simplifies the failure localization. The main r e m a i n i n g problems are the diversity of CAD systems and the g e n e r a t i o n of t e s t p r o g r a m s in general [8] and of proper test loops for the e - b e a m testing in particular. ACKNOWLEDGEMENT We w o u l d like to thank our colleaques F. F o r c i e r and K. M a r q u a r d t for their c o n t r i b u t i o n s , Mrs. B. G 6 r l i c h for typing the m a n u s c r i p t and E. Plies, E. W o l f g a n g and K. Zibert for their general support. REFERENCES

[i] [2] [3] [4] [5] [6] [7] [8]

E. Wolfgang, M i c r o e l e c t r o n i c Enqineerinq, 4 (1986) 77-106 P. Fazekas, E. Wolfgang, W. Gerling, K. Goser, IEEE C u r r i c u l u m for Test Technoloqy, (1983) 26 - 31 G. Geiger, S. G6rlich, H. Harbeck, P. Ke~ler, E. Wolfgang, K. Zibert, in: Proc. ist Int. Conf. on C o m p u t e r Technoloq¥, Systems and Application, C O M P E U R O 87 (1987) 598-603 N. Kuji, T. Tamama, M. Nagatani, IEEE, CAD-5, 313-319 (1986) B. Courtois, in: Proc. Int. Symp. on Circuits and Systems (1984) 217-220 B. Baril, in: Proc. Int. Test Conf. (1986) 182-189 P. K 6 1 1 e n s p e r g e r , A. Krupp, M. Sturm, M. Weyl, F. Widulla, E. Wolfgang, in: Proc. Int. Test Conf. (1984) 550 - 556 R. M. Clarke, Electronics Test, 8 (1986) 33-37