IEC 61131-3-based PLC Implemented by means of FPGA

Programmable Devices and Embedded Systems Proceedings of 13th Conference on Proceedings of the the 13th IFAC IFAC Conference on online at www.sciencedirect.com May 13-15, 2015. Cracow, Poland Available Programmable Programmable Devices Devices and and Embedded Embedded Systems Systems May May 13-15, 13-15, 2015. 2015. Cracow, Cracow, Poland Poland

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IFAC-PapersOnLine 48-4 (2015) 374–379 IEC 61131-3-based PLC Implemented by means of FPGA IEC PLC IEC 61131-3-based 61131-3-based PLC Implemented Implemented by by means means of of FPGA FPGA M. Chmiel*, R. Czerwinski **, P. Smolarek*** 

M. M. Chmiel*, Chmiel*, R. R. Czerwinski Czerwinski **, **, P. P. Smolarek*** Smolarek*** *(*)(*) Institute of Electronics, Faculty of Automatic Control, Electronics and Computer Science,  SilesianofUniversity of Technology, Akademicka Str. 16, 44-100 Gliwice, Poland *(*)(*) of Control, and *(*)(*) Institute Institute of Electronics, Electronics, Faculty Faculty of *Automatic Automatic Control, Electronics Electronics and Computer Computer Science, Science, (Tel: +48-32-237-14-95; e-mail: [email protected], **[email protected]). Silesian Silesian University University of of Technology, Technology, Akademicka Akademicka Str. Str. 16, 16, 44-100 44-100 Gliwice, Gliwice, Poland Poland (Tel: (Tel: +48-32-237-14-95; +48-32-237-14-95; e-mail: e-mail: ** [email protected], [email protected], **[email protected]). **[email protected]). Abstract: The paper discusses the design process of a programmable logic controller implemented by means of FPGA device. Designed is toprocess be compliant with EN 61131-3 standard. Different aspects by of Abstract: The paper paper discusses thePLC design of aa programmable programmable logic controller implemented Abstract: The discusses the design process of logic controller implemented by instruction list and hardware architecture designing are presented, e.g. PLC structure with particular means of of FPGA FPGA device. device. Designed Designed PLC PLC is to to be be compliant compliant with with EN EN 61131-3 61131-3 standard. standard. Different Different aspects aspects of of means emphasis central processingarchitecture unit or is memory map. are Conclusions an EN Standard are also instructiononlist list and hardware hardware designing presented,one.g. e.g. PLC61131-3 structure with particular particular instruction and architecture designing are presented, PLC structure with shown. emphasis on on central central processing processing unit unit or or memory memory map. map. Conclusions Conclusions on on an an EN EN 61131-3 61131-3 Standard Standard are are also also emphasis shown. shown. The developed PLC is implemented using FPGA device. This gives opportunity to develop interesting solutions. For example, using dual port RAM gives us opportunity develop bit/word access without The developed developed PLC is is implemented implemented using FPGA device. This gives givestoopportunity opportunity to develop develop interesting The PLC using FPGA device. This to interesting necessity of masking bits. Up to date FPGA devices have also disadvantage there are no tri-state buffers solutions. For For example, example, using using dual dual port port RAM RAM gives gives us us opportunity opportunity to to develop develop bit/word bit/word access access without without solutions. inside. This is the reason for using multiplexers that control traffic on busses. necessity of of masking masking bits. bits. Up Up to to date date FPGA FPGA devices devices have have also also disadvantage disadvantage -- there there are are no no tri-state tri-state buffers buffers necessity inside. This is the reason for using multiplexers that control traffic on busses. © 2015, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved. inside. This Control is the reason for using multiplexers that control traffic on busses. Keywords: Systems, Central Processing Unit, Programmable Logic Devices, EN 61131-3 Standard, Programmable Logic Controllers. Keywords: Control Control Systems, Systems, Central Central Processing Processing Unit, Unit, Programmable Programmable Logic Logic Devices, Devices, EN EN 61131-3 61131-3 Keywords: Standard, Programmable Programmable Logic Logic Controllers. Controllers. Standard,  architecture - the PLC is realized as micro processing unit in  1. INTRODUCTION which the -action isis realized based on the control program. architecture PLC as processing unit in architecture - the the of PLCthe is realized as micro micro processing unit in 1. INTRODUCTION Implementation PLC gives us chance to check 1. INTRODUCTION The EN 61131 is a standard for programmable controllers which the action is based on the control program. which the action is based on the control program. advantages and disadvantages the standard. Feasibility of (John and Tiegelkamp (2010)). It consists nine parts; Implementation of the the PLC PLC ofgives gives us chance chance to check check The EN is aa standard for controllers Implementation of us to The EN 61131 61131 ismost standard for programmable programmable controllers the standard collections is also possible to check however, the important for Authors research advantages and disadvantages of standard. Feasibility (John and (2010)). It nine parts; advantages andand disadvantages of the the standard.Moreover, Feasibilityit of of (John and Tiegelkamp Tiegelkamp (2010)). It consists consists nine parts; (Hrynkiewicz Chmiel (2012a) (2012b)). is investigations is third part (EN 61131-3). This part discusses the standard collections is also possible to check however, the most important for Authors research the standard collections is also possible to check however, the languages. most important for Authors research possible to embed function blocks(2012b)). like B-BAC writtenit in programming Two groups of languages are (Hrynkiewicz and Chmiel (2012a) Moreover, investigations is third (EN 61131-3). This discusses (Hrynkiewicz and Chmielinto (2012a) (2012b)). Moreover, it is is investigations islanguages third part part and (EN graphic 61131-3). This part part The discusses standard-based language PLC and increase effectiveness specified: text languages. most possible to embed function blocks like B-BAC written in programming languages. Two groups of languages are possible to embed function blocks like B-BAC written in programming languages. Twographical groups languages. of languages are of the control program (Klopot et al. (2014)). common industry and are Onmost the standard-based specified: intext textthelanguages languages graphic languages. languages. The The standard-based language language into into PLC PLC and and increase increase effectiveness effectiveness specified: and graphic most other hand, the most comfortable form of language, during of the control program (Klopot et al. (2014)). common in in the the industry industry are are graphical graphical languages. languages. On On the the of control program (Klopotofetclassical al. (2014)). Thethepaper presents concept implementation of common design of the controller and also is other hand, hand, the most most comfortable formforof of programmers, language, during during the programmable logic controller by means of FPGA logic other the comfortable form language, The paper presents concept of implementation of Instruction List (IL). Instruction list is especially helpful for The paper presents PLC concept of classical classical implementation of design of the controller and also for programmers, is devices. Presented conception is compatible withlogic EN design of the controller and also for programmers, is the programmable programmable logic logic controller controller by by means means of of FPGA FPGA testing, commissioning and improving the control programs. the logic Instruction List (IL). Instruction list is especially helpful for 61131-3 standard. "Classical software architecture" means Instruction List (IL). Instruction list is especially helpful for devices. Presented Presented PLC conception conception is compatible compatible with EN devices. PLC is with EN testing, improving the software processor. In fact, it should be stated that presented testing, commissioning commissioning and improving the control control programs. Some manufacturers and offer controllers that programs. can be 61131-3 standard. "Classical software architecture" means 61131-3 standard. "Classical software architecture" means solution is SystemInon Chip. Presented CPU presented is really programmed using languages classified underthat standard EN software processor. fact, be Some manufacturers offer controllers can be software processor. Inhowever fact, it it should should be stated stated that that presented Some manufacturers offer controllers that can be software processor; it is supported by means of 61131-3 (Siemens (2008), Boggs et al.under (2003), Rockwell solution is System on Chip. Presented CPU is programmed using languages classified standard EN solution is System- e.g. on timers Chip. and Presented CPU is really really programmed using languages classified under standard EN hardware modules counters are realized as Automation (2012)).(2008), It seems very etoften that the Rockwell hardware software processor; however it supported by of 61131-3 (Siemens Boggs (2003), software processor; however it is isparallel supported by means meanswith of 61131-3 (Siemens (2008), Boggs et al. al. with (2003), Rockwell hardware blocks and works in (concurrent) structure of the PLC is not compatible the software hardware modules e.g. timers and counters are realized as Automation (2012)). It seems very often that the hardware hardware modules e.g. timers and counters are realized as Automation (2012)). It seems very often that the hardware CPU (Chmiel and and Hrynkiewiczin(2005) (2010)). standard -ofthethemanufacturer uses the translator that enables hardware structure not with the hardware blocks blocks and works works in parallel parallel (concurrent) (concurrent) with with structure ofprocessing the PLC PLC is isprogram not compatible compatible withstandard-based the software software additional written in CPU (Chmiel and Hrynkiewicz (2005) (2010)). standard the manufacturer uses the translator that enables CPU (Chmiel and Hrynkiewicz (2005) (2010)). The paper concludes three different aspects: EN 61131-3 standard the manufacturer uses the translator that enables language toprocessing the "native"program languagewritten and then compiles it for additional in standard-based standard, of PLC andaspects: FPGAs EN resources. additional processing program written in standard-based The paperelements concludes threestructure different 61131-3 that controller language (Cenelec (2013)). Such an approach The paper concludes three different aspects: EN 61131-3 language to the "native" language and then compiles it for language to the "native" language and then compiles it for standard, elements elements of of PLC PLC structure structure and and FPGAs FPGAs resources. resources. often makes use of the PLC not optimal. As a matter of standard, that controller language (Cenelec (2013)). Such an 2. PLC STRUCTURE that controller languageresources (Cenelec are (2013)). an approach approach facts, the controller not Such aligned with the often makes use of the PLC not optimal. As a matter of often makes use of the PLC not optimal. As a matter of 2. standards. 2. PLC PLCofSTRUCTURE STRUCTURE There are many degrees freedom when starting designing facts, facts, the the controller controller resources resources are are not not aligned aligned with with the the PLC. One constraint was obvious - when EN 61131-3 standard standards. There are degrees of starting designing standards. What was the motivation for research work presented in this There are many many degrees of freedom freedom when starting designing but other must be assumed. It has been assumed that PLC. One was obvious -- EN 61131-3 standard paper? Thethe answer is quite - to built the structure PLC. One constraint constraint was obviousany EN 61131-3Because standardof-What was was motivation foreasy research workPLC presented in this this instructions are unary or without argument. What the motivation for research work presented in but other must be assumed. It has been assumed that and "the language" of which is compliant with provisions of but other must be assumed. It has been assumed paper? The is easy built the experimental andunary research character ofargument. the work, there isthat no paper? The answer answer is quite quiteFPGAs easy -- to to builtusPLC PLC the structure structure instructions are or without any Because of EN 61131-3 standard. give opportunity to instructions are unary orBasic without any argument. Because of and "the language" of which is compliant with provisions of need to built huge PLC. assumptions include: data bus and "the language" of which is compliant with provisions of experimental and and research research character character of of the the work, work, there there is is no no develop and test different solutions and built prototypes of experimental EN 61131-3 standard. FPGAs give us opportunity to is 32-bit wide, address is assumptions 8-bit wide and control busbus is EN 61131-3 standard. FPGAs give (2012), us opportunity to need to built built huge PLC. bus Basic include: data PLCs (Milik (2006), Mocha and Kania Chmiel et al. need to huge PLC. Basic assumptions include: data bus develop and test different solutions and built prototypes of 10-bit wide. develop and test different solutions and built prototypes of is 32-bit 32-bit wide, wide, address address bus bus is is 8-bit 8-bit wide wide and and control control bus bus is is (2001)). Presented design is based on classical software is PLCs PLCs (Milik (Milik (2006), (2006), Mocha Mocha and and Kania Kania (2012), (2012), Chmiel Chmiel et et al. al. 10-bit wide. 10-bit wide. (2001)). (2001)). Presented Presented design design is is based based on on classical classical software software

Copyright 374 Hosting by Elsevier Ltd. All rights reserved. 2405-8963©©IFAC 2015,2015 IFAC (International Federation of Automatic Control) Peer review under responsibility of International Federation of Automatic Control. Copyright © 374 Copyright © IFAC IFAC 2015 2015 374 10.1016/j.ifacol.2015.07.063

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. FPGA Device

Central Processing Unit CR_b1 CR_b2 CR_b3 CR_b4 CR_b5 CR_b6 CR_b7

Timer Memory Timer Controller

Bit Markers Memory Controller

CR_b0

Counter Memory Adress Bus

Data Bus

Counter Controller

Control Bus

CR_W0

Bit Logic Unit

OV CR_W1 CR_W2 CR_W3 CR_W4 CR_W5 CR_W6 CR_W7

Word Markers Memory Controller

Data Bus

PII/PIQ

8

Program and Data Memory Control Bus

Adress Bus

Data Bus

I/O Controller 16

Adress Bus

Double Word Arythmetic - Logic Unit

2

32

8

10

Signal Modules: DI, DO, AI, AO, etc.

Programmer

Fig. 1. The structure of programmable logic controller. Generalized structure of the PLC is presented in Fig. 1. The most important part of the controller is Central Processing Unit (CPU). CPU includes elements that control the work of entire controller - read and execute instructions. Moreover, CPU includes memories dedicated for markers (bit memory markers and double word memory markers) with marker controllers. Central processing unit is divided into two main parts: bit logic unit and double word arithmetic-logic unit. Those parts operate on stacks of Current Result (CR) registers. There is also flag OV inside CPU. The purpose of two separate data processing units is to accelerate execution of simple operations on binary variables.

Control bus includes signals for communication the CPU with internal modules like counters (Fig. 3: CU - Count Up, CD - Count Down, SC - Set Counter, R - Reset), timers (Fig. 3: TOF - Timer OFF, TP - Timer Pulse, TON - Timer ON) or I/O controller. A control bus includes also signals for reading data from modules into CPU (RD) and for writing data into modules from CPU (WR). End of control loop is signaled by means of END bit in control bus. 9 END

Counters and timers are realized as hardware modules that support operation of central processing unit. Counters and timers are based on the 30-bit wide data. The timer resolution is equal to 1ms.

END TIME

WR

RD

TON

TP

TOF

R

SC

CD

CU

Fig. 3. The structure of control bus. 3. MEMORY MAP

From the point of view of "outside", the most important is possibility to connect inputs and outputs. Necessity of operating on different standards (24VDC, 120VAC, 10V for analogue I/O) forced the necessity of connecting signal modules outside the FPGA. The I/O Controller that is part of PLC implemented inside FPGA is responsible for communication with signal modules. Input and output image memories are parts of the I/O controller. The imaging is synchronized with the program cycle. Inputs and outputs are read/written from/to image memories in the control program. Cyclic program processing scheme is presented in Fig. 2. Control loop

0

One of the most important features of PLCs is memory. It is hard to imagine control program that uses no data memory in real industrial solutions. Second kind of memory is program memory. The structure of first one is the most interesting for programmers and it should be carefully constructed in the PLC. Data in PLCs have different formats. First of all, bit variables are used for bit calculations. However, it is necessary to use "wider" data for calculations based on the byte, word, double word or float variables. It would be good if using one memory contents different data format would be accessible. For example bit M0.0 should be a part of M0 double word marker. Programmers should have access to bit and to entire double word. PLC vendors commonly offer this possibility; however, accessibility to bit is sometimes done by masking operations - explicitly or implicitly, that is done

I/O Imaging

Fig. 2. Cyclic program processing scheme. 375

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by the software after program compilation. There are microprocessors, like ARM Cortex-M3, which has immediate access to bits and double words thanks to the bitband alias (ARM (2008)).

intended as bit/double word designator (as presented in example in Fig. 5). It is possible to address 128 bits and 128 double words. Those 128 bits are parts of double words thanks to real dual-port RAM. One double word of input image memory is bit accessible, one double word of output image memory and two double words as markers memory. However, the memory map is designed for research purpose. There is nothing to prevent to extend address bus and as the effect the memory map too.

Presented in this paper PLC is implemented by means of programmable logic. Up to date programmable logic devices has built-in memories called block RAM (Xilinx (2011)). These memories can be flexibly configured. The most interesting for designed PLC is configuration as true dualport RAM. The true dual-port RAM consists of two completely independent access ports, A and B - Fig. 4a. The structure is fully symmetrical. Both ports are interchangeable: each port has its own data in, data out, address and other control inputs. Ports used in true dual-port mode can be arrange for different combinations, e.g. Port A can be arrange to access 18kb memory as 16Kx1bit and Port B can be arrange to access the same memory array as 512x32bits. It should be noticed that the accessibility is immediate and is not done by aliasing, masking operations, etc.

DI1 DI0

PORT A

4. CONTROL UNIT The programmable logic controller CPU is designed to execute the appropriate instructions, specified by the programmer. Instruction list of presented CPU was designed based on the EN 61131-3 standard, especially based on text language - Instruction List (IL). Instruction list of designed unit consists of operations: copy bit/double word data, bitwise operations for bit/double word data, arithmetic, rotation and move for double word data, trigger detection, jumps, counters and timers service. Complete Instruction List can be found in (Chmiel et al. (2013)).

DUAL-PORT RAM m

As it was already stated, instructions in IL are unary or without any argument. The first part of the instruction is opcode. In this project the CPU executes instruction set consisting of 120 types of commands, which makes the operation code is 7-bit wide. The second part of command is operand, which may be data or constant. The standard does not specify the size of the operands, and actually says it can be anything. As the most common data in industry are stored on 16-bits (Integer) or 32-bits (Real), it was decided to use 32-bit wide data. The combined operation code and operand results in a memory cell of a 39-bits width.

PORT A

PORT B

MEMORY ARRAY

CTRL A

n

n

PORT B

CTRL B

One-operand CPU requires extra special register called in the standard CR (Current Result) (Cenelec (2013), John and Tiegelkamp (2010)). Each operation uses the contents of the register, and the result is written back to CR. As the programmable controllers perform operations on numeric variables and single bits, the unit is equipped with two types of CR: CR_W0 (32 bits) for numeric operations and CR_b0 (1 bit) for bit operations. Moreover, to use "bracket operations" it was necessary to built-in stacks of CRs (by means of LIFO - Last In Firs Out data structure).

b) ... MW 3

MW 3

MW 2

MW 2

MW 1 MW 0 31

0

Addr 1000_0001 Addr 0000_0001

Fig. 5. Example of bit/byte addressing scheme.

Possibilities of block RAM are used in presented PLC. For example there are two double word memory markers that have bit accessibility as bit markers (Fig. 4b). These two double word memory markers can be also accessed as classical two double word memory markers. a) m

7

0

The structure of the CPU is presented in Fig. 6. The most important parts of the CPU are:

Fig. 4. a) Model of dual-port RAM, b) Fragment of markers memory organization.

a)

Input and output image memories can be also arranged as bit/double word memories. Due to 8-bit memory address in designed PLC, only 256 memory cells can be addressed. In fact, the memory space is further reduced twice. This is because one bit of address in memory map (MSB) is 376

Program Counter (PC) - is implemented as a module of 10-bit counter synchronized by main system clock, having the possibility of direct entry values (for "jump" execution);

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10

Program Counter

Program Memory

PM_ADDR

39 8

Command Counter

IC

AB

OP

32

DB

WR_CC

WR_PC

INC_PC

DMUX_CH

IC

4

CRW_CH

CR_W0

WR_W

Instruction Decoder

IN_1

Bit Logic Unit (ALU_b)

ALUW_ CR_ b0

OUT (ACCW_DATA) DATA_BIT _BUS

CR_b0

CODE

IN_2

Word Arithmetic – Logic Unit (ALU_W) DATA_BUS

Bit Stack

IN_1 CODE Double

ALUW_OV

WR_b

CRb_CH

CR_b0

OP _SIG_b

DEC_BSP

INC_BSP

WR_BS

DEC_WSP

WR_WS

INC_WSP

Word Stack

DATA_BIT _BUS

6

DB

8

CTRL_OF_BUS

Con trol Bu s

5 OP_SIG_W

IN_ 2 OUT

Fig. 6. The structure of the CPU. b) Program memory (PM) - contains a program written by the programmer; it has been placed in the structure of "Block RAM" of an FPGA; At this time of research, program is loaded during FPGA configuration process; c) Command counter (CC) - is a special block arranged for the control of time (number of system clock cycles) of particular instructions. It has direct access to the command code and the instruction decoder. Thanks to the command counter, CPU is able to carry out instructions of any duration of execution, i.e. multiplication or division instructions that take more than one system clock cycle; d) Bit-logic unit (ALU_b) - performs operations on bits. Bit-logic unit includes: a processing module, CR_b0 and 256-bit stack for bracket instructions. Specific commands for PLCs, like AND/OR/XOR/NOT, are executed; e) Arithmetic-logic unit (ALU_W) - performs operations on 32-bit variables. It includes: processing module, CR_W0 and 256-double word stack for bracket instructions. In addition, ALU generates an overflow (OV); f) Markers memory (MM) - is RAM memory, where the user can store any data: single-bit or 32-bit. It is built-in into Block RAM and its structure was described in Section III; g) Data bus (DB) - enable communication between different PLC modules. It must therefore be very 377

"flexible". There are no tri-state buffers inside contemporary FPGAs. It is impossible to create the traditional bi-directional bus. Each must contain a separate inputs and outputs in order to write and read information. This makes every module has to include 64-bit port for each module using double word data. Such a data bus was created using multiplexers and it includes: six one-bit inputs, seven 32-bit inputs, one one-bit output and 32 -bit output. Moreover, to execute instructions and to ensure flexible communication a connection between the least significant bit of 32-bit output and the one-bit input as well as between the onebit output and the least significant 32-bit input has been created. It is therefore possible to transmit one-bit data from markers memory by means of 32-bit output of markers memory. Communication, via the data bus controller, is to create a suitable channel in data bus multiplexers. This channel is determined by instruction decoder; h) Instruction decoder (ID) - decodes the code of operation and generates control signals for all modules of the PLC. It has been designed as a finite state machine implementing the four main phases of instruction cycle (Fig. 7): initialization, decoding, execution and instruction fetch for the next command. The transition to each subsequent phase occurs with the rising edge of the system clock except the state of instruction execution. Execution phase lasts specified number of

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clock cycles (see Command counter). During the initialization phase command counter is set by number of clock cycles required to implement the instruction. During decoding phase the appropriate control signals are prepared. The third phase is the execution order. In this phase the instruction decoder waits for command counter is zero. In the meantime it resets, increment or decrement signals for stacks, prepares PC and resets the control signal. The last phase of a state machine of instruction decoder is preparation for next instruction cycle, e.g. the signal that increment PC is reset. Time analysis of a state machine is shown in Fig. 8 and Fig. 9. Timing diagram presented in Fig. 7 shows the execution of the first instruction from the moment the system is

turn on. It takes three clock cycles to generate the correct result by the ALU. Time analysis presented in Fig. 8 shows the execution of the command "in the middle of the program" for which ALU generates the result in one clock cycle. CLK

3 Instruction fetch Command Counter = 0

0 Initialization

CLK

Command Counter <> 0

2 Execution

1 Decoding

CLK

Fig. 7. Internal structure of the bit logic unit.

Fig. 8. Three clock instruction realization diagram.

Fig. 9. One clock instruction realization diagram. three directions: CPU, signal modules and image memory. It realizes communication with central processing unit within the control loop (Section IV).

5. I/O CONTROLLER I/O controller forms intermediate block between central processing unit and signal modules. Due to industrial standards signals modules are done outside an FPGA. In fact, I/O controller is responsible for communications in

After the end of control loop I/O controller realizes communication with signal modules. Input data are 378

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completed and output data are transferred to the signal modules. Transmission protocol between I/O controller and signal modules in both directions is presented in Fig. 9. Transmission is based on the simple parallel protocol synchronized by means of read and write signals. I/O controller is responsible for intelligent data exchange with I/O modules because internal Data Bus is 32-bit wide but external Data bus is 16-bit wide. Furthermore, analogue 16bit data is converted to 32-bit two's complement value. WRite

REFERENCES ARM (2008). Cortex-M3, Technical Reference Manual. Boggs M. S., Fulton T. L., Hausman S., McNabb G., McNutt A., Stimmel S. W. (2003). Programmable Logic Controller – Method, System and Apparatus. US Patent No. US 6,574,743 B1. Cenelec (2013). EN 61131-3, Programmable Controller – Part 3: Programming Languages, International Standard, Management Centre, Avenue Marnix 17, B1000 Brussels. Chmiel M., Mocha J., Hrynkiewicz E., Milik A. (2001). Central Processing Units for PLC implementation in Virtex-4 FPGA, Proc. of the 18th IFAC World Congress, August 28-September 2, Milano, Italy. Chmiel M. and Hrynkiewicz E. (2005). Remarks on Parallel Bit-Byte CPU structures of Programmable Logic Controllers. In: Design of Embedded Control Systems, Section V, (ed. Adamski M. A., Karatkevich A., Węgrzyn M.), Springer, pp. 231-242. Chmiel M., Hrynkiewicz E. (2010). Concurrent Operation of the Processors in Bit-Byte CPU of a PLC, Control and Cybernetics, Vol. 39, Issue: 2, pp. 559-579. Chmiel M., Czerwiński R., Kulisz J., Malcher A., Bartkowiak T., Chodorowski P., Gandyra S., Konar B., Krzyżyk A., Lech A., Nowak E., Porębski S., Rosół M., Smolarek P. (2013), Simple Programmable Logic Controller, Technical documentation, Silesian University of Technology, Gliwice, Poland. Hrynkiewicz E., Chmiel M. (2012a). Programmable Logic Controller - Basic Structure and Idea of Programming, Electrical Review, R.88 nr 11b/2012, pp. 98-101. Hrynkiewicz E., Chmiel M. (2012b). About Programmable Logic Controller - step by step, Electrical Review, R.88 nr 9a/2012, pp. 303-307. John K.-H., Tiegelkamp M. (2010). IEC 61131-3: Programming Industrial Automation Systems. Springer. Klopot T., Laszczyk P., Stebel K., Czeczot J. (2014). Flexible function block implementation of the balance-based adaptive controller as the potential alternative for PIDbased industrial applications. Transactions of the Institute of Measurement and Control. Volume: 36. Issue: 8. Pages: 1098-1113. Milik A. (2006). High Level Synthesis – Reconfigurable Hardware Implementation of Programmable Logic Controller, PDeS’06, Brno, Czech Republic, 14-16 Feb. 2006, 138-143. Mocha J. and Kania D. (2012). Hardware Implementation of a Control Program in FPGA Structures, Electrical Review, vol. 88, no. 12/2012, 95-100 (in polish). Rockwell Automation (2012). Logix5000 Controllers IEC 61131-3 Compliance. Rockwell Automation Publication 1756-PM018C-EN-P. Siemens (2008). Simatic S7-200 Programmable Controller – System Manual. Siemens AG, Germany. Xilinx (2011). Spartan-6 FPGA Block RAM Resources, User Guide.

ADDR DATA

DATA

WR

contain those bits. It is possible thanks to dual-port block RAM of an FPGA device.

ReaD

ADDR

379

RD

Fig. 10. Transmission protocol between I/O controller and signal modules. Two problems concern I/O controller and PLC configuration. First of all, address space (8-bit external Address Bus) of signal modules is incompatible with PLC memory map. This is because a PLC memory map is designed for experiments and it will be extended in the future. The second problem is that in this configuration there is no information about module presence. I/O controller must check entire address space. Simple transmission will be replaced in the future by means of intelligent protocol of data exchange. I/O controller is based on dual-port block RAM presented in Section 3. 6. CONCLUSIONS The design process of a programmable logic controller is shown in the paper. Designed PLC is compliant with EN 61131-3 standard. The developed PLC is implemented using FPGA device in form of System on Chip. Hardware units like timers, counters and I/O controller support central processing unit for more effective work. The CPU structure consists of three main elements: memories, control units and executing units. Instructions are unary or without arguments. Central processing unit includes arithmetic-logic unit with floating point operations and bit-logic unit. It is very important that bit-logic unit executes operations within one clock cycle. Instruction decoder was designed to execute 120 commands. It is built in very "flexible" way, and it can be easily adapted to other implementation. The element most responsible for this "flexibility" is the program counter, which includes a number of system clock cycles needed to execute particular instructions. Entering new value can be easily modified the number of cycles. The longest instructions are floating point calculations as well as multiplication and division. Very important aspect for PLC work is memory map. It is designed for direct access to bits and double words that

379