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Impact of border traps in ultrathin metal-organic framework Cu3(BTC)2 based capacitors
Accepted Manuscript Impact of border traps in ultrathin metal-organic framework Cu3(BTC)2 based capacitors Liz M. Montañez, Ina Strauß, Jürgen Caro, H.Jörg Osten PII:
S1387-1811(18)30562-6
DOI:
https://doi.org/10.1016/j.micromeso.2018.10.029
Reference:
MICMAT 9167
To appear in:
Microporous and Mesoporous Materials
Received Date: 5 September 2018 Revised Date:
25 October 2018
Accepted Date: 26 October 2018
Please cite this article as: L.M. Montañez, I. Strauß, Jü. Caro, H.Jö. Osten, Impact of border traps in ultrathin metal-organic framework Cu3(BTC)2 based capacitors, Microporous and Mesoporous Materials (2018), doi: https://doi.org/10.1016/j.micromeso.2018.10.029. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
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Impact of Border Traps in Ultrathin Metal-Organic Framework Cu3(BTC)2 Based Capacitors
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Graphical abstract
Crystal structure of the Cu3(BTC)2 and density of border traps of the p-Si/Cu3(BTC)2/Al MIS capacitor device measured at different frequencies. The MOF layer was prepared with 20 spray-
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cycles.
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Impact of Border Traps in Ultrathin Metal-Organic Framework Cu3(BTC)2 Based Capacitors Liz M. Montañeza,c#, Ina Straußb,c#, Jürgen Carob,c, H. Jörg Ostena,c* a
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Institut für Materialien und Bauelemente der Elektronik, Leibniz Universität Hannover, Schneiderberg 32, D-30167 Hannover, Germany b
c
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Institut für Physikalische Chemie und Elektrochemie, Leibniz Universität Hannover, Callinstr. 3A, D-30167 Hannover, Germany
Laboratorium für Nano- und Quantenengineering, Leibniz Universität Hannover, Schneiderberg 39, D-30167 Hannover, Germany
#
Both authors contributed equally to this paper
E-mail: [email protected]
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ABSTRACT
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metal-organic frameworks
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KEYWORDS: border traps, Cu3(BTC)2, spray-coating, metal-insulator-semiconductor capacitor,
The synthesis of metal-organic frameworks (MOFs) as thin films allows their integration into different electronic devices. Particularly, their application in metal-insulating-semiconductor (MIS) capacitors provides a comprehensive study of the electrical transport mechanism and, therefore, of the effect of border traps. A low concentration of border traps guarantees a good performance of MIS capacitors. This paper is focused on the investigation of the charge components within the MOF and near the MOF/substrate interface in ultrathin Cu3(BTC)2 films
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grown directly on silicon wafers by an innovative spray-coating method. The layer thickness was easily handled by varying the number of spray cycles in the deposition process. The crystal structure and morphology of the films were characterized via X-ray diffraction and Raman
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spectroscopy. Afterwards, the film thickness was determined via confocal microscopy. The electrical characterization was performed via capacitance-voltage (C-V) measurements in forward and reverse direction at room temperature and at different frequencies. Our results
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provide evidence of the existence of positive fixed charges in the Cu3(BTC)2 dielectric layer as
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well as of the presence of border traps which causes hysteresis in the C-V response.
1. INTRODUCTION
Electrical charges in oxides may influence the condition of an underlying silicon surface and,
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thus the performance of electronic devices. For example, significant positive charge in an overlying dielectric layer may attract electrons to the semiconductor/insulator interface leading to variations in the formation of conducting channels. Si/SiO2 systems feature different defects
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such as trivalent silicon center in the SiO2 (E' center) and at the SiO2/Si interface (Pb center) [1]. These defects are responsible for the generation of interfacial charges in thermally oxidized
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silicon namely interface trapped charges, border trapped charges, and fixed oxide charges. This work focuses on electrically active defects, which are located in the dielectric layer but close to the dielectric/semiconductor interface, so-called border traps. These near-interfacial traps have the ability to exchange charge with the silicon surface, but with large time response in comparison
to
the
interface
traps,
thus
promoting
charge
trapping
near
the
dielectric/semiconductor interface [2,3]. Charge trapping can degrade the interfacial properties;
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therefore a low amount of border traps can already be crucial for an efficient device performance. SiO2 has been widely used in microelectronics and Si-based sensors, owing to the very low surface recombination, low density of interface states, and low density of border traps
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[4,5]. As the nanoelectronics continue scaling, back-end-of-line interconnects performance and reliability are becoming increasingly important. Dimensional scaling of the interconnect leads to increases in important basic metrics such as resistance and capacitance that can degrade the
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interconnect and overall integrated device performance [6]. To minimize these negative effects, insulating materials with increasingly lower values of dielectric constant (so-called low-K
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materials) are being explored and implemented in order to reduce interconnect resistance– capacitance delays and capacitive power dissipation. In a wide range of MIS capacitors-based sensors, border traps play a significant role in the electrical quality of the device. Border traps induce threshold voltage shifts, causing device instabilities [3]. Therefore, low amount of border
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traps and low density of interfaces states are required to guarantee high device performance [7]. In the past years, the integration of organic materials into capacitors and transistors has attracted much attention as promising dielectric layers for gas sensing application because of its flexibility inexpensive
fabrication
[8,9].
These
organics
materials
exhibit
a
reasonable
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and
interface/substrates quality and good sensing properties. In this context, the investigation of
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metal-organic frameworks, a new class of porous materials consisting of metal ions bridged with organic linkers can also be attractive.
MOFs, have received great attention for a wide range of potential application including separation, catalysis, storage and sensing [10–13]. This broad range of applications becomes possible due to the unique properties of MOFs. They provide a large surface area, as well as
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tailorable chemical features, which are tunable by the selection of the metal ions and the linker molecules, thus resulting in a great quantity of available MOF structures [10]. In recent years, much interest has been dedicated in the deposition techniques to achieve thin MOF films and
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their integration into electronic devices [14–17]. Among them, it was shown that ZIF-8, as a zeolitic imidazolate framework, is a promising candidate to substitute low dielectric materials because of its good dielectric properties [18]. The assembly of semiconducting or insulating
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MOFs in organic field effect transistors (OFET) also has been investigated. For instance, Ni3(2,3,6,7,10,11-hexaiminotriphenylene)2 possesses high charge transport properties owing to
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its full charge delocalization [19,20]. On the other hand, Cu3(BTC)2 with BTC=benzene 1,3,5tricarboxylate, also known as HKUST-1 can improve the performance of OFETs simply by modifying the dielectric layer of the device [21]. Recently, the integration of Cu3(BTC)2 in MIS capacitor structures was demonstrated. The feasibility of this application is due to the synthesis
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of high quality and uniform layers [22].
MIS capacitor structures provide further information concerning oxide charges and trap states located within the device. The present work deals with the impact of border traps in Cu3(BTC)2,
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a crystalline material composed of copper dimers and benzene-1,3,5-tricarboxylate linkers. This
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MOF possesses excellent chemical and physical properties [23]. The main properties that make Cu3(BTC)2 attractive in electronic applications are its rigid and stable structure, insulating properties, a large bandgap of 3.5 eV [24] and a low dielectric constant of 2.33 [25]. In this work, we present the fabrication of ultrathin Cu3(BTC)2 films directly prepared on Si wafers by the spray-coating method, which is a low-cost and low-time consuming deposition technique [26,27]. With our method, oriented Cu3(BTC)2 multilayers with good uniformity are available and enable their incorporation within MIS capacitors. The successful growth and quality of the
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MOF were confirmed through different analytic techniques. Afterwards, the effect of border traps in MOF layers was characterized for the first time, by measuring the capacitance curves in
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both forward and reverse directions.
2. EXPERIMENTAL
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2.1. Materials
All chemicals and solvents were purchased from Sigma Aldrich and used without further
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purification. Polished boron-doped p-type silicon (p-Si) wafers with (100)-orientation, 525 µm thickness and 0.5-0.75 Ωcm resistivity were used for device fabrication. The quality of these wafers meets the requirements for the quality-oriented semiconductor industry.
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2.2. Deposition of Cu3(BTC)2 by the spray-coating method
Exploiting the modularity associated with MOFs, we were able to grow oriented Cu3(BTC)2 multilayers on Si substrates. The precursors were prepared following the procedure developed by
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Arslan et al [26]. First, a 1 mM ethanolic solution of copper(II) acetate and a 0.2 mM ethanolic solution of BTC were prepared. The substrates were vertically fixed on a metal plate with a
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distance of 12 cm to the spray gun. The precursor solutions were sprayed on the Si substrates for 20 seconds. After each step, the substrates were sprayed with ethanol for 20 seconds. Afterwards, the samples were dried within a gaseous nitrogen flow. In general, one cycle within the spray coating process includes the deposition of the benzene-1,3,5-tricarboxylic acid linker (first step) and the metal source (second step), see Figure 1. This method allows the growth of ultrathin MOF films with a layer thickness up to ~5 nm without losing its uniformity. These
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characteristics are desirable for the integration of MOF in MIS capacitors. All Cu3(BTC)2 films were deposited at room temperature.
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2.3. Device fabrication Cu3(BTC)2 based MIS capacitors were fabricated on silicon wafers. First, aluminum was evaporated as the back electrode and annealed in forming gas in order to form a good Ohmic
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contact. Second, thin Cu3(BTC)2 films were synthesized by the spray-coating method in a layerby-layer growth mode. Different layer thicknesses were achieved by increasing the number of
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spray cycles. Finally, circular Al electrodes were deposited topside using a shadow mask. Si/SiO2/Al MIS capacitors were also fabricated in order to compare the density of border traps with the ones of Cu3(BTC)2. The layer thickness of the SiO2 was fixed to 10 nm. Additionally, one Si/SiO2/Al capacitor was annealed in forming gas in order to improve the surface properties.
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Figure 2 shows the device structure and the occupancy of the charges inside the pSi/Cu3(BTC)2/Al MIS capacitor including the border traps proposed by Fleetwood et al [28]. Fixed charges are located in the dielectric layer. These charges are fixed and could not
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communicate with the substrate. Interface traps are located at the MOF/Si interface whereas border traps are located close to, but not at the MOF/Si interface (see Figure 2). In contrast to
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fixed charges, the interface traps and border traps can be charged during the voltage sweep and therefore they can exchange charges with the silicon conduction band but with different time responses [3].
2.4. Characterization techniques X-ray diffraction measurements (XRD) of Cu3(BTC)2 were performed on a Bruker D8 Advance X-ray diffractometer with LYNXEYE detection technology. A CuKα (λ=0.154 nm) radiation was
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used and a 2θ-range from 5 ° to 20 ° was applied (step size 0.02, time per step 1395 s). The substrate was rotated with 15 RPM during the measurement. Raman spectra were collected using a Bruker Senterra Raman spectrometer, with a laser excitation wavelength of 532 nm and
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0.2 mW laser power under an Olympus LWD objective (100 x magnification) for 5 seconds with 10 times acquisition repetitions. The reference Cu3(BTC)2 powder was synthesized following the
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synthesis route of Huo et al [29] for nanoporous Cu3(BTC)2.
For the determination of the height profile and topographical imaging, a Leica DCM3D scanning
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confocal microscopy was used. At a fifty-fold magnification, a 3D-view of the surface was constructed utilizing an EPI50x 0.9 lens. Before measuring, the Cu3(BTC)2 layer was removed from a section of the substrate (scratched), to determine the difference in height between the layer and the Si substrate. The electrical measurements were performed through capacitancevoltage using an Agilent 4294A impedance analyzer. The measurements were conducted with a
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small AC signal of 25 mV and by sweeping the DC gate voltage from -4 to 2 V and back again. Frequency-dependent measurements were carried out in the frequency range 3-500 kHz under constant environment (T≈294 K and approximately 30% relative humidity). After the electrical
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measurements, transmission electron microscopy (TEM) images were obtained at an acceleration
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voltage of 200 kV using a FEI Tecnai G2 F20 TMP microscope.
3. RESULTS
This section is divided into the following parts: first, the successful incorporation of the Cu3(BTC)2 on the MIS capacitors is investigated through XRD and Raman spectroscopy. After that, the layer thickness is determined by confocal microscopy and TEM. The thickness is also
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verified by capacitance measurements (“electrical thickness”). Next, the density of border traps is calculated from the hysteresis in the C-V curve. Finally, the charge transport mechanism is
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investigated. 3.1 Crystal and morphological structure
The crystalline structure of Cu3(BTC)2 layers has been evaluated by XRD experiments (shown in
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Figure 3). For comparison, we added a diffractogram of Cu3(BTC)2 calculated for powder by Ahmed et al [30]. The patterns indicate that the Cu3(BTC)2 films exhibit a high degree of
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orientation along the (222) plane parallel to the surface. An increase in layer thickness (more than 15 cycles) induces an increase of the intensity of the (200) and (220) directions. Additionally, Raman spectra of a 20 cycle film of Cu3(BTC)2 on a glass substrate were measured (see SI, Figure S1). Compared to a Cu3(BTC)2 powder sample [31], the film shows the
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characteristic C=C symmetric stretching of the benzene ring and the out-of-plane ring (C-H) bending vibrations (740 and 826 cm-1). The peak around 500 cm-1 indicates the Cu-O stretching [32].
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In the case of samples prepared by the solvothermal method with a layer thickness in the micron
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scale, a growth step of 1.5 nm around the d111 crystal spacing was measured through atomic force microscopy [33]. In contrast, a deposition of 1.143 nm per cycle was obtained for thin layers (< 100 nm) grown by the layer-by-layer method [34]. In order to determine the thickness of the Cu3(BTC)2 layers, scanning confocal microscopy investigations were carried out. Topographical imaging of the layers was received by adding scratches to the Cu3(BTC)2 layer as can be seen in SI, Figure S2. The image shows an even film (green/yellow area) for the Cu3(BTC)2 layer with 20 cycles. Figure 4 shows the film thickness as a function of the number of spray cycles. The
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values change from approximately 5.8 nm for 5 cycles up to 24.1 nm for 20 cycles. A linear extrapolation gives a deposition of approximately 1.2 nm per cycle, which is consistent with the value reported by Kim et al [34], signifying a reduction of the growth step around the d111 crystal
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spacing for ultrathin layers.
The layer thickness of the Cu3(BTC)2 prepared with 5 spray cycles incorporated within the MIS
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capacitor was further measured by cross-section TEM (see inset Figure 4). The image shows the substrate-insulating-metal interface and reveals a uniform deposition of the MOF layer over the
obtained by confocal microscopy.
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silicon substrate. The MOF film thickness was measured around ~5.2 nm. A similar value was
3.2 C-V characteristics: Effect of charges in Cu3(BTC)2
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Forward (solid line) and reverse (dotted line) capacitance-voltage characteristics of pSi/Cu3(BTC)2/Al capacitor measured at room temperature are shown in Figure 5. Thin Cu3(BTC)2 films were grown with the following numbers of spray cycles: 5 (black), 10 (red), 15
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(blue) and 20 cycles (green). All C-V curves exhibit the typical accumulation, depletion and inversion regions, verifying the successful incorporation of the Cu3(BTC)2 as a dielectric layer
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within the MIS capacitor. The so-called flat-band voltage corresponds to the voltage, which, when applied to the gate electrode, yields a flat energy band in the semiconductor. If there is no charge present in the oxide or at the oxide-semiconductor interface, the flat-band voltage simply equals the difference between the gate metal work function and the semiconductor work function. Sophisticated measurement setups compensate that effect, therefore, the position of the flat-band voltage in the C-V curve lays at 0 V. The deviation of capacitance curve of the p-
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Si/Cu3(BTC)2/Al devices from the ideal one arises from different sources. (1) Fixed positive charges; these charges shift the C-V curves towards negative voltage. The shift of the C-V curves could be associated to the positive charges existing on the copper atoms of the framework and/or
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to remaining solvent during the deposition process [35,36]. (2) Interface traps at the Cu3(BTC)2/Si, which produce a small stretch-out around the depletion region of the capacitance curve. (3) Border traps; these traps lead to the formation of hysteresis after the forward and
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reverse sweep. The origin of border traps is attributed to defects in the dielectric layer such as oxygen vacancies in the case of inorganic materials [37]. Defects involving Cu+ ions generated
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during the deposition process could be the main source of border traps in the sprayed Cu3(BTC)2 [38]. Figure 5b shows the C-V curves measured a low frequency (3 kHz). The capacitance displays a hump in the depletion region as a response of the interface and border traps which induce an increase in capacitance, because they can follow the A-C current easily at low
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frequencies. Therefore the determination of layer thickness and the analysis of border traps should be performed at higher frequencies (in our investigations at 500 kHz).
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3.3 C-V characteristics: Effect of layer thickness The dielectric capacitance (Cd) was calculated using the McNutt' method [39]. This technique
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ignores the contribution of border traps and, therefore, yields an accurate Cd value. Figure 6 shows the capacitance curves in the McNutt' representation model showing a good linear behavior. An extrapolation to the linear regions leads to Cd values of 3.5×10-7 F/cm2 (5 cycles), 1.9×10-7 F/cm2 (10 cycles), 1,3×10-7 F/cm2 (15 cycles), and 0.9×10-7 F/cm2 (20 cycles), respectively. Assuming a dielectric constant of 2.33 [25], the electrically extracted thicknesses of the Cu3(BTC)2 were found to increase linearly with the number of spray cycles from 5.9 nm to
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22.1 nm, indicating a good control of the layer thickness. The electrically determined thickness is very close to the ones measured by confocal microscopy and TEM (see Table 1).
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3.4 C-V characteristics: Effect of border traps The total effective border trap density (Ntotal,bt) was extracted from the integration of the
expression [28]. =
1
|
−
|
(1)
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,
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capacitance curves swept in both forward (CF) and reverse (CR) directions using the following
Here, V is the applied gate voltage, q is the electron charge and A the area of the gate contact. Figure 7 depicts the Ntotal,bt determined from the C-V hysteresis measured at 500 kHz. In depletion, border traps are dominated by a sharp broad peak with a maximum value around 2.12×1011 cm-2. This value rapidly decreases once the device reaches accumulation or inversion.
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The strong contribution of Ntotal,bt in depletion can be associated with the reduction of the majority carrier at the silicon surface allowing the change of charge occupancy of the border
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traps. This effect is similar to the interface states [2]. However, the distribution of border traps influences the accumulation and inversion regions too, probably due to its large time responses.
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This behavior is evident for all our samples including also low frequency measurements (see SI, Figure S3). A comparison of the density of border traps of the Si/Cu3(BTC)2/Al capacitors with inorganic materials (Si/SiO2, Si/SiON [28], GaN/HfO2 [40] and GaN/Al2O3 [41]) is shown in Figure 8 and the values are summarized in Table 2. The Ntotal,bt of the Si/SiO2 reduces one order of magnitude after annealing treatments from 1.67×1011 cm-2 down to 2.5×1010 cm-2 (see SI, Figure 4S). In contrast, in the case of GaN/HfO2 and GaN/Al2O3, Ntotal,bt increases after annealing treatments. Note that Ntotal,bt strongly depends on device processing, type of substrate and
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annealing conditions. Therefore, a key parameter to decrease the density of border traps is the development of an innovative annealing condition since it can improve or degrade the interfacial properties of MIS devices. According to Table 2, the Si/Cu3(BTC)2 system exhibits comparable
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Ntotal,bt values with those of inorganic materials showing the potential of our MOFs in MIS devices.
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The orientation of hysteresis in the C-V curve leads to the suggestion that the injection of charges from the gate is the dominant process [42]. Thus, the activation of border traps can be explained
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in terms of through-bond tunneling and/or hopping transport. The hopping mechanism occurs through the organic linkers or inorganic metals ions [43,44]. In the case of the thinnest Cu3(BTC)2 sample (5 cycles, 5.6 nm), tunneling transport is the most probable conduction way. In contrast, for thicker layers, the hopping process is the predominant mechanism. The schematic diagram of the band structure of the p-Si/Cu3(BTC)2/Al MIS capacitor is shown in Figure 9.
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First, after applying high voltage, the charges are injected from the gate to the traps located near the Al/Cu3(BTC)2 interface (1). Afterwards, electrons are transported via hopping through empty traps located between the bulk of the MOF until they reach the border traps located close to the
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MOF/Si interface (2) [45,46].
Capacitance-voltage measurements performed at the frequency range from 500 kHz to 1 kHz show the split of the peak of border traps (see SI, Figure S5). These peaks can be connected to the signature of the border traps in forward and reverse directions which response becomes strong at low frequencies. Figure 10 shows the distribution of border traps corresponding to the 4 investigated Cu3(BTC)2 layers. It can be observed that an increase in layer thickness induces a decrease of the maximum peak of the Ntotal,bt and a shift of the curves towards smaller voltages.
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The considerable decrease of border traps may be related to the increases of the layer thickness
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and, therefore, the predominant through-bond hopping conduction approach [44,47].
4. CONCLUSIONS
To summarize, the impact of border traps in the charge transport mechanism of Cu3(BTC)2 MOF
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films has been investigated through capacitance measurements. We were able to synthesize ultrathin, oriented and uniform Cu3(BTC)2 films with controllable thicknesses. From capacitance
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curves, we inferred the presence of fixed positive charges in the MOF layer. Furthermore, the formation of hysteresis in the bidirectional capacitance measurements suggests the existence of border traps and, therefore, the charge transport occurs in two sequential steps. First, injection of electrons from the gate to the traps close to the Al/Cu3(BTC)2 interface and then transport
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towards the border traps located close to the Cu3(BTC)2/Si interface via tunneling or/and hopping. Low border trap density values between 2.2×1011-9.4×1011 cm-2eV-1 were extracted from the hysteretic behavior, signifying low electron trapping process. The successful growth of
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ultrathin Cu3(BTC)2 films and their relatively low concentration of border traps recommend the use of this MOF as a dielectric layer in capacitor-based sensors. Density of border traps could be
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most-likely further reduced by an innovative annealing procedure.
ACKNOWLEDGMENT
This research work was supported by the Hannover School of Nanotechnology (HSN). TEM measurements were performed by Philipp Gribisch at the Laboratorium für Nano- und Quantenengineering.
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Figure captions Figure 1. Schematic representation of the crystal structure of Cu3(BTC)2 built on Si substrate,
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showing the deposition steps of one spray cycle. Figure 2. Device structure of the p-Si/Cu3(BTC)2/Al MIS capacitor showing the location of the different charges which can be present in the device.
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Figure 3. XRD patterns of Cu3(BTC)2 layers with 5, 10, 15 and 20 spray cycles compared to
orientation along the (222) direction.
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calculated Cu3(BTC)2 powder pattern (bars) [30]. The synthesized films show a preferred
Figure 4. High profile changes of Cu3(BTC)2 films depending on the number of spray cycles as determined by scanning confocal microscopy. The inset shows a cross-section TEM image of the
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p-Si/Cu3(BTC)2/Al MIS capacitor prepared with 5 spray cycles.
Figure 5. Capacitance-voltage characteristics of the p-Si/Cu3(BTC)2/Al MIS capacitor measured at 500 kHz (a) and 3 kHz (b). All the measurements were swept first from accumulation to
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inversion (solid line) and then from inversion to accumulation (dotted line). The samples were
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deposited with different numbers of spray cycles (#C). Figure 6. Capacitance curve in the McNutt' representation model showing a good linear behavior.
Figure 7. Total border trap density and capacitance-voltage curve as a function of the applied gate voltage of the p-Si/Cu3(BTC)2/Al MIS capacitor. The MOF layer was prepared with 15 spray cycles. The shadowed region represents the strongest contribution of border traps.
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Figure 8. Total border trap density determined at the maximum peak in depletion of the pSi/Cu3(BTC)2/Al in comparison to other dielectrics of various thicknesses. None-annealed (NA)
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and annealed (A) samples Figure 9. Schematic energy band diagram of the p-Si/Cu3(BTC)2/Al MIS capacitor under a large negative voltage (strong accumulation). The diagram shows the injection (1) and the hopping (2)
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processes.
Figure 10. Total border trap density as a function of the applied gate voltage of the p-
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Si/Cu3(BTC)2/Al MIS capacitor measured at 500 kHz (a) and at 3 kHz (b).
Table 1. Layer thickness of the samples determined by confocal microscopy (dCM) and from the electrical measurements (dEM). In addition, the table summarizes the dielectric capacitance at
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which the electrically thicknesses were calculated.
Table 2. Border trap densities of Cu3(BTC)2 compared with those of inorganic materials. The table also summarizes the type of substrate, type of annealing treatment (A) and layer thickness
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of the different materials. NA (none-annealed samples).
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Figures
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Figure 1. Schematic representation of the crystal structure of Cu3(BTC)2 built on Si substrate, showing the deposition steps of one spray cycle.
Figure 2. Device structure of the p-Si/Cu3(BTC)2/Al MIS capacitor showing the location of the different charges which can be present in the device.
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Cu3(BTC)2 (222) (022)
#C: 20
Intensity (a.u.)
(002)
#C: 15
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#C: 10
#C: 5
6
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10
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14
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Figure 3. XRD patterns of Cu3(BTC)2 layers with 5, 10, 15 and 20 spray cycles compared to calculated Cu3(BTC)2 powder pattern (bars) [30]. The synthesized films show a preferred orientation along the (222) direction.
Figure 4. High profile changes of Cu3(BTC)2 films depending on the number of spray cycles as determined by scanning confocal microscopy. The inset shows a cross-section TEM image of the pSi/Cu3(BTC)2/Al MIS capacitor prepared with 5 spray cycles.
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3,5
f = 500kHz p-Si/Cu3(BTC)2/Al
Cc × 10 (F/cm )
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(a) #C: 5
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Figure 5. Capacitance-voltage characteristics of the p-Si/Cu3(BTC)2/Al MIS capacitor measured at 500 kHz (a) and 3 kHz (b). All the measurements were swept first from accumulation to inversion (solid line) and then from inversion to accumulation (dotted line).
Cc × 10-7(F/cm2)
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#C:5
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#C:10
1.5
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sqrt|dC/dV|×103((F/Vcm 2)1/2)
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Figure 6. Capacitance curve in the McNutt' representation model showing a good linear behavior.
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12 1011 f = 500kHz
∆ Nbt (cm-2V-1)
10
8
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109 -3
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Figure 7. Total border trap density and capacitance-voltage curve as a function of the applied gate voltage of the p-Si/Cu3(BTC)2/Al MIS capacitor. The MOF layer was prepared with 15 spray cycles. The shadowed region represents the strongest contribution of border traps.
this work this work Fleetwood et al [28] Jia et al [41] Winzer et al [40]
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Nbt, total (1011 cm-2)
3
NA
2
NA
1
A NA NA
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A
NA
Cu3(BTC)2
SiO2
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SiON
HfO2
Al2O3
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Figure 8. Total border trap density of the p-Si/Cu3(BTC)2/Al in comparison to other dielectrics of various thicknesses. None-annealed (NA) and annealed (A) samples.
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(a)
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Figure 9. Schematic energy band diagram of the p-Si/Cu3(BTC)2/Al MIS capacitor under a large negative voltage (strong accumulation). The diagram shows the injection (1) and the hopping (2) processes.
f = 500kHz
-3
-2
-1
0
(b)
f = 3kHz -3
-2
-1
0
Voltage (V)
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Figure 10. Total border trap density as a function of the applied gate voltage of the p-Si/Cu3(BTC)2/Al MIS capacitor measured at 500 kHz (a) and at 3 kHz (b).
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#C:15 #C:20 18.5 24.1 5.8 12.6 dCM (nm) 15.9 22.1 5.9 10.5 dEM (nm) -7 -2 3.5 1.9 1.3 0.9 Cd (10 Fcm ) Table 1. Layer thickness of the samples determined by confocal microscopy (dCM) and from the electrical measurements (dEM). In addition, the table summarizes the dielectric capacitance at which the electrically thicknesses were calculated.
A
d (nm) 5.9 10.5 15.9 22.1
Nbt,total (1011cm-2) 7.99 1.63 Cu3(BTC)2 p-silicon NA 2.12 0.79 NA 1.67 10 SiO2 p-silicon H2/N2 0.25 7.0 0.17 SiON [28] p-silicon NA 9.0 1.9 NA 1.00 HfO2 [41] GaN vacuum 1.90 NA 1.20 14 Al2O3 [40] GaN O2 1.70 Table 2. Border trap densities of Cu3(BTC)2 compared with those of inorganic materials. The table also summarizes the type of substrate, type of annealing treatment (A) and layer thickness of the different materials. NA (none-annealed samples).
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Substrate
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Impact of Border Traps in Ultrathin Metal Organic Framework Cu3(BTC)2 based Capacitors Highlights
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Impact of border traps in ultrathin metal organic framework Cu3(BTC)2 is investigated.
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Crystalline Cu3(BTC)2 were synthesized directly in silicon wafers using the hand spray coating technique, a low-cost and low-time consuming synthesis method.
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Charge transport occurs in two sequential steps: injection of electrons from the gate into the MOF and then via through-bond tunneling and/or hopping transport toward the Cu3(BTC)2/Si interface.
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S1387-1811(18)30562-6
DOI:
https://doi.org/10.1016/j.micromeso.2018.10.029
Reference:
MICMAT 9167
To appear in:
Microporous and Mesoporous Materials
Received Date: 5 September 2018 Revised Date:
25 October 2018
Accepted Date: 26 October 2018
Please cite this article as: L.M. Montañez, I. Strauß, Jü. Caro, H.Jö. Osten, Impact of border traps in ultrathin metal-organic framework Cu3(BTC)2 based capacitors, Microporous and Mesoporous Materials (2018), doi: https://doi.org/10.1016/j.micromeso.2018.10.029. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
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Impact of Border Traps in Ultrathin Metal-Organic Framework Cu3(BTC)2 Based Capacitors
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Graphical abstract
Crystal structure of the Cu3(BTC)2 and density of border traps of the p-Si/Cu3(BTC)2/Al MIS capacitor device measured at different frequencies. The MOF layer was prepared with 20 spray-
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cycles.
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Impact of Border Traps in Ultrathin Metal-Organic Framework Cu3(BTC)2 Based Capacitors Liz M. Montañeza,c#, Ina Straußb,c#, Jürgen Carob,c, H. Jörg Ostena,c* a
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Institut für Materialien und Bauelemente der Elektronik, Leibniz Universität Hannover, Schneiderberg 32, D-30167 Hannover, Germany b
c
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Institut für Physikalische Chemie und Elektrochemie, Leibniz Universität Hannover, Callinstr. 3A, D-30167 Hannover, Germany
Laboratorium für Nano- und Quantenengineering, Leibniz Universität Hannover, Schneiderberg 39, D-30167 Hannover, Germany
#
Both authors contributed equally to this paper
E-mail: [email protected]
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ABSTRACT
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metal-organic frameworks
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KEYWORDS: border traps, Cu3(BTC)2, spray-coating, metal-insulator-semiconductor capacitor,
The synthesis of metal-organic frameworks (MOFs) as thin films allows their integration into different electronic devices. Particularly, their application in metal-insulating-semiconductor (MIS) capacitors provides a comprehensive study of the electrical transport mechanism and, therefore, of the effect of border traps. A low concentration of border traps guarantees a good performance of MIS capacitors. This paper is focused on the investigation of the charge components within the MOF and near the MOF/substrate interface in ultrathin Cu3(BTC)2 films
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grown directly on silicon wafers by an innovative spray-coating method. The layer thickness was easily handled by varying the number of spray cycles in the deposition process. The crystal structure and morphology of the films were characterized via X-ray diffraction and Raman
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spectroscopy. Afterwards, the film thickness was determined via confocal microscopy. The electrical characterization was performed via capacitance-voltage (C-V) measurements in forward and reverse direction at room temperature and at different frequencies. Our results
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provide evidence of the existence of positive fixed charges in the Cu3(BTC)2 dielectric layer as
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well as of the presence of border traps which causes hysteresis in the C-V response.
1. INTRODUCTION
Electrical charges in oxides may influence the condition of an underlying silicon surface and,
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thus the performance of electronic devices. For example, significant positive charge in an overlying dielectric layer may attract electrons to the semiconductor/insulator interface leading to variations in the formation of conducting channels. Si/SiO2 systems feature different defects
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such as trivalent silicon center in the SiO2 (E' center) and at the SiO2/Si interface (Pb center) [1]. These defects are responsible for the generation of interfacial charges in thermally oxidized
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silicon namely interface trapped charges, border trapped charges, and fixed oxide charges. This work focuses on electrically active defects, which are located in the dielectric layer but close to the dielectric/semiconductor interface, so-called border traps. These near-interfacial traps have the ability to exchange charge with the silicon surface, but with large time response in comparison
to
the
interface
traps,
thus
promoting
charge
trapping
near
the
dielectric/semiconductor interface [2,3]. Charge trapping can degrade the interfacial properties;
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therefore a low amount of border traps can already be crucial for an efficient device performance. SiO2 has been widely used in microelectronics and Si-based sensors, owing to the very low surface recombination, low density of interface states, and low density of border traps
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[4,5]. As the nanoelectronics continue scaling, back-end-of-line interconnects performance and reliability are becoming increasingly important. Dimensional scaling of the interconnect leads to increases in important basic metrics such as resistance and capacitance that can degrade the
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interconnect and overall integrated device performance [6]. To minimize these negative effects, insulating materials with increasingly lower values of dielectric constant (so-called low-K
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materials) are being explored and implemented in order to reduce interconnect resistance– capacitance delays and capacitive power dissipation. In a wide range of MIS capacitors-based sensors, border traps play a significant role in the electrical quality of the device. Border traps induce threshold voltage shifts, causing device instabilities [3]. Therefore, low amount of border
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traps and low density of interfaces states are required to guarantee high device performance [7]. In the past years, the integration of organic materials into capacitors and transistors has attracted much attention as promising dielectric layers for gas sensing application because of its flexibility inexpensive
fabrication
[8,9].
These
organics
materials
exhibit
a
reasonable
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and
interface/substrates quality and good sensing properties. In this context, the investigation of
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metal-organic frameworks, a new class of porous materials consisting of metal ions bridged with organic linkers can also be attractive.
MOFs, have received great attention for a wide range of potential application including separation, catalysis, storage and sensing [10–13]. This broad range of applications becomes possible due to the unique properties of MOFs. They provide a large surface area, as well as
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tailorable chemical features, which are tunable by the selection of the metal ions and the linker molecules, thus resulting in a great quantity of available MOF structures [10]. In recent years, much interest has been dedicated in the deposition techniques to achieve thin MOF films and
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their integration into electronic devices [14–17]. Among them, it was shown that ZIF-8, as a zeolitic imidazolate framework, is a promising candidate to substitute low dielectric materials because of its good dielectric properties [18]. The assembly of semiconducting or insulating
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MOFs in organic field effect transistors (OFET) also has been investigated. For instance, Ni3(2,3,6,7,10,11-hexaiminotriphenylene)2 possesses high charge transport properties owing to
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its full charge delocalization [19,20]. On the other hand, Cu3(BTC)2 with BTC=benzene 1,3,5tricarboxylate, also known as HKUST-1 can improve the performance of OFETs simply by modifying the dielectric layer of the device [21]. Recently, the integration of Cu3(BTC)2 in MIS capacitor structures was demonstrated. The feasibility of this application is due to the synthesis
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of high quality and uniform layers [22].
MIS capacitor structures provide further information concerning oxide charges and trap states located within the device. The present work deals with the impact of border traps in Cu3(BTC)2,
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a crystalline material composed of copper dimers and benzene-1,3,5-tricarboxylate linkers. This
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MOF possesses excellent chemical and physical properties [23]. The main properties that make Cu3(BTC)2 attractive in electronic applications are its rigid and stable structure, insulating properties, a large bandgap of 3.5 eV [24] and a low dielectric constant of 2.33 [25]. In this work, we present the fabrication of ultrathin Cu3(BTC)2 films directly prepared on Si wafers by the spray-coating method, which is a low-cost and low-time consuming deposition technique [26,27]. With our method, oriented Cu3(BTC)2 multilayers with good uniformity are available and enable their incorporation within MIS capacitors. The successful growth and quality of the
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MOF were confirmed through different analytic techniques. Afterwards, the effect of border traps in MOF layers was characterized for the first time, by measuring the capacitance curves in
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both forward and reverse directions.
2. EXPERIMENTAL
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2.1. Materials
All chemicals and solvents were purchased from Sigma Aldrich and used without further
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purification. Polished boron-doped p-type silicon (p-Si) wafers with (100)-orientation, 525 µm thickness and 0.5-0.75 Ωcm resistivity were used for device fabrication. The quality of these wafers meets the requirements for the quality-oriented semiconductor industry.
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2.2. Deposition of Cu3(BTC)2 by the spray-coating method
Exploiting the modularity associated with MOFs, we were able to grow oriented Cu3(BTC)2 multilayers on Si substrates. The precursors were prepared following the procedure developed by
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Arslan et al [26]. First, a 1 mM ethanolic solution of copper(II) acetate and a 0.2 mM ethanolic solution of BTC were prepared. The substrates were vertically fixed on a metal plate with a
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distance of 12 cm to the spray gun. The precursor solutions were sprayed on the Si substrates for 20 seconds. After each step, the substrates were sprayed with ethanol for 20 seconds. Afterwards, the samples were dried within a gaseous nitrogen flow. In general, one cycle within the spray coating process includes the deposition of the benzene-1,3,5-tricarboxylic acid linker (first step) and the metal source (second step), see Figure 1. This method allows the growth of ultrathin MOF films with a layer thickness up to ~5 nm without losing its uniformity. These
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characteristics are desirable for the integration of MOF in MIS capacitors. All Cu3(BTC)2 films were deposited at room temperature.
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2.3. Device fabrication Cu3(BTC)2 based MIS capacitors were fabricated on silicon wafers. First, aluminum was evaporated as the back electrode and annealed in forming gas in order to form a good Ohmic
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contact. Second, thin Cu3(BTC)2 films were synthesized by the spray-coating method in a layerby-layer growth mode. Different layer thicknesses were achieved by increasing the number of
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spray cycles. Finally, circular Al electrodes were deposited topside using a shadow mask. Si/SiO2/Al MIS capacitors were also fabricated in order to compare the density of border traps with the ones of Cu3(BTC)2. The layer thickness of the SiO2 was fixed to 10 nm. Additionally, one Si/SiO2/Al capacitor was annealed in forming gas in order to improve the surface properties.
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Figure 2 shows the device structure and the occupancy of the charges inside the pSi/Cu3(BTC)2/Al MIS capacitor including the border traps proposed by Fleetwood et al [28]. Fixed charges are located in the dielectric layer. These charges are fixed and could not
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communicate with the substrate. Interface traps are located at the MOF/Si interface whereas border traps are located close to, but not at the MOF/Si interface (see Figure 2). In contrast to
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fixed charges, the interface traps and border traps can be charged during the voltage sweep and therefore they can exchange charges with the silicon conduction band but with different time responses [3].
2.4. Characterization techniques X-ray diffraction measurements (XRD) of Cu3(BTC)2 were performed on a Bruker D8 Advance X-ray diffractometer with LYNXEYE detection technology. A CuKα (λ=0.154 nm) radiation was
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used and a 2θ-range from 5 ° to 20 ° was applied (step size 0.02, time per step 1395 s). The substrate was rotated with 15 RPM during the measurement. Raman spectra were collected using a Bruker Senterra Raman spectrometer, with a laser excitation wavelength of 532 nm and
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0.2 mW laser power under an Olympus LWD objective (100 x magnification) for 5 seconds with 10 times acquisition repetitions. The reference Cu3(BTC)2 powder was synthesized following the
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synthesis route of Huo et al [29] for nanoporous Cu3(BTC)2.
For the determination of the height profile and topographical imaging, a Leica DCM3D scanning
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confocal microscopy was used. At a fifty-fold magnification, a 3D-view of the surface was constructed utilizing an EPI50x 0.9 lens. Before measuring, the Cu3(BTC)2 layer was removed from a section of the substrate (scratched), to determine the difference in height between the layer and the Si substrate. The electrical measurements were performed through capacitancevoltage using an Agilent 4294A impedance analyzer. The measurements were conducted with a
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small AC signal of 25 mV and by sweeping the DC gate voltage from -4 to 2 V and back again. Frequency-dependent measurements were carried out in the frequency range 3-500 kHz under constant environment (T≈294 K and approximately 30% relative humidity). After the electrical
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measurements, transmission electron microscopy (TEM) images were obtained at an acceleration
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voltage of 200 kV using a FEI Tecnai G2 F20 TMP microscope.
3. RESULTS
This section is divided into the following parts: first, the successful incorporation of the Cu3(BTC)2 on the MIS capacitors is investigated through XRD and Raman spectroscopy. After that, the layer thickness is determined by confocal microscopy and TEM. The thickness is also
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verified by capacitance measurements (“electrical thickness”). Next, the density of border traps is calculated from the hysteresis in the C-V curve. Finally, the charge transport mechanism is
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investigated. 3.1 Crystal and morphological structure
The crystalline structure of Cu3(BTC)2 layers has been evaluated by XRD experiments (shown in
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Figure 3). For comparison, we added a diffractogram of Cu3(BTC)2 calculated for powder by Ahmed et al [30]. The patterns indicate that the Cu3(BTC)2 films exhibit a high degree of
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orientation along the (222) plane parallel to the surface. An increase in layer thickness (more than 15 cycles) induces an increase of the intensity of the (200) and (220) directions. Additionally, Raman spectra of a 20 cycle film of Cu3(BTC)2 on a glass substrate were measured (see SI, Figure S1). Compared to a Cu3(BTC)2 powder sample [31], the film shows the
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characteristic C=C symmetric stretching of the benzene ring and the out-of-plane ring (C-H) bending vibrations (740 and 826 cm-1). The peak around 500 cm-1 indicates the Cu-O stretching [32].
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In the case of samples prepared by the solvothermal method with a layer thickness in the micron
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scale, a growth step of 1.5 nm around the d111 crystal spacing was measured through atomic force microscopy [33]. In contrast, a deposition of 1.143 nm per cycle was obtained for thin layers (< 100 nm) grown by the layer-by-layer method [34]. In order to determine the thickness of the Cu3(BTC)2 layers, scanning confocal microscopy investigations were carried out. Topographical imaging of the layers was received by adding scratches to the Cu3(BTC)2 layer as can be seen in SI, Figure S2. The image shows an even film (green/yellow area) for the Cu3(BTC)2 layer with 20 cycles. Figure 4 shows the film thickness as a function of the number of spray cycles. The
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values change from approximately 5.8 nm for 5 cycles up to 24.1 nm for 20 cycles. A linear extrapolation gives a deposition of approximately 1.2 nm per cycle, which is consistent with the value reported by Kim et al [34], signifying a reduction of the growth step around the d111 crystal
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spacing for ultrathin layers.
The layer thickness of the Cu3(BTC)2 prepared with 5 spray cycles incorporated within the MIS
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capacitor was further measured by cross-section TEM (see inset Figure 4). The image shows the substrate-insulating-metal interface and reveals a uniform deposition of the MOF layer over the
obtained by confocal microscopy.
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silicon substrate. The MOF film thickness was measured around ~5.2 nm. A similar value was
3.2 C-V characteristics: Effect of charges in Cu3(BTC)2
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Forward (solid line) and reverse (dotted line) capacitance-voltage characteristics of pSi/Cu3(BTC)2/Al capacitor measured at room temperature are shown in Figure 5. Thin Cu3(BTC)2 films were grown with the following numbers of spray cycles: 5 (black), 10 (red), 15
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(blue) and 20 cycles (green). All C-V curves exhibit the typical accumulation, depletion and inversion regions, verifying the successful incorporation of the Cu3(BTC)2 as a dielectric layer
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within the MIS capacitor. The so-called flat-band voltage corresponds to the voltage, which, when applied to the gate electrode, yields a flat energy band in the semiconductor. If there is no charge present in the oxide or at the oxide-semiconductor interface, the flat-band voltage simply equals the difference between the gate metal work function and the semiconductor work function. Sophisticated measurement setups compensate that effect, therefore, the position of the flat-band voltage in the C-V curve lays at 0 V. The deviation of capacitance curve of the p-
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Si/Cu3(BTC)2/Al devices from the ideal one arises from different sources. (1) Fixed positive charges; these charges shift the C-V curves towards negative voltage. The shift of the C-V curves could be associated to the positive charges existing on the copper atoms of the framework and/or
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to remaining solvent during the deposition process [35,36]. (2) Interface traps at the Cu3(BTC)2/Si, which produce a small stretch-out around the depletion region of the capacitance curve. (3) Border traps; these traps lead to the formation of hysteresis after the forward and
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reverse sweep. The origin of border traps is attributed to defects in the dielectric layer such as oxygen vacancies in the case of inorganic materials [37]. Defects involving Cu+ ions generated
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during the deposition process could be the main source of border traps in the sprayed Cu3(BTC)2 [38]. Figure 5b shows the C-V curves measured a low frequency (3 kHz). The capacitance displays a hump in the depletion region as a response of the interface and border traps which induce an increase in capacitance, because they can follow the A-C current easily at low
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frequencies. Therefore the determination of layer thickness and the analysis of border traps should be performed at higher frequencies (in our investigations at 500 kHz).
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3.3 C-V characteristics: Effect of layer thickness The dielectric capacitance (Cd) was calculated using the McNutt' method [39]. This technique
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ignores the contribution of border traps and, therefore, yields an accurate Cd value. Figure 6 shows the capacitance curves in the McNutt' representation model showing a good linear behavior. An extrapolation to the linear regions leads to Cd values of 3.5×10-7 F/cm2 (5 cycles), 1.9×10-7 F/cm2 (10 cycles), 1,3×10-7 F/cm2 (15 cycles), and 0.9×10-7 F/cm2 (20 cycles), respectively. Assuming a dielectric constant of 2.33 [25], the electrically extracted thicknesses of the Cu3(BTC)2 were found to increase linearly with the number of spray cycles from 5.9 nm to
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22.1 nm, indicating a good control of the layer thickness. The electrically determined thickness is very close to the ones measured by confocal microscopy and TEM (see Table 1).
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3.4 C-V characteristics: Effect of border traps The total effective border trap density (Ntotal,bt) was extracted from the integration of the
expression [28]. =
1
|
−
|
(1)
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,
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capacitance curves swept in both forward (CF) and reverse (CR) directions using the following
Here, V is the applied gate voltage, q is the electron charge and A the area of the gate contact. Figure 7 depicts the Ntotal,bt determined from the C-V hysteresis measured at 500 kHz. In depletion, border traps are dominated by a sharp broad peak with a maximum value around 2.12×1011 cm-2. This value rapidly decreases once the device reaches accumulation or inversion.
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The strong contribution of Ntotal,bt in depletion can be associated with the reduction of the majority carrier at the silicon surface allowing the change of charge occupancy of the border
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traps. This effect is similar to the interface states [2]. However, the distribution of border traps influences the accumulation and inversion regions too, probably due to its large time responses.
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This behavior is evident for all our samples including also low frequency measurements (see SI, Figure S3). A comparison of the density of border traps of the Si/Cu3(BTC)2/Al capacitors with inorganic materials (Si/SiO2, Si/SiON [28], GaN/HfO2 [40] and GaN/Al2O3 [41]) is shown in Figure 8 and the values are summarized in Table 2. The Ntotal,bt of the Si/SiO2 reduces one order of magnitude after annealing treatments from 1.67×1011 cm-2 down to 2.5×1010 cm-2 (see SI, Figure 4S). In contrast, in the case of GaN/HfO2 and GaN/Al2O3, Ntotal,bt increases after annealing treatments. Note that Ntotal,bt strongly depends on device processing, type of substrate and
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annealing conditions. Therefore, a key parameter to decrease the density of border traps is the development of an innovative annealing condition since it can improve or degrade the interfacial properties of MIS devices. According to Table 2, the Si/Cu3(BTC)2 system exhibits comparable
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Ntotal,bt values with those of inorganic materials showing the potential of our MOFs in MIS devices.
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The orientation of hysteresis in the C-V curve leads to the suggestion that the injection of charges from the gate is the dominant process [42]. Thus, the activation of border traps can be explained
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in terms of through-bond tunneling and/or hopping transport. The hopping mechanism occurs through the organic linkers or inorganic metals ions [43,44]. In the case of the thinnest Cu3(BTC)2 sample (5 cycles, 5.6 nm), tunneling transport is the most probable conduction way. In contrast, for thicker layers, the hopping process is the predominant mechanism. The schematic diagram of the band structure of the p-Si/Cu3(BTC)2/Al MIS capacitor is shown in Figure 9.
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First, after applying high voltage, the charges are injected from the gate to the traps located near the Al/Cu3(BTC)2 interface (1). Afterwards, electrons are transported via hopping through empty traps located between the bulk of the MOF until they reach the border traps located close to the
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MOF/Si interface (2) [45,46].
Capacitance-voltage measurements performed at the frequency range from 500 kHz to 1 kHz show the split of the peak of border traps (see SI, Figure S5). These peaks can be connected to the signature of the border traps in forward and reverse directions which response becomes strong at low frequencies. Figure 10 shows the distribution of border traps corresponding to the 4 investigated Cu3(BTC)2 layers. It can be observed that an increase in layer thickness induces a decrease of the maximum peak of the Ntotal,bt and a shift of the curves towards smaller voltages.
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The considerable decrease of border traps may be related to the increases of the layer thickness
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and, therefore, the predominant through-bond hopping conduction approach [44,47].
4. CONCLUSIONS
To summarize, the impact of border traps in the charge transport mechanism of Cu3(BTC)2 MOF
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films has been investigated through capacitance measurements. We were able to synthesize ultrathin, oriented and uniform Cu3(BTC)2 films with controllable thicknesses. From capacitance
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curves, we inferred the presence of fixed positive charges in the MOF layer. Furthermore, the formation of hysteresis in the bidirectional capacitance measurements suggests the existence of border traps and, therefore, the charge transport occurs in two sequential steps. First, injection of electrons from the gate to the traps close to the Al/Cu3(BTC)2 interface and then transport
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towards the border traps located close to the Cu3(BTC)2/Si interface via tunneling or/and hopping. Low border trap density values between 2.2×1011-9.4×1011 cm-2eV-1 were extracted from the hysteretic behavior, signifying low electron trapping process. The successful growth of
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ultrathin Cu3(BTC)2 films and their relatively low concentration of border traps recommend the use of this MOF as a dielectric layer in capacitor-based sensors. Density of border traps could be
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most-likely further reduced by an innovative annealing procedure.
ACKNOWLEDGMENT
This research work was supported by the Hannover School of Nanotechnology (HSN). TEM measurements were performed by Philipp Gribisch at the Laboratorium für Nano- und Quantenengineering.
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Figure captions Figure 1. Schematic representation of the crystal structure of Cu3(BTC)2 built on Si substrate,
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showing the deposition steps of one spray cycle. Figure 2. Device structure of the p-Si/Cu3(BTC)2/Al MIS capacitor showing the location of the different charges which can be present in the device.
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Figure 3. XRD patterns of Cu3(BTC)2 layers with 5, 10, 15 and 20 spray cycles compared to
orientation along the (222) direction.
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calculated Cu3(BTC)2 powder pattern (bars) [30]. The synthesized films show a preferred
Figure 4. High profile changes of Cu3(BTC)2 films depending on the number of spray cycles as determined by scanning confocal microscopy. The inset shows a cross-section TEM image of the
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p-Si/Cu3(BTC)2/Al MIS capacitor prepared with 5 spray cycles.
Figure 5. Capacitance-voltage characteristics of the p-Si/Cu3(BTC)2/Al MIS capacitor measured at 500 kHz (a) and 3 kHz (b). All the measurements were swept first from accumulation to
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inversion (solid line) and then from inversion to accumulation (dotted line). The samples were
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deposited with different numbers of spray cycles (#C). Figure 6. Capacitance curve in the McNutt' representation model showing a good linear behavior.
Figure 7. Total border trap density and capacitance-voltage curve as a function of the applied gate voltage of the p-Si/Cu3(BTC)2/Al MIS capacitor. The MOF layer was prepared with 15 spray cycles. The shadowed region represents the strongest contribution of border traps.
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Figure 8. Total border trap density determined at the maximum peak in depletion of the pSi/Cu3(BTC)2/Al in comparison to other dielectrics of various thicknesses. None-annealed (NA)
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and annealed (A) samples Figure 9. Schematic energy band diagram of the p-Si/Cu3(BTC)2/Al MIS capacitor under a large negative voltage (strong accumulation). The diagram shows the injection (1) and the hopping (2)
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processes.
Figure 10. Total border trap density as a function of the applied gate voltage of the p-
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Si/Cu3(BTC)2/Al MIS capacitor measured at 500 kHz (a) and at 3 kHz (b).
Table 1. Layer thickness of the samples determined by confocal microscopy (dCM) and from the electrical measurements (dEM). In addition, the table summarizes the dielectric capacitance at
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which the electrically thicknesses were calculated.
Table 2. Border trap densities of Cu3(BTC)2 compared with those of inorganic materials. The table also summarizes the type of substrate, type of annealing treatment (A) and layer thickness
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of the different materials. NA (none-annealed samples).
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Figures
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Figure 1. Schematic representation of the crystal structure of Cu3(BTC)2 built on Si substrate, showing the deposition steps of one spray cycle.
Figure 2. Device structure of the p-Si/Cu3(BTC)2/Al MIS capacitor showing the location of the different charges which can be present in the device.
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Cu3(BTC)2 (222) (022)
#C: 20
Intensity (a.u.)
(002)
#C: 15
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#C: 10
#C: 5
6
8
10
12
14
18
20
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2Θ (°)
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Figure 3. XRD patterns of Cu3(BTC)2 layers with 5, 10, 15 and 20 spray cycles compared to calculated Cu3(BTC)2 powder pattern (bars) [30]. The synthesized films show a preferred orientation along the (222) direction.
Figure 4. High profile changes of Cu3(BTC)2 films depending on the number of spray cycles as determined by scanning confocal microscopy. The inset shows a cross-section TEM image of the pSi/Cu3(BTC)2/Al MIS capacitor prepared with 5 spray cycles.
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3,5
f = 500kHz p-Si/Cu3(BTC)2/Al
Cc × 10 (F/cm )
3,0
(a) #C: 5
2
2,5
-7
2,0 #C: 10
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1,5 #C: 15 1,0
#C: 20 0,5 3,5
accumulation
depletion
inversion
(b)
3,0
Cc × 10 (F/cm )
f = 3 kHz
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2
2,5
-7
2,0
1,0 0,5 -4
-3
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1,5
-2
-1
0
1
2
Voltage (V)
fit
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Figure 5. Capacitance-voltage characteristics of the p-Si/Cu3(BTC)2/Al MIS capacitor measured at 500 kHz (a) and 3 kHz (b). All the measurements were swept first from accumulation to inversion (solid line) and then from inversion to accumulation (dotted line).
Cc × 10-7(F/cm2)
3.0
#C:5
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2.5 2.0
#C:10
1.5
#C:15
1.0
#C:20 1
2
3
sqrt|dC/dV|×103((F/Vcm 2)1/2)
4
Figure 6. Capacitance curve in the McNutt' representation model showing a good linear behavior.
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12 1011 f = 500kHz
∆ Nbt (cm-2V-1)
10
8
1010
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6
Cc×10-8(F/cm-2)
#C:15
4
109 -3
-2
-1
0
Voltage (V)
2
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Figure 7. Total border trap density and capacitance-voltage curve as a function of the applied gate voltage of the p-Si/Cu3(BTC)2/Al MIS capacitor. The MOF layer was prepared with 15 spray cycles. The shadowed region represents the strongest contribution of border traps.
this work this work Fleetwood et al [28] Jia et al [41] Winzer et al [40]
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Nbt, total (1011 cm-2)
3
NA
2
NA
1
A NA NA
NA
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A
0
A
NA
Cu3(BTC)2
SiO2
NA NA
SiON
HfO2
Al2O3
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Figure 8. Total border trap density of the p-Si/Cu3(BTC)2/Al in comparison to other dielectrics of various thicknesses. None-annealed (NA) and annealed (A) samples.
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(a)
∆ Nbt (cm-2V-1)
1012
#C:5 #C:10 #C:15 #C:20
109
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1011
1010
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Figure 9. Schematic energy band diagram of the p-Si/Cu3(BTC)2/Al MIS capacitor under a large negative voltage (strong accumulation). The diagram shows the injection (1) and the hopping (2) processes.
f = 500kHz
-3
-2
-1
0
(b)
f = 3kHz -3
-2
-1
0
Voltage (V)
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Figure 10. Total border trap density as a function of the applied gate voltage of the p-Si/Cu3(BTC)2/Al MIS capacitor measured at 500 kHz (a) and at 3 kHz (b).
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#C:15 #C:20 18.5 24.1 5.8 12.6 dCM (nm) 15.9 22.1 5.9 10.5 dEM (nm) -7 -2 3.5 1.9 1.3 0.9 Cd (10 Fcm ) Table 1. Layer thickness of the samples determined by confocal microscopy (dCM) and from the electrical measurements (dEM). In addition, the table summarizes the dielectric capacitance at which the electrically thicknesses were calculated.
A
d (nm) 5.9 10.5 15.9 22.1
Nbt,total (1011cm-2) 7.99 1.63 Cu3(BTC)2 p-silicon NA 2.12 0.79 NA 1.67 10 SiO2 p-silicon H2/N2 0.25 7.0 0.17 SiON [28] p-silicon NA 9.0 1.9 NA 1.00 HfO2 [41] GaN vacuum 1.90 NA 1.20 14 Al2O3 [40] GaN O2 1.70 Table 2. Border trap densities of Cu3(BTC)2 compared with those of inorganic materials. The table also summarizes the type of substrate, type of annealing treatment (A) and layer thickness of the different materials. NA (none-annealed samples).
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Substrate
#C:10
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Samples
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Parameters
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Impact of Border Traps in Ultrathin Metal Organic Framework Cu3(BTC)2 based Capacitors Highlights
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Impact of border traps in ultrathin metal organic framework Cu3(BTC)2 is investigated.
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Crystalline Cu3(BTC)2 were synthesized directly in silicon wafers using the hand spray coating technique, a low-cost and low-time consuming synthesis method.
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Charge transport occurs in two sequential steps: injection of electrons from the gate into the MOF and then via through-bond tunneling and/or hopping transport toward the Cu3(BTC)2/Si interface.
1