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Impact of device aging in the compact electro-thermal modeling of SiC power MOSFETs
Microelectronics Reliability xxx (xxxx) xxxx
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Impact of device aging in the compact electro-thermal modeling of SiC power MOSFETs L. Ceccarelli⁎, A.S. Bahman, F. Iannuzzo Department of Energy Technology, Aalborg University, Pontoppidanstræde 111, 9220 Aalborg East, Denmark
ABSTRACT
This paper provides an insight into the impact of aging-related parameter drift in the operation of a 1.2 kV discrete SiC power MOSFET in a TO-247-4 package. First, the on-state and switching behavior of the pristine component is characterized using a physics-based, temperature-dependent PSpice model, optimized and validated with experimental data under a wide range of operational conditions. The package parasitic elements and lumped thermal network are extracted from finite element simulation of the device geometry. Subsequently, the degradation of several parameters, including threshold voltage and thermal impedance, are introduced in the model, based on the aging data reported in the literature for the same device and packaging technology. Hence, both models, with and without aging, are used to simulate and compare the thermal stress on the component during a mission profile for a traction inverter application. The simulations show a significant impact of the aged parameters on the device electrical and thermal performance for the given mission profile, leading to larger thermal stress at a chip and package level.
1. Introduction Silicon carbide (SiC) power electronic devices have introduced an attractive alternative to traditional silicon-based devices in those applications where greater efficiency, reduced volume or high power density are needed. Wide bandgap (WBG) semiconductor materials like SiC offer a number of notable physical properties for the manufacturing of power electronic switches, such as: high voltage blocking capability with low on-state losses, fast switching characteristics, high temperature operations with increased efficiency [1,2]. SiC power MOSFETs were proved to offer superior performance in comparison to Si IGBTs in many applications, including automotive and aerospace [3–5], where high efficiency and power density, as well as reliability, are most required. Although SiC MOSFETs are becoming more popular in the design of power converters, their higher cost and scarce reliability data, especially for multichip power modules, still limits their diffusion in the field. Moreover, the full potential of SiC devices is still hindered by state-of-the-art packaging materials, which can hardly withstand high temperature variations. Several studies in literature have reported instabilities and degradation mechanisms in commercial 1.2 kV SiC MOSFETs discrete components and power modules. The accelerated DC power cycling tests conducted in Refs. [6,7] show a significant drift in the device static characteristics, while in Ref. [8] the chip- and package-related aging were successfully decoupled. Among those, the most evident degradation at chip level is the gate threshold voltage VTH shift due to charge trapping in the oxide-semiconductor interface. This phenomenon has
⁎
also been studied, among others, in Ref. [9–11], using high-temperature gate bias (HTGB) stress tests, and represents a serious concern for the applications, as it affects the power losses and reduces robustness. At a package level, instead, the aging and failure mechanisms are related to bond wire and die attach fatigue [12]. Although Si and SiC devices mostly share the same packaging technology nowadays, the power cycling lifetime for SiC ones has been found to be lower than for Si [13]. This is due to the inherent difference in the thermo-mechanical properties of the materials and chip size, as demonstrated in Ref. [14], determining higher stress and strain in SiC chips. The wear-out of bond wires and die attach determines a shift in the on-state voltage Vds,ON and, at the same time, deteriorates the heat conduction properties of the package. In particular, cracks and voids in the solder induce changes in the characteristic thermal impedance, as studied in Refs. [15,16]. All these aging phenomena combined together may affect the device performance throughout its lifetime during normal operation. Poor heat conduction and higher power loss increase the thermal stress on the chip and the package, which might exceed the safe-operating area (SOA) reported by the manufacturer. This was also pointed out in Ref. [7], where a significant increase in the junction temperature swing is observed during power cycling. The scope of this paper is to simulate and compare the thermal stress (average junction temperature and temperature fluctuation) on pristine and aged device during a real mission profile, by introducing a parametric shift in its compact electro-thermal model. The use of a mission-profile-based approach can provide an insight on the device reliability that is closer to real applications [17]. The simulated
Corresponding author. E-mail address: [email protected] (L. Ceccarelli).
https://doi.org/10.1016/j.microrel.2019.06.028 Received 9 May 2019; Accepted 13 June 2019 0026-2714/ © 2019 Elsevier Ltd. All rights reserved.
Please cite this article as: L. Ceccarelli, A.S. Bahman and F. Iannuzzo, Microelectronics Reliability, https://doi.org/10.1016/j.microrel.2019.06.028
Microelectronics Reliability xxx (xxxx) xxxx
L. Ceccarelli, et al.
Parasitic Model (ANSYS Q3D)
Experimental Characterization
Parameter Shift
Compact Device Model (PSpice) Losses mapping
Mission Profile
Converter Model
V, Rg
Losses LUTs
D, fs
Esw=f(Tj,Id)
Id
Pc=f(Tj,Id)
PMOS
Zjc
Fig. 2. Extraction of package parasitic parameters in ANSYS Q3D: current density color plot.
PMOS
Tj
Zca
Ta
4 parasitic elements have been added in the model, as well as the temperature-dependency of several parameters [19]. The lumped stray impedances of the package were extracted in ANSYS Q3D, where the detailed model of the TO-247-4 package was implemented, as shown in Fig. 2. The identification of the tested device's parameters has been carried out by means of a dedicated tool, developed earlier in MATLAB [21]. The parameters have been partly extracted from the static I-V and capacitance measurements and partly from the device datasheet provided by the manufacturer. A static characterization of the device has been carried out using a B1506A Keysight curve tracer/device analyzer and TP04390A ThermoStream airflow heater. The measured and simulated static I-V curves in the 1st quadrant are reported together in Fig. 3a and b respectively at 25 °C and 150 °C. Fig. 3c and d shows instead the measured and simulated third-quadrant I-V curves at different gate voltages and
Impedence Thermal Network
Die-attach Degradation
Thermal Model (ANSYS Icepak)
Fig. 1. Flowchart of the simulation approach.
junction temperature evolution during the mission profile, processed by a cycle counting algorithm, allows quantifying the thermal stress on the device at different aging stages. This work is meant to provide a sensitivity analysis of the aging impact for a number of parameters using simulations, rather than general conclusions about the real device degradation, which is influenced by several additional factors, including manufacturing process.
Exp
2. Electro-thermal model structure A latest-generation 1 kV/35 A discrete SiC MOSFET from Wolfspeed (part number C3M0065100K) [18] was chosen as a case study to identify and validate the compact device model. The device is enclosed in the recently developed TO-247-4 package. The multi-physics simulation strategy used in this work combines the advantages of a compact device model in PSpice and a thermal network extracted from the finiteelement-method (FEM) modeling of the device geometry [19]. The proposed simulation flowchart is depicted in Fig. 1. A MATLAB/Simulink code is used to run a PSpice SiC MOSFET model and map the switching and conduction energy losses (Esw and Pc in the figure) into dedicated look-up tables (losses LUTs). An analytical converter model generates the power losses for a selected mission profile. The losses are then injected in the impedance thermal network, which allows for the calculation of the device junction temperature. The estimated temperature is fed back to the loss model to obtain accurate temperaturedependent power losses. The damage is introduced as parameter variation in the PSpice compact model and as geometry variation (solder voids) in the FEM thermal model.
(a) Sim (PSpice)
(c) Exp Sim (PSpice)
Exp
(b) Sim (PSpice)
(d) Exp Sim (PSpice)
2.1. SiC MOSFET device model identification A temperature-dependent SiC MOSFET model was implemented in PSpice. The model is the extension of an established physics-based model, first presented in Ref. [20], which includes, among other things, a detailed physical characterization of the MOS channel current in linear and saturation regions. The body diode behavior and the TO-237-
Fig. 3. Comparison of measured and simulated I-V characteristics in the 1st quadrant at 25 °C (a) and 150 °C (b) and in the 3rd quadrant at 25 °C (c) and 150 °C (d). 2
Microelectronics Reliability xxx (xxxx) xxxx
MOSH L
Gate Driver
Gate Driver
IMOSL
MOSL
CDC
Vds
VDC
Exp
Sim (PSpice)
Drain Current [A]
Drain-to-Source Voltage [V]
L. Ceccarelli, et al.
(a)
Tj=150°C Rg=20Ω
Scope
MCU
Exp
Sim (PSpice) Drain Current [A]
Drain-to-Source Voltage [V]
Vgs
(b)
Tj=150°C Rg=20Ω
Fig. 5. Comparison of measured and simulated turn-on (a) and turn-off (b) of MOSL at Vds = 500 V, Tj = 150 °C and Rg = 20 Ω.
(a) Exp
Sim ---Fitting
(b) Exp
Sim ---Fitting
Fig. 4. Schematic and picture of the setup for the switching characterization via double-pulse test (DPT).
temperatures. The simulated and measured curves show good matching, with less than 6% maximum relative error over the full operating range. A Double-Pulse test (DPT) bench has been built using a custom designed PCB for TO-247-4 package. The setup is depicted in Fig. 4. It has been possible to measure the switching characteristics of the device under test (MOSL in the figure) up to 600 VDC and rated current (35 A). The upper MOSFET in the half-bridge topology (MOSH) has been used as freewheeling path for the load current during the off state through its body diode, which also allows measuring the reverse recovery energy. Both MOSFETs have been mounted on an aluminum cooling/heating plate whose temperature can be controlled via thermo-electrical cells (TEC) and a thermocouple. The switching waveforms have been measured at junction temperatures ranging from room temperature (25 °C) up to 150 °C. A comparison of the simulated and measured switching waveforms from the DPT is provided in Fig. 5a and b, with respectively turn-on and turn-off of MOSL. The DC bus voltage is set to 500 V and the junction temperature is 150 °C, while the switched drain current is 30 A. The ringing frequency in the experimental waveforms was matched in the simulation by adding stray elements on the high and low side of the DC bus. The model can correctly predict the switching timings and both the dV/dt and dI/dt during turn-on and turn-off. Fig. 6 shows a comparison of simulated and experimental switching energy loss. A good match is found for both turn-on (Eon) and turn-off (Eoff) energy loss both for increasing drain current and junction temperature.
Fig. 6. Comparison of measured and simulated switching energy loss for MOSL vs. load current (a) and temperature (b).
2.2. Thermal impedance model The Foster-type thermal impedance model approximates the thermal response of a solid material structure with an equivalent electrical model formed by the lumped connection of RC elements [22]. A multilayer impedance network [23] has been extracted from transient FEM simulation in ANSYS Icepak. The TO-247-4 package structure and materials were accurately modeled in the simulation, including the epoxy resin encapsulating the device, with temperature-dependent material parameters. A color plot of the cross-sectional simulated temperature distribution is showed in Fig. 7, where a constant power of 20 W is applied to the MOSFET chip. Fig. 8 shows the fitting of the thermal impedance curve from junction to case Zth,jc resulting from the transient simulation. 3. Introducing parameter degradation 3.1. Threshold voltage shift According to the literature, the VTH in SiC MOSFETs can shift as much as 10% from the original value due to electro-thermal stress 3
Microelectronics Reliability xxx (xxxx) xxxx
L. Ceccarelli, et al.
Epoxy Resin Solder
Chip
Tj = 62.7°C Cu Baseplate TIM Al Hotplate TEC Al Heatsink
Fig. 11. Translation of a 30 min drive cycle into a frequency/current mission profile for 3P-VSI.
Fig. 7. Temperature contour plot in ANSYS Icepak, showing a vertical cross section coincident with the chip junction midpoint.
Foster Network R1=0.0223
R2=0.151
R3=0.399
C1=38.39
C2=0.0772
C3=0.0052
Tj
Tc
Fig. 12. SiC MOSFET junction temperature evolution during the mission profile in Fig. 11 for different aging conditions.
Fig. 8. Fitting of the simulated junction-to-case transient thermal impedance.
Table 1 Aging conditions for the MP simulation.
VTH (%) Void area (%)
Pristine
Aging 1
Aging 2
100% –
110% 20%
120% 40%
10% and 20% in VTH affects the conduction loss (a) and the switching energy loss (b) at increasing drain current. In the first case, depending on the operating junction temperature, the conduction losses increase by 3–6%, while the switching losses increase on average by 12%. Fig. 9. Comparison of simulated conduction power loss (a) and switching energy loss (b) at different levels of VTH shift.
3.2. Solder fatigue The thermo-mechanical simulation study in Ref. [24] and the test conducted in Ref. [12] show that SiC devices in both discrete packages and modules may undergo significant solder fatigue. In these devices, the crack usually initiates at the die corners, where the highest stress occur, and propagates towards the centre [25]. It is possible to calculate the thermal impedance variation using FEM simulation by introducing void areas in the solder layer [15]. In this study, a 1-μm thick void volume was included in the thermal simulation with different areas. Fig. 10 shows the impact of solder damage on the thermal impedance correspondent to 20% and 40% void area. The thermal impedance starts showing deviation at around 10 ms, after which the heat starts spreading beyond the chip through the solder layer [16]. The steady state thermal impedance in the two aging stages is found to increase by respectively 11% and 35%, which represents a major degradation in thermal performance.
Die-attach area
20% void
40% void
Fig. 10. Impact of different degrees of solder void on the junction-to-case transient thermal impedance.
4. Mission profile simulation
[6,11]. The data is obtained from devices with similar voltage rating from the same manufacturer. The VTH shift affects both conduction power losses, by increasing the on-state voltage, and switching losses, by introducing a delay in the commutation. Fig. 9 shows how a drift of
A 30-minute drive cycle for automotive (providing speed and acceleration) [26] was translated into a frequency and current mission profile (in Fig. 11) for a 30 kW 3P-VSI inverter. Subsequently, the converter model is used to transform the mission profile into the 4
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simulation of an inverter mission profile. The simulated conditions point out a non-negligible degradation in the electro-thermal behaviour of SiC MOSFETs, which leads to higher junction temperature and larger temperature swings. These conditions are well known to be harmful for the device, leading to operation outside of the SOA boundaries and accelerating its aging process or introducing new instabilities. Declaration of Competing Interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. References [1] M.N. Yoder, Wide bandgap semiconductor materials and devices, IEEE Trans. Electron Devices 43 (10) (1996) 1633–1636 Oct. [2] J.A. Cooper, M.R. Melloch, R. Singh, A. Agarwal, J.W. Palmour, Status and prospects for SiC power MOSFETs, IEEE Trans. Electron Devices 49 (4) (2002) 658–664. Apr. [3] T. Bertelshofer, R. Horff, A. Maerz, M. Bakran, A performance comparison of a 650 V Si IGBT and SiC MOSFET inverter under automotive conditions, PCIM Europe 2016; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 2016, pp. 1–8. [4] S. O’Donnell, J. Debauche, P. Wheeler, A. Castellazzi, Silicon carbide MOSFETs in more electric aircraft power converters: the performance and reliability benefits over silicon IGBTs for a specified flight mission profile, 2016 18th European Conference on Power Electronics and Applications (EPE’16 ECCE Europe), 2016, pp. 1–10. [5] S. Yin, K.J. Tseng, R. Simanjorang, Y. Liu, J. Pou, A 50-kW high-frequency and highefficiency SiC voltage source inverter for more electric aircraft, IEEE Trans. Ind. Electron. 64 (11) (2017) 9124–9134 Nov. [6] H. Luo, F. Iannuzzo, F. Blaabjerg, M. Turnaturi, and E. Mattiuzzo, “Aging precursors and degradation effects of SiC-MOSFET modules under highly accelerated power cycling conditions,” in 2017 IEEE Energy Conversion Congress and Exposition (ECCE), 2017, pp. 2506–2511. [7] H. Luo, N. Baker, F. Iannuzzo, F. Blaabjerg, Die degradation effect on aging rate in accelerated cycling tests of SiC power MOSFET modules, Microelectron. Reliab. 76–77 (2017) 415–419 Sep. [8] N. Baker, H. Luo, F. Iannuzzo, Simultaneous on-state voltage and bond-wire resistance monitoring of silicon carbide MOSFETs, Energies 10 (3) (2017) 384 Mar. [9] A.J. Lelis, R. Green, D.B. Habersat, M. El, Basic mechanisms of threshold-voltage instability and implications for reliability testing of SiC MOSFETs, IEEE Trans. Electron Devices 62 (2) (2015) 316–323 Feb. [10] J.A.O. González, O. Alatise, A Novel Non-Intrusive Technique for BTI Characterization in SiC mosfets, in IEEE Trans. Power Electron. 34 (6) (2019) 5737–5747. [11] Q. Molin, M. Kanoun, C. Raynaud, H. Morel, Measurement and analysis of SiCMOSFET threshold voltage shift, Microelectron. Reliab. 88–90 (2018) 656–660 Sep. [12] H. Luo, P.D. Reigosa, F. Iannuzzo, F. Blaabjerg, On-line solder layer degradation measurement for SiC-MOSFET modules under accelerated power cycling condition, Microelectron. Reliab. 88–90 (2018) 563–567 Sep. [13] C. Herold, M. Schaefer, F. Sauerland, T. Poller, J. Lutz, O. Schilling, Power cycling capability of modules with SiC-diodes, CIPS 2014; 8th International Conference on Integrated Power Electronics Systems, 2014, pp. 1–6. [14] B. Hu, et al., Failure and reliability analysis of a SiC power module based on stress comparison to a Si device, IEEE Trans. Device Mater. Reliab. 17 (4) (2017) 727–737 Dec. [15] D.C. Katsis, J.D. VanWyk, A finite element modeling of dynamic hot spot effects in MOSFET dies due to voiding in the solder die-attach, IEEE 34th Annual Conference on Power Electronics Specialist, 2003. PESC ’03, 2 2003, pp. 828–833. [16] S. Singh, et al., Effects of die-attach voids on the thermal impedance of power electronic packages, IEEE Trans. Compon. Packag. Manuf. Technol. 7 (10) (2017) 1608–1616 Oct. [17] A.S. Bahman, F. Iannuzzo, F. Blaabjerg, Mission-profile-based stress analysis of bond-wires in SiC power modules, Microelectron. Reliab. 64 (2016) 419–424 Sep. [18] “http://www.wolfspeed.com/power/products/sic-mosfets/c3m0065100k.” C3M006510K Datasheet. [19] L. Ceccarelli, A.S. Bahman, F. Iannuzzo, F. Blaabjerg, A fast electro-thermal cosimulation modeling approach for SiC power MOSFETs, Proceedings of the 32nd IEEE Applied Power Electronics Conference and Exposition, Tampa, USA, 2017, pp. 966–973. [20] T.R. McNutt, A.R. Hefner, H.A. Mantooth, D. Berning, S.H. Ryu, Silicon carbide power MOSFET model and parameter extraction sequence, IEEE Trans. Power Electron. 22 (2) (2007) 353–363 Mar. [21] L. Ceccarelli, F. Iannuzzo, and M. Nawaz, “PSpice modeling platform for SiC power MOSFET modules with extensive experimental validation,” in 2016 IEEE Energy Conversion Congress and Exposition (ECCE), 2016, pp. 1–8. [22] M. März, P. Nance, Thermal Modeling of Power Electronic Systems, Infineon Technol. AG Munich, 2000. [23] A.S. Bahman, K. Ma, P. Ghimire, F. Iannuzzo, F. Blaabjerg, A 3-D-Lumped Thermal
Fig. 13. Rain-flow count histogram showing the cycle occurrence vs. mean and amplitude of each cycle for a pristine device (a) and a degraded one (b).
sinusoidal PWM switching pattern for the MOSFETs. The selected switching frequency is 50 kHz. The electrical and thermal models are the same for each of the six MOSFETs making up the inverter topology. We assumed that all the switches are placed on the same heatsink. Therefore, each of the thermal networks is connected to a common point, which represents the case. The case is connected to the ambient through an additional RC thermal network, representing the heatsink. The ambient temperature is set to 50 °C. The minimum time step used in the simulation is 1 millisecond, allowing the estimation of the junction temperature evolution with high resolution, down to the fundamental frequency ripple. After the mission profile was applied to the pristine MOSFET, the aging effects were introduced simultaneously in all the switches. Therefore, the losses LUTs were re-mapped and a new thermal network was extracted for the aged device. Fig. 12 reports the simulated junction temperature during the mission profile for the pristine device and for two different aging conditions, reported in Table 1. Fig. 12 clearly shows how different stages of wear for the MOSFETs have a significant impact on the junction temperature evolution, changing both its average value and ripple amplitude. In order to better quantify the thermal stress impact due to aging, a rain-flow algorithm for cycle counting was applied to the temperature data. The histograms mapping the cycle frequency versus average cycle temperature Tm and magnitude ΔT are charted in Fig. 13 in the case of pristine device (Fig. 13a) and aging 1 (Fig. 13b). In the case of wear, the thermal stress histogram shifts towards higher mean temperatures and larger temperature swing magnitudes. Based on reliability models for soldered and wire-bonded devices, like the one in Ref. [27], ΔT and Tm are the main factors influencing the device power-cycle lifetime, meaning that heavier thermal loading accelerates degradation. 5. Conclusion This paper explores the influence of wear mechanism on the electrothermal performance of a discrete SiC MOSFET by means of an innovative compact simulation strategy. After the device and package have been properly characterized in the electrical and thermal domain with the help of experimental data and FEM simulation. Subsequently, the influence of threshold voltage shift and solder fatigue on the power loss and thermal impedance was studied and introduced in the 5
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L. Ceccarelli, et al. Network Model for Long-Term Load Profiles Analysis in High-Power IGBT Modules, in IEEE J. Emerg. and Sel. Top. Power Electron. 4 (3) (2016) 1050–1063. [24] K. Yang, X. Zhang, M. Li, M. Chen, L. Gao, Numerical simulations based thermal reliability of power device packages, 2013 14th International Conference on Electronic Packaging Technology, 2013, pp. 635–641. [25] A.S. Bahman, F. Iannuzzo, C. Uhrenfeldt, F. Blaabjerg, S. Munk-Nielsen, Modeling of short-circuit-related thermal stress in aged IGBT modules, IEEE Trans. Ind. Appl.
53 (5) (2017) 4788–4795 Sep. [26] “Worldwide harmonized light vehicles test procedure: https://en.wikipedia.org/ wiki/Worldwide_harmonized_light_vehicles_test_procedure.”. [27] R. Bayerer, T. Herrmann, T. Licht, J. Lutz, and M. Feller, “Model for Power Cycling lifetime of IGBT Modules - various factors influencing lifetime,” in 5th International Conference on Integrated Power Electronics Systems, 2008, pp. 1–6.
6
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Impact of device aging in the compact electro-thermal modeling of SiC power MOSFETs L. Ceccarelli⁎, A.S. Bahman, F. Iannuzzo Department of Energy Technology, Aalborg University, Pontoppidanstræde 111, 9220 Aalborg East, Denmark
ABSTRACT
This paper provides an insight into the impact of aging-related parameter drift in the operation of a 1.2 kV discrete SiC power MOSFET in a TO-247-4 package. First, the on-state and switching behavior of the pristine component is characterized using a physics-based, temperature-dependent PSpice model, optimized and validated with experimental data under a wide range of operational conditions. The package parasitic elements and lumped thermal network are extracted from finite element simulation of the device geometry. Subsequently, the degradation of several parameters, including threshold voltage and thermal impedance, are introduced in the model, based on the aging data reported in the literature for the same device and packaging technology. Hence, both models, with and without aging, are used to simulate and compare the thermal stress on the component during a mission profile for a traction inverter application. The simulations show a significant impact of the aged parameters on the device electrical and thermal performance for the given mission profile, leading to larger thermal stress at a chip and package level.
1. Introduction Silicon carbide (SiC) power electronic devices have introduced an attractive alternative to traditional silicon-based devices in those applications where greater efficiency, reduced volume or high power density are needed. Wide bandgap (WBG) semiconductor materials like SiC offer a number of notable physical properties for the manufacturing of power electronic switches, such as: high voltage blocking capability with low on-state losses, fast switching characteristics, high temperature operations with increased efficiency [1,2]. SiC power MOSFETs were proved to offer superior performance in comparison to Si IGBTs in many applications, including automotive and aerospace [3–5], where high efficiency and power density, as well as reliability, are most required. Although SiC MOSFETs are becoming more popular in the design of power converters, their higher cost and scarce reliability data, especially for multichip power modules, still limits their diffusion in the field. Moreover, the full potential of SiC devices is still hindered by state-of-the-art packaging materials, which can hardly withstand high temperature variations. Several studies in literature have reported instabilities and degradation mechanisms in commercial 1.2 kV SiC MOSFETs discrete components and power modules. The accelerated DC power cycling tests conducted in Refs. [6,7] show a significant drift in the device static characteristics, while in Ref. [8] the chip- and package-related aging were successfully decoupled. Among those, the most evident degradation at chip level is the gate threshold voltage VTH shift due to charge trapping in the oxide-semiconductor interface. This phenomenon has
⁎
also been studied, among others, in Ref. [9–11], using high-temperature gate bias (HTGB) stress tests, and represents a serious concern for the applications, as it affects the power losses and reduces robustness. At a package level, instead, the aging and failure mechanisms are related to bond wire and die attach fatigue [12]. Although Si and SiC devices mostly share the same packaging technology nowadays, the power cycling lifetime for SiC ones has been found to be lower than for Si [13]. This is due to the inherent difference in the thermo-mechanical properties of the materials and chip size, as demonstrated in Ref. [14], determining higher stress and strain in SiC chips. The wear-out of bond wires and die attach determines a shift in the on-state voltage Vds,ON and, at the same time, deteriorates the heat conduction properties of the package. In particular, cracks and voids in the solder induce changes in the characteristic thermal impedance, as studied in Refs. [15,16]. All these aging phenomena combined together may affect the device performance throughout its lifetime during normal operation. Poor heat conduction and higher power loss increase the thermal stress on the chip and the package, which might exceed the safe-operating area (SOA) reported by the manufacturer. This was also pointed out in Ref. [7], where a significant increase in the junction temperature swing is observed during power cycling. The scope of this paper is to simulate and compare the thermal stress (average junction temperature and temperature fluctuation) on pristine and aged device during a real mission profile, by introducing a parametric shift in its compact electro-thermal model. The use of a mission-profile-based approach can provide an insight on the device reliability that is closer to real applications [17]. The simulated
Corresponding author. E-mail address: [email protected] (L. Ceccarelli).
https://doi.org/10.1016/j.microrel.2019.06.028 Received 9 May 2019; Accepted 13 June 2019 0026-2714/ © 2019 Elsevier Ltd. All rights reserved.
Please cite this article as: L. Ceccarelli, A.S. Bahman and F. Iannuzzo, Microelectronics Reliability, https://doi.org/10.1016/j.microrel.2019.06.028
Microelectronics Reliability xxx (xxxx) xxxx
L. Ceccarelli, et al.
Parasitic Model (ANSYS Q3D)
Experimental Characterization
Parameter Shift
Compact Device Model (PSpice) Losses mapping
Mission Profile
Converter Model
V, Rg
Losses LUTs
D, fs
Esw=f(Tj,Id)
Id
Pc=f(Tj,Id)
PMOS
Zjc
Fig. 2. Extraction of package parasitic parameters in ANSYS Q3D: current density color plot.
PMOS
Tj
Zca
Ta
4 parasitic elements have been added in the model, as well as the temperature-dependency of several parameters [19]. The lumped stray impedances of the package were extracted in ANSYS Q3D, where the detailed model of the TO-247-4 package was implemented, as shown in Fig. 2. The identification of the tested device's parameters has been carried out by means of a dedicated tool, developed earlier in MATLAB [21]. The parameters have been partly extracted from the static I-V and capacitance measurements and partly from the device datasheet provided by the manufacturer. A static characterization of the device has been carried out using a B1506A Keysight curve tracer/device analyzer and TP04390A ThermoStream airflow heater. The measured and simulated static I-V curves in the 1st quadrant are reported together in Fig. 3a and b respectively at 25 °C and 150 °C. Fig. 3c and d shows instead the measured and simulated third-quadrant I-V curves at different gate voltages and
Impedence Thermal Network
Die-attach Degradation
Thermal Model (ANSYS Icepak)
Fig. 1. Flowchart of the simulation approach.
junction temperature evolution during the mission profile, processed by a cycle counting algorithm, allows quantifying the thermal stress on the device at different aging stages. This work is meant to provide a sensitivity analysis of the aging impact for a number of parameters using simulations, rather than general conclusions about the real device degradation, which is influenced by several additional factors, including manufacturing process.
Exp
2. Electro-thermal model structure A latest-generation 1 kV/35 A discrete SiC MOSFET from Wolfspeed (part number C3M0065100K) [18] was chosen as a case study to identify and validate the compact device model. The device is enclosed in the recently developed TO-247-4 package. The multi-physics simulation strategy used in this work combines the advantages of a compact device model in PSpice and a thermal network extracted from the finiteelement-method (FEM) modeling of the device geometry [19]. The proposed simulation flowchart is depicted in Fig. 1. A MATLAB/Simulink code is used to run a PSpice SiC MOSFET model and map the switching and conduction energy losses (Esw and Pc in the figure) into dedicated look-up tables (losses LUTs). An analytical converter model generates the power losses for a selected mission profile. The losses are then injected in the impedance thermal network, which allows for the calculation of the device junction temperature. The estimated temperature is fed back to the loss model to obtain accurate temperaturedependent power losses. The damage is introduced as parameter variation in the PSpice compact model and as geometry variation (solder voids) in the FEM thermal model.
(a) Sim (PSpice)
(c) Exp Sim (PSpice)
Exp
(b) Sim (PSpice)
(d) Exp Sim (PSpice)
2.1. SiC MOSFET device model identification A temperature-dependent SiC MOSFET model was implemented in PSpice. The model is the extension of an established physics-based model, first presented in Ref. [20], which includes, among other things, a detailed physical characterization of the MOS channel current in linear and saturation regions. The body diode behavior and the TO-237-
Fig. 3. Comparison of measured and simulated I-V characteristics in the 1st quadrant at 25 °C (a) and 150 °C (b) and in the 3rd quadrant at 25 °C (c) and 150 °C (d). 2
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MOSH L
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Gate Driver
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MOSL
CDC
Vds
VDC
Exp
Sim (PSpice)
Drain Current [A]
Drain-to-Source Voltage [V]
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Tj=150°C Rg=20Ω
Scope
MCU
Exp
Sim (PSpice) Drain Current [A]
Drain-to-Source Voltage [V]
Vgs
(b)
Tj=150°C Rg=20Ω
Fig. 5. Comparison of measured and simulated turn-on (a) and turn-off (b) of MOSL at Vds = 500 V, Tj = 150 °C and Rg = 20 Ω.
(a) Exp
Sim ---Fitting
(b) Exp
Sim ---Fitting
Fig. 4. Schematic and picture of the setup for the switching characterization via double-pulse test (DPT).
temperatures. The simulated and measured curves show good matching, with less than 6% maximum relative error over the full operating range. A Double-Pulse test (DPT) bench has been built using a custom designed PCB for TO-247-4 package. The setup is depicted in Fig. 4. It has been possible to measure the switching characteristics of the device under test (MOSL in the figure) up to 600 VDC and rated current (35 A). The upper MOSFET in the half-bridge topology (MOSH) has been used as freewheeling path for the load current during the off state through its body diode, which also allows measuring the reverse recovery energy. Both MOSFETs have been mounted on an aluminum cooling/heating plate whose temperature can be controlled via thermo-electrical cells (TEC) and a thermocouple. The switching waveforms have been measured at junction temperatures ranging from room temperature (25 °C) up to 150 °C. A comparison of the simulated and measured switching waveforms from the DPT is provided in Fig. 5a and b, with respectively turn-on and turn-off of MOSL. The DC bus voltage is set to 500 V and the junction temperature is 150 °C, while the switched drain current is 30 A. The ringing frequency in the experimental waveforms was matched in the simulation by adding stray elements on the high and low side of the DC bus. The model can correctly predict the switching timings and both the dV/dt and dI/dt during turn-on and turn-off. Fig. 6 shows a comparison of simulated and experimental switching energy loss. A good match is found for both turn-on (Eon) and turn-off (Eoff) energy loss both for increasing drain current and junction temperature.
Fig. 6. Comparison of measured and simulated switching energy loss for MOSL vs. load current (a) and temperature (b).
2.2. Thermal impedance model The Foster-type thermal impedance model approximates the thermal response of a solid material structure with an equivalent electrical model formed by the lumped connection of RC elements [22]. A multilayer impedance network [23] has been extracted from transient FEM simulation in ANSYS Icepak. The TO-247-4 package structure and materials were accurately modeled in the simulation, including the epoxy resin encapsulating the device, with temperature-dependent material parameters. A color plot of the cross-sectional simulated temperature distribution is showed in Fig. 7, where a constant power of 20 W is applied to the MOSFET chip. Fig. 8 shows the fitting of the thermal impedance curve from junction to case Zth,jc resulting from the transient simulation. 3. Introducing parameter degradation 3.1. Threshold voltage shift According to the literature, the VTH in SiC MOSFETs can shift as much as 10% from the original value due to electro-thermal stress 3
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Epoxy Resin Solder
Chip
Tj = 62.7°C Cu Baseplate TIM Al Hotplate TEC Al Heatsink
Fig. 11. Translation of a 30 min drive cycle into a frequency/current mission profile for 3P-VSI.
Fig. 7. Temperature contour plot in ANSYS Icepak, showing a vertical cross section coincident with the chip junction midpoint.
Foster Network R1=0.0223
R2=0.151
R3=0.399
C1=38.39
C2=0.0772
C3=0.0052
Tj
Tc
Fig. 12. SiC MOSFET junction temperature evolution during the mission profile in Fig. 11 for different aging conditions.
Fig. 8. Fitting of the simulated junction-to-case transient thermal impedance.
Table 1 Aging conditions for the MP simulation.
VTH (%) Void area (%)
Pristine
Aging 1
Aging 2
100% –
110% 20%
120% 40%
10% and 20% in VTH affects the conduction loss (a) and the switching energy loss (b) at increasing drain current. In the first case, depending on the operating junction temperature, the conduction losses increase by 3–6%, while the switching losses increase on average by 12%. Fig. 9. Comparison of simulated conduction power loss (a) and switching energy loss (b) at different levels of VTH shift.
3.2. Solder fatigue The thermo-mechanical simulation study in Ref. [24] and the test conducted in Ref. [12] show that SiC devices in both discrete packages and modules may undergo significant solder fatigue. In these devices, the crack usually initiates at the die corners, where the highest stress occur, and propagates towards the centre [25]. It is possible to calculate the thermal impedance variation using FEM simulation by introducing void areas in the solder layer [15]. In this study, a 1-μm thick void volume was included in the thermal simulation with different areas. Fig. 10 shows the impact of solder damage on the thermal impedance correspondent to 20% and 40% void area. The thermal impedance starts showing deviation at around 10 ms, after which the heat starts spreading beyond the chip through the solder layer [16]. The steady state thermal impedance in the two aging stages is found to increase by respectively 11% and 35%, which represents a major degradation in thermal performance.
Die-attach area
20% void
40% void
Fig. 10. Impact of different degrees of solder void on the junction-to-case transient thermal impedance.
4. Mission profile simulation
[6,11]. The data is obtained from devices with similar voltage rating from the same manufacturer. The VTH shift affects both conduction power losses, by increasing the on-state voltage, and switching losses, by introducing a delay in the commutation. Fig. 9 shows how a drift of
A 30-minute drive cycle for automotive (providing speed and acceleration) [26] was translated into a frequency and current mission profile (in Fig. 11) for a 30 kW 3P-VSI inverter. Subsequently, the converter model is used to transform the mission profile into the 4
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simulation of an inverter mission profile. The simulated conditions point out a non-negligible degradation in the electro-thermal behaviour of SiC MOSFETs, which leads to higher junction temperature and larger temperature swings. These conditions are well known to be harmful for the device, leading to operation outside of the SOA boundaries and accelerating its aging process or introducing new instabilities. Declaration of Competing Interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. References [1] M.N. Yoder, Wide bandgap semiconductor materials and devices, IEEE Trans. Electron Devices 43 (10) (1996) 1633–1636 Oct. [2] J.A. Cooper, M.R. Melloch, R. Singh, A. Agarwal, J.W. Palmour, Status and prospects for SiC power MOSFETs, IEEE Trans. Electron Devices 49 (4) (2002) 658–664. Apr. [3] T. Bertelshofer, R. Horff, A. Maerz, M. Bakran, A performance comparison of a 650 V Si IGBT and SiC MOSFET inverter under automotive conditions, PCIM Europe 2016; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 2016, pp. 1–8. [4] S. O’Donnell, J. Debauche, P. Wheeler, A. Castellazzi, Silicon carbide MOSFETs in more electric aircraft power converters: the performance and reliability benefits over silicon IGBTs for a specified flight mission profile, 2016 18th European Conference on Power Electronics and Applications (EPE’16 ECCE Europe), 2016, pp. 1–10. [5] S. Yin, K.J. Tseng, R. Simanjorang, Y. Liu, J. Pou, A 50-kW high-frequency and highefficiency SiC voltage source inverter for more electric aircraft, IEEE Trans. Ind. Electron. 64 (11) (2017) 9124–9134 Nov. [6] H. Luo, F. Iannuzzo, F. Blaabjerg, M. Turnaturi, and E. Mattiuzzo, “Aging precursors and degradation effects of SiC-MOSFET modules under highly accelerated power cycling conditions,” in 2017 IEEE Energy Conversion Congress and Exposition (ECCE), 2017, pp. 2506–2511. [7] H. Luo, N. Baker, F. Iannuzzo, F. Blaabjerg, Die degradation effect on aging rate in accelerated cycling tests of SiC power MOSFET modules, Microelectron. Reliab. 76–77 (2017) 415–419 Sep. [8] N. Baker, H. Luo, F. Iannuzzo, Simultaneous on-state voltage and bond-wire resistance monitoring of silicon carbide MOSFETs, Energies 10 (3) (2017) 384 Mar. [9] A.J. Lelis, R. Green, D.B. Habersat, M. El, Basic mechanisms of threshold-voltage instability and implications for reliability testing of SiC MOSFETs, IEEE Trans. Electron Devices 62 (2) (2015) 316–323 Feb. [10] J.A.O. González, O. Alatise, A Novel Non-Intrusive Technique for BTI Characterization in SiC mosfets, in IEEE Trans. Power Electron. 34 (6) (2019) 5737–5747. [11] Q. Molin, M. Kanoun, C. Raynaud, H. Morel, Measurement and analysis of SiCMOSFET threshold voltage shift, Microelectron. Reliab. 88–90 (2018) 656–660 Sep. [12] H. Luo, P.D. Reigosa, F. Iannuzzo, F. Blaabjerg, On-line solder layer degradation measurement for SiC-MOSFET modules under accelerated power cycling condition, Microelectron. Reliab. 88–90 (2018) 563–567 Sep. [13] C. Herold, M. Schaefer, F. Sauerland, T. Poller, J. Lutz, O. Schilling, Power cycling capability of modules with SiC-diodes, CIPS 2014; 8th International Conference on Integrated Power Electronics Systems, 2014, pp. 1–6. [14] B. Hu, et al., Failure and reliability analysis of a SiC power module based on stress comparison to a Si device, IEEE Trans. Device Mater. Reliab. 17 (4) (2017) 727–737 Dec. [15] D.C. Katsis, J.D. VanWyk, A finite element modeling of dynamic hot spot effects in MOSFET dies due to voiding in the solder die-attach, IEEE 34th Annual Conference on Power Electronics Specialist, 2003. PESC ’03, 2 2003, pp. 828–833. [16] S. Singh, et al., Effects of die-attach voids on the thermal impedance of power electronic packages, IEEE Trans. Compon. Packag. Manuf. Technol. 7 (10) (2017) 1608–1616 Oct. [17] A.S. Bahman, F. Iannuzzo, F. Blaabjerg, Mission-profile-based stress analysis of bond-wires in SiC power modules, Microelectron. Reliab. 64 (2016) 419–424 Sep. [18] “http://www.wolfspeed.com/power/products/sic-mosfets/c3m0065100k.” C3M006510K Datasheet. [19] L. Ceccarelli, A.S. Bahman, F. Iannuzzo, F. Blaabjerg, A fast electro-thermal cosimulation modeling approach for SiC power MOSFETs, Proceedings of the 32nd IEEE Applied Power Electronics Conference and Exposition, Tampa, USA, 2017, pp. 966–973. [20] T.R. McNutt, A.R. Hefner, H.A. Mantooth, D. Berning, S.H. Ryu, Silicon carbide power MOSFET model and parameter extraction sequence, IEEE Trans. Power Electron. 22 (2) (2007) 353–363 Mar. [21] L. Ceccarelli, F. Iannuzzo, and M. Nawaz, “PSpice modeling platform for SiC power MOSFET modules with extensive experimental validation,” in 2016 IEEE Energy Conversion Congress and Exposition (ECCE), 2016, pp. 1–8. [22] M. März, P. Nance, Thermal Modeling of Power Electronic Systems, Infineon Technol. AG Munich, 2000. [23] A.S. Bahman, K. Ma, P. Ghimire, F. Iannuzzo, F. Blaabjerg, A 3-D-Lumped Thermal
Fig. 13. Rain-flow count histogram showing the cycle occurrence vs. mean and amplitude of each cycle for a pristine device (a) and a degraded one (b).
sinusoidal PWM switching pattern for the MOSFETs. The selected switching frequency is 50 kHz. The electrical and thermal models are the same for each of the six MOSFETs making up the inverter topology. We assumed that all the switches are placed on the same heatsink. Therefore, each of the thermal networks is connected to a common point, which represents the case. The case is connected to the ambient through an additional RC thermal network, representing the heatsink. The ambient temperature is set to 50 °C. The minimum time step used in the simulation is 1 millisecond, allowing the estimation of the junction temperature evolution with high resolution, down to the fundamental frequency ripple. After the mission profile was applied to the pristine MOSFET, the aging effects were introduced simultaneously in all the switches. Therefore, the losses LUTs were re-mapped and a new thermal network was extracted for the aged device. Fig. 12 reports the simulated junction temperature during the mission profile for the pristine device and for two different aging conditions, reported in Table 1. Fig. 12 clearly shows how different stages of wear for the MOSFETs have a significant impact on the junction temperature evolution, changing both its average value and ripple amplitude. In order to better quantify the thermal stress impact due to aging, a rain-flow algorithm for cycle counting was applied to the temperature data. The histograms mapping the cycle frequency versus average cycle temperature Tm and magnitude ΔT are charted in Fig. 13 in the case of pristine device (Fig. 13a) and aging 1 (Fig. 13b). In the case of wear, the thermal stress histogram shifts towards higher mean temperatures and larger temperature swing magnitudes. Based on reliability models for soldered and wire-bonded devices, like the one in Ref. [27], ΔT and Tm are the main factors influencing the device power-cycle lifetime, meaning that heavier thermal loading accelerates degradation. 5. Conclusion This paper explores the influence of wear mechanism on the electrothermal performance of a discrete SiC MOSFET by means of an innovative compact simulation strategy. After the device and package have been properly characterized in the electrical and thermal domain with the help of experimental data and FEM simulation. Subsequently, the influence of threshold voltage shift and solder fatigue on the power loss and thermal impedance was studied and introduced in the 5
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L. Ceccarelli, et al. Network Model for Long-Term Load Profiles Analysis in High-Power IGBT Modules, in IEEE J. Emerg. and Sel. Top. Power Electron. 4 (3) (2016) 1050–1063. [24] K. Yang, X. Zhang, M. Li, M. Chen, L. Gao, Numerical simulations based thermal reliability of power device packages, 2013 14th International Conference on Electronic Packaging Technology, 2013, pp. 635–641. [25] A.S. Bahman, F. Iannuzzo, C. Uhrenfeldt, F. Blaabjerg, S. Munk-Nielsen, Modeling of short-circuit-related thermal stress in aged IGBT modules, IEEE Trans. Ind. Appl.
53 (5) (2017) 4788–4795 Sep. [26] “Worldwide harmonized light vehicles test procedure: https://en.wikipedia.org/ wiki/Worldwide_harmonized_light_vehicles_test_procedure.”. [27] R. Bayerer, T. Herrmann, T. Licht, J. Lutz, and M. Feller, “Model for Power Cycling lifetime of IGBT Modules - various factors influencing lifetime,” in 5th International Conference on Integrated Power Electronics Systems, 2008, pp. 1–6.
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