- Email: [email protected]
Implementation constraints in self-checking integrated circuits
World Abstracts continued from page 41
The effects of phosphorus diffusion cooling rate on I"L gain B. L. MORRIS Solid St. Electron. 23, 457 (1980). It has been found that the current gain of an I~L cell can be seriously degraded if the deep collector (phosphorus) diffusion is not slow cooled. A correlation between improper cooling rate and the generation of a severe edge dislocation network is established. This network is shown to result in leaky emitter-base and collector-base junctions in an FL cell but not in a conventional n-p-n transistor. These leaky junctions correlate with the observed low gain. A model is proposed to explain the cooling rate dependence of the dislocation networks in terms of vacancy clustering. Preoxidation gettering of oxidation-induced stacking faults in silicon by the phosphorus diffusion process J-H. CHEN and M-C. CHEN lnt. J. Electron. 47(6), 555 (1979). Preoxidation gettering of oxidation-induced stacking faults (OSF) in a silicon wafer by the reverse side phosphorus diffusion-induced misfit dislocations has been studied. This gettering scheme either prevents the formation of OSF during the thermal oxidation of silicon or deactivates the electrical activity of those OSF having been formed. The gettering action takes place by removing or isolating the impurities from being precipitated at the OSF nucleation sites and confines them to the misfit dislocations at the reverse side of the wafer. It is expected that the misfit dislocations continue to act as sinks of impurities during the subsequent high-temperature oxidation process and results in a great improvement of device yield and performance.
5. Testing Ultrasonic in-line inspection technique for contact materials E. JOST and G. FONTAINE IEEE Trans. Components, ttybrids Mfg Technology. CHMT-3 (l), 79 (March 1980). The quality of the bond between the contact material and the base metal carrier is becoming increasingly important as the contact size is reduced to conserve silver. Many contact materials are produced by continuous brazing techniques. With conventional methods the quality of the continuous brazed joint cannot be evaluated in sufficient detail by in-line ultrasonic scanning. A new approach is described which allows the in-line inspection of a strip at normal bonding speeds and the print-out of void and flaw characteristics of the brazed interface. Computer-aided determination of tests for the detection and Iocalisation of faults in electronic circuits and systems U. FRUHAUFand P. SLOWIG Nachrichtentechnik Elektronik30(4), 144 (1980).(In German.) Computer-aided methods are used with advantage for the fault diagnostic in electronic circuits in order to design more effective test determination to enable the introduction of objective evaluation criteria. As methods applicable for all circuit classes are too expensive, the various calculation methods are examined as to their specific possibilities and optimum fields of application. The result of these examinations is a comparative analysis being more profound than the conventional examinations. Hardening RANIs against soft errors hi. BRODSKY Electronics, 117 (April 1980). Accelerated tests pinpoint effects on alpha-induced soft errors of dynamic RAM design changes, supply voltage, and cycle time. Some facts about environmental stress screening I. QUART and D. EDGERTON, Jr.
Proc. Annual Reliability and Afaintainability Symposium, San Francisco, p.220 (22-24 January 1980). This paper describes environmental stress screening experiments performed at Hughes Aircraft Company during the past three years. The experiments performed at the module level involved large numbers of production hardware. Data is presented indicating techniques for selecting environments and optimising stress levels and duration for the screening of module level assemblies. The differences in screen results are discussed as to hardware and manufacturing processes. Also, some results tend to refute some intuitive ideas that are the rationale for some current screening practices. 42
Failure analysis on a 65K MOS RAM ~ith a new type of memor)" di_~play W. N A S S W E I T E R Fifth Solid State Circtdts Conference- ESSCIRC 79, lEE l'ubhz. 178, 113. Essential to any understanding of a semiconductor memory's failure mechanisms is a visual presentation of bits in their physical topology under varying test conditions. As part of our memory development effort we have designed a new type of Bit Map; a memory display which provides virtually a real-time presentation for interactive device characterisation. This Bit Map System forms the basis of a fast and effective failure analysis which is needed for the introduction of our new generation of 65-k bit-MOS RAM's. With it the designer identifies memory problems and relates them to specific areas or individual bits. Bit Mapping gives us a detailed analysis of electrical and logical operation by showing location and type of failure; it leads to a thorough understanding of the device down to the bit level. Implementation constraints in self-checking integrated circuits Y. C R O U Z E T and C. LANDRAULT
Fifth Solid State Circtdts Conference - ESSCIRC 79, lEE Pltbh~. 178, 58. The next few years will no doubt lead to the appearance of faulttolerant computers on the market due to several factors such as: (1) the technological evolution leading to high performance but increasingly cheaper VLSI circuits. (2) the increasing complexity of the tasks assigned to computers and, at the same time, the increasing authority of these tasks. The problems with which the designers of such fault-tolerant systems are faced must lead 1C manufacturers to introduce a new generation of circuits better adapted to the realisation of fault-tolerant systems (1, 2, 3). In this paper we do not take into account the functional constraints due to the realisation of such ICS, they are extensively dealt with in the literature (4). We only take into account the constraints linked with the implementation of such circuits. After a first paragraph of definitions, the second part of this paper is devoted to failure modelling encountered in MOS single channel ICs. This modelling enables one to divide these failures into several classes according to the type of incorrect operation that they induce. In the third part, we pinpoint the implementation constraints that follow according to the class of failures that is taken into account during the design of the fault tolerant circuit, these constraints being more or less severe according to whether we consider single, unidirectional or multiple faults. The use of an industrial x-ray source for electronic component radiation effects work L. ADAMS and I. THOMPSON IEEE Trans. Components, Hybrids Affg Technology. CHMT-3 (!), 144 (March 1980). Low energy x-ray tubes have been used as a source of ionising radiation in various past radiation effects studies. In such studies there has not been a requirement for the absolute dose to be known, and little detail has been reported regarding the tube characteristics and the type of dosimetry employed. The use of an industrial x-ray source for space environment simulation is an attractive technique in that such a source is commonly available in aerospace and semiconductor manufacturing facilities and no special licensing or safety regulations are involved. Prior to using an x-ray source for space simulation the tube characteristics must be known, a reliable technique for dosimetry must be established, and the source must be correlated with other standard space simulation sources such as the cobalt-60 gammacell. An experimental program covering the above points is described. It results in a defined procedure which can be followed by other workers interested in the use of an industrial x-ray source as a calibrated source of ionising radiation. Digital system diagnostics-design/evaluation G. A. CONLEY
Proc. Annual Reliability and Maintab~ability Symposium, San Francisco, p.38 (22-24 January 1980). This paper describes the FMEA process used on a complex digital data system. This system incorporated a central processor (general purpose computer), man/machine interface channels (magnetic tape unit and typewriter input/output), microprocessor-controlled 1/O channels, and fault detection/isolation tools in both hardware and software. The specification for the system required that 98% of all failures be
The effects of phosphorus diffusion cooling rate on I"L gain B. L. MORRIS Solid St. Electron. 23, 457 (1980). It has been found that the current gain of an I~L cell can be seriously degraded if the deep collector (phosphorus) diffusion is not slow cooled. A correlation between improper cooling rate and the generation of a severe edge dislocation network is established. This network is shown to result in leaky emitter-base and collector-base junctions in an FL cell but not in a conventional n-p-n transistor. These leaky junctions correlate with the observed low gain. A model is proposed to explain the cooling rate dependence of the dislocation networks in terms of vacancy clustering. Preoxidation gettering of oxidation-induced stacking faults in silicon by the phosphorus diffusion process J-H. CHEN and M-C. CHEN lnt. J. Electron. 47(6), 555 (1979). Preoxidation gettering of oxidation-induced stacking faults (OSF) in a silicon wafer by the reverse side phosphorus diffusion-induced misfit dislocations has been studied. This gettering scheme either prevents the formation of OSF during the thermal oxidation of silicon or deactivates the electrical activity of those OSF having been formed. The gettering action takes place by removing or isolating the impurities from being precipitated at the OSF nucleation sites and confines them to the misfit dislocations at the reverse side of the wafer. It is expected that the misfit dislocations continue to act as sinks of impurities during the subsequent high-temperature oxidation process and results in a great improvement of device yield and performance.
5. Testing Ultrasonic in-line inspection technique for contact materials E. JOST and G. FONTAINE IEEE Trans. Components, ttybrids Mfg Technology. CHMT-3 (l), 79 (March 1980). The quality of the bond between the contact material and the base metal carrier is becoming increasingly important as the contact size is reduced to conserve silver. Many contact materials are produced by continuous brazing techniques. With conventional methods the quality of the continuous brazed joint cannot be evaluated in sufficient detail by in-line ultrasonic scanning. A new approach is described which allows the in-line inspection of a strip at normal bonding speeds and the print-out of void and flaw characteristics of the brazed interface. Computer-aided determination of tests for the detection and Iocalisation of faults in electronic circuits and systems U. FRUHAUFand P. SLOWIG Nachrichtentechnik Elektronik30(4), 144 (1980).(In German.) Computer-aided methods are used with advantage for the fault diagnostic in electronic circuits in order to design more effective test determination to enable the introduction of objective evaluation criteria. As methods applicable for all circuit classes are too expensive, the various calculation methods are examined as to their specific possibilities and optimum fields of application. The result of these examinations is a comparative analysis being more profound than the conventional examinations. Hardening RANIs against soft errors hi. BRODSKY Electronics, 117 (April 1980). Accelerated tests pinpoint effects on alpha-induced soft errors of dynamic RAM design changes, supply voltage, and cycle time. Some facts about environmental stress screening I. QUART and D. EDGERTON, Jr.
Proc. Annual Reliability and Afaintainability Symposium, San Francisco, p.220 (22-24 January 1980). This paper describes environmental stress screening experiments performed at Hughes Aircraft Company during the past three years. The experiments performed at the module level involved large numbers of production hardware. Data is presented indicating techniques for selecting environments and optimising stress levels and duration for the screening of module level assemblies. The differences in screen results are discussed as to hardware and manufacturing processes. Also, some results tend to refute some intuitive ideas that are the rationale for some current screening practices. 42
Failure analysis on a 65K MOS RAM ~ith a new type of memor)" di_~play W. N A S S W E I T E R Fifth Solid State Circtdts Conference- ESSCIRC 79, lEE l'ubhz. 178, 113. Essential to any understanding of a semiconductor memory's failure mechanisms is a visual presentation of bits in their physical topology under varying test conditions. As part of our memory development effort we have designed a new type of Bit Map; a memory display which provides virtually a real-time presentation for interactive device characterisation. This Bit Map System forms the basis of a fast and effective failure analysis which is needed for the introduction of our new generation of 65-k bit-MOS RAM's. With it the designer identifies memory problems and relates them to specific areas or individual bits. Bit Mapping gives us a detailed analysis of electrical and logical operation by showing location and type of failure; it leads to a thorough understanding of the device down to the bit level. Implementation constraints in self-checking integrated circuits Y. C R O U Z E T and C. LANDRAULT
Fifth Solid State Circtdts Conference - ESSCIRC 79, lEE Pltbh~. 178, 58. The next few years will no doubt lead to the appearance of faulttolerant computers on the market due to several factors such as: (1) the technological evolution leading to high performance but increasingly cheaper VLSI circuits. (2) the increasing complexity of the tasks assigned to computers and, at the same time, the increasing authority of these tasks. The problems with which the designers of such fault-tolerant systems are faced must lead 1C manufacturers to introduce a new generation of circuits better adapted to the realisation of fault-tolerant systems (1, 2, 3). In this paper we do not take into account the functional constraints due to the realisation of such ICS, they are extensively dealt with in the literature (4). We only take into account the constraints linked with the implementation of such circuits. After a first paragraph of definitions, the second part of this paper is devoted to failure modelling encountered in MOS single channel ICs. This modelling enables one to divide these failures into several classes according to the type of incorrect operation that they induce. In the third part, we pinpoint the implementation constraints that follow according to the class of failures that is taken into account during the design of the fault tolerant circuit, these constraints being more or less severe according to whether we consider single, unidirectional or multiple faults. The use of an industrial x-ray source for electronic component radiation effects work L. ADAMS and I. THOMPSON IEEE Trans. Components, Hybrids Affg Technology. CHMT-3 (!), 144 (March 1980). Low energy x-ray tubes have been used as a source of ionising radiation in various past radiation effects studies. In such studies there has not been a requirement for the absolute dose to be known, and little detail has been reported regarding the tube characteristics and the type of dosimetry employed. The use of an industrial x-ray source for space environment simulation is an attractive technique in that such a source is commonly available in aerospace and semiconductor manufacturing facilities and no special licensing or safety regulations are involved. Prior to using an x-ray source for space simulation the tube characteristics must be known, a reliable technique for dosimetry must be established, and the source must be correlated with other standard space simulation sources such as the cobalt-60 gammacell. An experimental program covering the above points is described. It results in a defined procedure which can be followed by other workers interested in the use of an industrial x-ray source as a calibrated source of ionising radiation. Digital system diagnostics-design/evaluation G. A. CONLEY
Proc. Annual Reliability and Maintab~ability Symposium, San Francisco, p.38 (22-24 January 1980). This paper describes the FMEA process used on a complex digital data system. This system incorporated a central processor (general purpose computer), man/machine interface channels (magnetic tape unit and typewriter input/output), microprocessor-controlled 1/O channels, and fault detection/isolation tools in both hardware and software. The specification for the system required that 98% of all failures be