Improved and new surface analysis and depth profiling methods for the analysis of semiconductor technology problems

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World Abstracts on Microelectronics and Reliability

The impact of packaging on the reliability of flip-chip solder bonded devices. KEVINJ. LODGEand DAVID J. PEDDER. IEEE Trans. Compon. Hybrids mfg TechnoL 13(4), 847 (1990). Flip-chip solder bonding offers numerous advantags over other, more conventional interconnection methods. In particular, the small bond size and short bond length lead to minimal electrical parasitics and to excellent high frequency behavior. The designable, selfaligning nature of the bonding technique also makes it well suited for micro-optic applications. In addition, flip-chip solder bonding offers very high interconnection density and the ability to place connections over the whole active area of the flip-chip solder bonding has, to date, been limited to relatively few users operating in closely controlled environments. This is related, in part, to concern over the reliability of this particular bonding technique. In flip-chip bonded devices, all mechanical and electrical interconnections pass through the solder bonds which, even at normal operating temperatures, are working at over two thirds of their absolute melting points. At such temperatures, yield strengths are low and processes such as creep and recrystallization can occur. Cyclic stresses caused by differential expansion between dissimilar materials or similar materials at differing temperatures in a device assembly can then lead to solder joint plastic deformation and to potential failure by a low cycle fatigue mechanism. There is currently a resurgence of interest in flip-chip solder bonding for a variety of applications, including interconnection of sensor arrays, VLSI integrated circuits, and in multichip module (MCM) construction. The question of flip-chip reliability, therefore, requires renewed attention in the context of these emerging device structures. This paper reports on the assessment of flip-chip solder joint reliability for a hybrid device assembly in which a zirconium-titanium-stannate (ZTS) dielectric ceramic chip is flip-chip bonded to a silicon circuit. This device assembly was subjected to severe thermal cycling testing, involving up to 2000 cycles from - 5 5 to + 125°C. A range of device solder bond geometries and chip passivation structures was investigated, with devices packaged in both hermetic and nonhermetic enclosures. The results showed that flip-chip solder bonds can be extremely reliable under such tests, with no failures being detected in devices that were hermetically packaged. Fatigue failures were observed in nonhermetically packaged devices. Extrapolation to likely operating conditions predicted field lifetimes of between 15 and 300 a. A review of thermal enhancement techniques for electronic systems. LEROY S. FLETCHER. IEEE Trans. Compon. Hybrids mfg Technol. 13(4), 1012 (1990). The demand for electronic components which will satisfy performance standards over a wide range of environmental conditions requires the use of thermal enhancement techniques. This paper reviews recent thermal enhancement techniques for maximizing the thermal contact conductance, including greases, metallic foils, and screens, composite materials and cements, and surface treatments. The relative merits of the various enhancement techniques are summarized and comparisons are made for selected thermal enhancement materials. The results of this review will be useful in selecting thermal enhancement materials for use in improving the thermal performance of electronic systems. Preparation, structure, and fracture modes of Pb-Sn and Pb-ln terminated flip-chips attached to gold capped micro6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S , Improved and new surface analysis and depth profiling methods for the analysis of semiconductor technology problems. R. V. CRIEGERN. Vacuum 41(7-9), 1611 (1990). Following the ceaseless miniaturization of semiconductor

sockets. KARL J. PUTTLITZ. IEEE Trans. Compon. Hybrids mfg Technol. 13(4), 647 (1990). Solder-bump flip-chip (SBFC) interconnection technology has proven to be reliable, cost-effective, and extendable. This type of chip-tosubstrate connection, also referred to as a controlledcollapse chip connection or C-4, is used in IBM's multilayer ceramic (MLC), metallized ceramic (MC), and thick film packages. On MLC substrates, flip-chip interconnects are achieved by placing diced chips face down and simultaneously reflowing the chip I/Os directly to corresponding substrate pads, termed microsockets. The substrate's molybdenum thick film conductor material is not directly wet by lead-tin or lead-indium terminated chips. Several preparatory metallization steps are required to render the surface suitable for solderability and chip attach. Fatigue life of thermal cycled solder joints directly depends upon the integrity and metallurgical properties of the joint interfaces and bulk solder characteristics. This paper discusses the effect of selecting nickel, deposited from an electroless phosphorus-based bath, as the base metal to achieve solder wetting. Specifically discussed are the degrading effects on solder wetting due to precipitate formation during process thermal exposure and the use of a gold cap to prevent the problem. Also addressed are the overall metallurgical characteristics of both lead-tin and lead indium C-4 joints, as well as their relation to performance (e.g. fracture mode and fatigue life). New method of water cleaning for circuit substrate. NAO TAKAYAMA, TOMIJI SUGIYAMAand KAZUHIKOTAKAHASHI. IEEE Trans. Compon. Hybrids mfg Technol. 13(4), 685 (1990). Soldering technology using rosin flux has been developed in the electronics industry due to the advantageous characteristics that it does not cause corrosion of conductors and the stability of the flux is high. Recently, however, the solvent which is commonly used for postcleaning of rosin flux residue (CFC-II3) has been linked to environmental pollution, especially ozone depletion. Many engineers are now wrestling with the difficult problem of developing an alternative cleaning method. Until now various kinds of water soluble flux have been practically used only for the wave soldering process. Utilization of the same type of flux in solder paste for the reflow soldering process has not been successful. This is because the solder particle and the flux of solder paste are required to contact each other under chemically stable conditions for extended periods, and this technical barrier made it fairly difficult to make practical use of solder pastes containing water soluble flux. We have developed a water soluble flux paste that has excellent characteristics equivalent to those of rosin flux by improving the activator and rheological modifier. Also, we have simultaneously developed original and novel cleaning equipment. The new solder paste and cleaning method was applied to on board power supply (OBP) products, and these products passed 1500 h of temperature, humidity, bias (THB) testing. This ensures that the new method, combining the newly developed water soluble paste and the cleaning equipment, can provide the same reliability of reflow soldered product as that of the product processed by the conventional cleaning method using rosin flux and solvent. SYSTEMS

AND

circuits, the analytical technological processes This applies particularly new specific analytical

EQUIPMENTS

techniques used to develop their must be continuously improved. to the lateral resolution, but also to needs, for example the sensitive

World Abstracts on Microelectronics and Reliability detection of metal contamination on silicon surfaces. These two requirements have been selected here in order to point out some important recent advances in surface analytical techniques now available on a commercial basis for application to semiconductor technology problems, SIMOX devices and circuits. C. E. DANEL CI-~N. Vacuum 42(5/6), 383 (1991). The initial driving force for the CMOS silicon-on-insulator (SO1) technology development was the promise of improved circuit performance due to the reduced junction capacitance, latch-up free dielectric isolation, higher packing density and radiation hardness, Recent material improvements and successful LSI/VLSI circuit demonstrations have made SIMOX the leading SOl approach for CMOS circuits. The simplicity in the scaling of SIMOX integrated circuit (IC) processing and the recent demonstration that very thin film SOl MOSFETs offer significant performance improvement over bulk devices make SIMOX technology a viable alternative to the bulk CMOS scaling in the sub-half micrometer regime. This paper reviews the characteristics of the SOl devices, and the implementation of LSI/VLSI circuits on SIMOX substrates. PC chip sets reduce chip count. CHRIS TERRY. EDN. 57 (1 October 1990). IBM PC-compatible chip sets range from one to six chips and can give you caching facilities, a choice of buses, and power control. Quality monitoring of continuous flow processes. JOHN R. ENGLISH, MURALI KRISHNAMURTHIand TEP SASTRI. Computers ind. Engng 20(2), 251 (1991). In this research, existing quality control techniques for monitoring continuous flow processes are evaluated. Autocorrelation is a common characteristic of continuous flow process data, and the effect of the autocorrelated data is modelled as an autoregressive time series model of order one or two. The process is simulated on the computer for various process parameters, and the effectiveness of a given statistical process control technique for detecting known process disturbances is evaluated by determining the average run length. Due to the limitations of existing statistical process control techniques, a recursive Kalman filter is proposed as an alternative for eliminating the autocorrelation from the process data. The modelled manufacturing process, the computer simulation results, and the recursive Kalman filter are summarized in this paper. Development of a methodology for evaluating computer integrated manufacturing (CIM) implementation performance. SILVANUS J. U ~ K A and JOHN W. NAZEMETZ. Computers ind. Engng 19(1-4), 145 (1990). Competitive pressures of global markets has stimulated significant interest in upgrad-

7. S E M I C O N D U C T O R

INTEGRATED

ing of process technologies in manufacturing sectors of the economy. In response to these pressures, manufacturing firms have made substantial investments in advanced manufacturing technologies involving the pervasive use of computers to integrate the various functions of the enterprise. Although there are varying reports of the performance of these computer integrated systems, there has not been any consistent method used for evaluating implementation performance from one project and organization to the next. In order to compare Computer Integrated Manufacturing (CIM) implementation performance, effective procedures for evaluating individual projects are necessary. This paper presents an approach to evaluating CIM systems performance for comparison across a spectrum of projects. Simulation of three-dimensional effects in VLS! devices. P. CIAMPOLINI, A. PIERANTONI, A. FORGHIERI and G, BACCARANI. Microelectron. J. 21(6), 5 (1990). Two-dimensional (2D) modelling of electron devices is already established as an indispensable tool for VLS1 design, and a number of very sophisticated 2D device simulators have been developed. The increasing miniaturization and packing density of VLSI circuits is now boosting research activity towards threedimensional (3D) device simulation. In this paper we present some results obtained with our prototype 3D simulator, HFIELDS-3D, and discuss some topics related to the underlying philosophy and to the implementation of a vector code, which we are now exploiting on a CRAY X-MP48 machine. Characterization of electromigration parameters in VLSI metallizations by 1If noise measurements. ZEYNEP CELIKBUTLER, WIYI YANG, HOANG H. HOANG and WILLIAM R. HUNTER, Solid-St. Electron. 34(2), 185 (1991). Lowfrequency (LF) noise measurements were performed on aluminum thin films biased at current densities of 5 x l0 s to 3 × 106 Acm -2 at different temperatures up to 200°C. Correlation between the mechanisms causing these LF fluctuations and electromigration was investigated. Contrary to the I/~ form observed by other researchers, we observed l/f;' noise spectra where y varied between 0.8 and 1.5. Through the Arrhenius plot of noise power spectral density, activation energies ranging from 0.60 to 0.69 eV have been obtained which agree with activation energies obtained through l / f 2 noise measurement. These values also agree with activation energies measured by conventional stressing techniques and are in the same range as electromigration mechanisms originating from grain boundaries. Through the current dependence of y, and the current dependence of the noise power magnitude, we attempted to predict electromigration damage and time-to-failure. For the first time, we incorporated the current dependence of the spectral form in the analysis of noise magnitude for electromigration.

CIRCUITS,

The use of simulation in semiconductor technology development. D. C. COLEet al. Solid-St, Electron. 33(6), 591 (1990). An overview is presented on the types of problems encountered in semiconductor technology development that are actively studied today via simulation methods. Most of the simulation examples presented here are ones that have been explicitly used in actual industrial semiconductor device design cycles to aid in the optimization of device structures. The examples described here include process simulations, such as the diffusion of dopant atoms, oxidation, etching, deposition, and epitaxial growth, as well as device simulations, which predict the flow of charge carriers and field distribution within a semiconductor device, given its material structure and operating conditions. The main aim here

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MATERIALS

is to illustrate, by example, some of the capabilities of state-of-the-art simulators used in characterizing and predicting semiconductor process and device-related phenomena. We will attempt to outline the degree of sophistication of the physics incorporated in such simulation programs, and provide some contrast to the fundamental physics required for a complete physical description. As will be indicated, simulation development necessarily involves molding the appropriate physical models and numerical algorithms into a package that can be handled in a reasonable length of time by modern computing systems. We briefly outline some of the advances that have been made, and some concerns that remain, in such simulation development.