- Email: [email protected]
Improved critical area prediction by application of pattern recognition techniques
~
Microelectron. Reliab., Vol. 36, No. 11/12, pp. 1815-1818, 1996 Copyright © 1996 Elsevier Science Ltd Printed in Great Britain. All fights reserved 0026-2714/96 $15.00 + .00
t Pergamon
PIh S0026--2714(96)00204- I
IMPROVED
CRITICAL AREA PREDICTION B Y A P P L I C A T I O N OF PATTERN RECOGNITION TECHNIQUES J.H.N.MATTICK, R.W.KELSALL, R.E.MILES Department of Electronic & Electrical Engineering University of Leeds, Leeds LS2 9JT, England UK tel/fax: +44 (0)113 278-6493/233-2032 ,,~ email: [email protected]
Abstract: A novel technique to predict the susceptibility of VLSIC layouts to particle-induced failure is presented. The investigation applies the concept of Critical Areas to determine the failure probability of rectilinear layouts. A unique methodology has been devised, with which the relationship between the recurrent patterns observed within the topology of a layout and the robustness of the design against particulate contamination can be quantified. The critical area is formulated as a function of the dimensions of the identifiable geometrical shapes and the characteristics of the defect model. In comparison with current approximation methods, the proposed technique is quick, exact, adaptable for different defect models and guarantees computational accuracy irrespective of layout complexity.
Copyright © 1996 Elsevier Science Ltd THE DEMANDS OF CRITICAL AREA ANALYSIS The concept of Critical Area (CA), defined as the region of a layout where the geometrical centre of a physical defect must be located if it is to cause a particular failure mode, was proposed over a decade ago. The defect-sensitive or critical area Ac, together with the defect density Dd, are fundamental parameters in most VLSIC yield prediction models [ 1], as for example in the Murphy model given by equation (1): Y / = [ ( 1 - e-~i)/Ai] 2
where Ai = AcDd
(1)
Although the typical yield loss for each of the many sequential processing steps (N) in the fabrication of ICs is small, the good yield (Y = l-Ig=l Y/) can vary significantly. For example, by application of equation (l) and with A = 0.25, then a 5 % error in this value could cause a 1.2% variation in Yi. An error of comparable magnitude for a number of the other N - 1 steps, would result in a significant inaccuracy in the predicted cumulative yield Y. It is therefore of paramount importance that the estimation of Ai and hence the critical area (Ac) is realistic. Whereas the detection and monitoring of defects have progressively been refined in an attempt to understand and ultimately reduce their abundance, the analytical methods employed to determine CAs have progressed little. The CA should provide an effective measure by which the detrimental effect of spot defects can be predicted. Initially it was assumed that CA results derived from the analysis of trivial test structures could be applied reliably to investigate actual circuits. This
1815
1816
J . H . N . Mattick et al.
has since proved to be a fallacy; the layout topologies of modern, optimally compacted circuits are unique and bear no resemblance to those early test designs, To compound the problem, the methodologies currently employed to calculate CA frequently adopt unrealistic defect models and at best provide only an estimate. Consequently, the accuracy of the resulting yield/failure prediction is often questionable. Hence, there is an obvious need for an approach that is both exact and computationally efficient. A newly developed CA analysis technique is proposed that satisfies both these requirements; a pattern-recognition approach is implemented, which facilitates precise calculation of CA without any significant increase in computational effort. ONE PATTERN - ONE C R I T I C A L AREA By its very nature, the topology of VLSIC layouts is extremely complex. The proposed technique for their analysis divides the layout features into simpler geometrical regions; these represent a finite number of identifiable patterns in repeated combinations, which together can form the most intricate layout. Consider for example the layout illustrated in figure 1. Within the metallisation layer, seven similar 'T'-shaped patterns can be seen, each enclosed by a circle drawn on the figure. 7 IdenticalT-shaped MetallisationPatterns :~i:~i~!~i~ 4 ~ N~'.:~N~~i ~g~ .................... 1~ ':.... :J~
[
~:~i~ ~ii~iiii:~!~~i: Figure 1" Examples of a recurrent pattern
The 'T'-shapes in figure 1 account for only a fraction of the total feature material; other patterns exist and can also be identified. The ability to differentiate between their individual shapes is of great significance, since the CA can be evaluated as the sum of the Partial CA (PCA) associated with each distinct pattern. To calculate the CA, the layout description is first transformed from its original CAD-tool generated outline image, into a pattern-based representation. This new, modified format contains all the topological information to calculate the CA accurately.
Investigations have shown that the topology of any rectilinear layout can be represented by a specific combination of simple geometrical structures, that are selected from a finite list of predefined patterns; the 'T'-shape highlighted in figure 1 being an example. The PCA associated with each pattern is unique, and thus a mathematical function can be formulated to calculate its value exactly. It is then a simple task to evaluate the CA from the pattern-based representation, by summation of the individual PCA. The proposed pattern-recognition technique has the potential to reduce significantly the time taken to compute the CA for VLSIC layouts. P A T T E R N - R E C O G N I T I O N BY LAYOUT PARTITIONING Fundamental to the CA analysis technique is a procedure referred to as Partitioning - the division of a layout into precise arrangements of rectangular regions, called Partitioning Rectangles (PRs). The partitioning procedure detailed in this section, identifies the boundaries of those PRs associated with an intra-layer Short-circuit failure CA Analysis (SCA). The SCA partitioning algorithm is explained with the aid of the layout illustrated in figure 2; the layout contains three, unconnected metallisation features labelled A, E and J. The primary stage of partitioning is the extension of every edge of all features, colinearly with their original edges, until the extended-edges intersect orthogonally either with the unextended-edge of any feature, or with
Pattern recognition techniques
1817
the boundary of the layout itself. Consider first the two features A and E, as illustrated in figure 2. When sides 'ab' and 'ef' of features A and E respectively are exYmax . . . . . tended vertically, they intersect with the boundary of the layout at coordinates (xl, 0) and (:rt, Ymax). By contrast, the extended sides 'fg' Y2 and 'gh' (feature E) intersect with features J (at co-ordinate (:r3, Y2)) and A (z2, Yt) respectively. It is important to note that neither edge Yl extends through features J and A, nor do they intersect with the boundary of the layout. After this operation has been performed for 0 o XI X2 X3 every feature, the hypothetically extended sides (as denoted by the Figure 2: Partitioning dashed lines in figure 2) will denote the outlines of the PRs. Classification o f the P R s
Each PR is classified according to the topology of the region of the layout in which it is located. Consider for example the PR illustrated in figure 3. Cor,er-~ TO categorise the PRs, an elemental grid (of unit division equal to • _ .... ~ the minimum feature resolution) is first superimposed upon the par~ ~ ~ titioned layout. There is then a single grid-cell located at each of the ~]ii ~ four comers of the PR; these are labelled in figure 3. A value, referred ~-i , v i , © to as the Comer-Cell Count (CCC) and equal to the number of adjai ~ cent grid-cells composed of a dissimilar material, is now assigned to each of these four cells. The particular shape of the PR in figure 3 is classified by its ordered Figure 3: PRs and CCCs set of the CCCs and can thus be specified uniquely as {2233}. In fact, the topology of all rectilinear-style layouts can be described exactly by a combination of only 16 different patterns, where each pattern is composed of a particular arrangement of PRs. The representation of the layout is therefore transformed from its original co-ordinate-based geometry, into a precise combination of inter-connected rectangular regions (PRs). A PCA function is then associated with each pattern (as described in the next section) and used to evaluate the contribution to the overall CA, due to its constituent PRs. By application of this partitioning technique, a quick and accurate CA analysis is feasible, by virtue of this unique, simplified representation. CRITICAL AREAS AND DEFECT MODELS The popular CA analysis techniques applied today, are inherently restricted to an investigation of square-shaped defects with fixed-orientation. However, experimental evidence suggests that the irregular shapes exhibited by defects are seldom square; in fact they more closely resemble circles or ellipses [2]. Although circles have often been cited as models, they typically (see for example [3]) have not be applied beyond an investigation of the simple topologies exhibited by arrays of straight, parallel conductors. It is important that CA analysis techniques apply the most realistic models because, as will be demonstrated, this choice has a significant effect on the resulting CA prediction. If a defect of 'diameter' d is to cause a short-circuit failure between the constituent metallisation features (separated by a distance s) of two different electrical nets of a circuit, then at some location d > s. To evaluate the corresponding PCAs, it is necessary to envisage the path circumscribed by the centre of the defect around every feature; the PCAs are then defined as the closed regions whose perimeters are delineated by the loci of the defects around at least two separate nets. The
1818
J.H.N.
Mattick et al.
fraction of this region that lies within the confines of a particular PR therefore denotes its associated PCA. For both square and circular defect models, the PCAs are functions of the dimensions of the PRs and the characteristics of the specific defect model. Since the number of different types of PR is finite, the PCA function associated with each can be modified to account for any chosen (realistic) defect model, whilst the underlying pattern-recognition methodology is maintained. The capability of the proposed technique to anal: 2w : Partial Critical A r e a s yse simultaneously more than one defect model is a major advantage and enables the difference beii!ii~!" ::ii::ii:~i;:ii:!iJ- - ' . . ~. . . . .]. 2. .w i;:~l~~. tween the CAs due to circular and square defect models to be quantified. Consider an SCA of the 'L'-shaped regions (located between two conductors) illustrated in figFigure 4: PCAs of 'L'-shaped patterns ure 4. The hatched regions identify the PCAs as6o - 80 ~-- - PCA-square .~ sociated with this particular pattern, due to the ~" 5O o PCA-circle o~tr ~ CJ • o" 60 circular and square defects shown. • - PCAdifference tr.a" o ° t Q. < 40 • t~ tr o ° I It can be seen from the graph in figure 5, that for ~) 30 • • a --a~ . o ° ( 40 'E • .~ __a" o ° [ the particular pattern in figure 4, the PCA due to o 20 a square defect is in excess of 20% greater than ~tl T- 20 10 ----1 o.~o~=oo (0 that due to a circular defect. Indeed, the differ0.. 2,0 2.5 3.0 3.5 ence between the PCAs for each model when cal4.0 Defect radius (w) culated for many of the other fifteen PR patterns Figure 5: PCA for figure 4 is of comparable magnitude. DISCUSSION There is an unavoidable inaccuracy in the CA prediction made by the majority of techniques applied today due to the application of an overly simplistic square defect model. It is evident from figure 5 that, in comparison with a circular defect model, a square model results in a notable overestimation of the PCA. As a consequence, there will be significant differences between the CAs for the two defect models, when calculated for an entire layout. For example, the CA for the layout in figure 1 is calculated to be ,,~ 9% greater when a square, as opposed to a circular defect, is applied. There is an urgent requirement for a CA analysis technique with the capability to investigate realistic defect models. The proposed pattern-recognition approach fills this deficiency. Because a layout is first partitioned into smaller regions, each with an identifiable geometry, the subsequent CA prediction is simplified. Furthermore, since the pattern-based representation is a complete description of the topology of the original layout, the accuracy of the CA prediction is not compromised. By predefining the CA functions associated with each pattern, the computational effort is appreciably reduced. REFERENCES [1]
T.L.Michalka, R.C.Varshney, J.D.Meindl, A discussion of yield modeling with defect clustering, circuit repair, and circuit redundancy, IEEE Trans. on Semicon. Manu. 3-3, 116127 (1990). [2] C.Hess, A.P.Stroele, Modeling of real defect outlines and parameter extraction using a checkerboard test structure .... IEEE Trans. on Sernicon. Manu. 7-3, 284-292 (1994), [3] W.Maly, H.T.Heineken, EAgricola, A simple new yield model, Semiconductor International, 148-154 (July 1994).
Microelectron. Reliab., Vol. 36, No. 11/12, pp. 1815-1818, 1996 Copyright © 1996 Elsevier Science Ltd Printed in Great Britain. All fights reserved 0026-2714/96 $15.00 + .00
t Pergamon
PIh S0026--2714(96)00204- I
IMPROVED
CRITICAL AREA PREDICTION B Y A P P L I C A T I O N OF PATTERN RECOGNITION TECHNIQUES J.H.N.MATTICK, R.W.KELSALL, R.E.MILES Department of Electronic & Electrical Engineering University of Leeds, Leeds LS2 9JT, England UK tel/fax: +44 (0)113 278-6493/233-2032 ,,~ email: [email protected]
Abstract: A novel technique to predict the susceptibility of VLSIC layouts to particle-induced failure is presented. The investigation applies the concept of Critical Areas to determine the failure probability of rectilinear layouts. A unique methodology has been devised, with which the relationship between the recurrent patterns observed within the topology of a layout and the robustness of the design against particulate contamination can be quantified. The critical area is formulated as a function of the dimensions of the identifiable geometrical shapes and the characteristics of the defect model. In comparison with current approximation methods, the proposed technique is quick, exact, adaptable for different defect models and guarantees computational accuracy irrespective of layout complexity.
Copyright © 1996 Elsevier Science Ltd THE DEMANDS OF CRITICAL AREA ANALYSIS The concept of Critical Area (CA), defined as the region of a layout where the geometrical centre of a physical defect must be located if it is to cause a particular failure mode, was proposed over a decade ago. The defect-sensitive or critical area Ac, together with the defect density Dd, are fundamental parameters in most VLSIC yield prediction models [ 1], as for example in the Murphy model given by equation (1): Y / = [ ( 1 - e-~i)/Ai] 2
where Ai = AcDd
(1)
Although the typical yield loss for each of the many sequential processing steps (N) in the fabrication of ICs is small, the good yield (Y = l-Ig=l Y/) can vary significantly. For example, by application of equation (l) and with A = 0.25, then a 5 % error in this value could cause a 1.2% variation in Yi. An error of comparable magnitude for a number of the other N - 1 steps, would result in a significant inaccuracy in the predicted cumulative yield Y. It is therefore of paramount importance that the estimation of Ai and hence the critical area (Ac) is realistic. Whereas the detection and monitoring of defects have progressively been refined in an attempt to understand and ultimately reduce their abundance, the analytical methods employed to determine CAs have progressed little. The CA should provide an effective measure by which the detrimental effect of spot defects can be predicted. Initially it was assumed that CA results derived from the analysis of trivial test structures could be applied reliably to investigate actual circuits. This
1815
1816
J . H . N . Mattick et al.
has since proved to be a fallacy; the layout topologies of modern, optimally compacted circuits are unique and bear no resemblance to those early test designs, To compound the problem, the methodologies currently employed to calculate CA frequently adopt unrealistic defect models and at best provide only an estimate. Consequently, the accuracy of the resulting yield/failure prediction is often questionable. Hence, there is an obvious need for an approach that is both exact and computationally efficient. A newly developed CA analysis technique is proposed that satisfies both these requirements; a pattern-recognition approach is implemented, which facilitates precise calculation of CA without any significant increase in computational effort. ONE PATTERN - ONE C R I T I C A L AREA By its very nature, the topology of VLSIC layouts is extremely complex. The proposed technique for their analysis divides the layout features into simpler geometrical regions; these represent a finite number of identifiable patterns in repeated combinations, which together can form the most intricate layout. Consider for example the layout illustrated in figure 1. Within the metallisation layer, seven similar 'T'-shaped patterns can be seen, each enclosed by a circle drawn on the figure. 7 IdenticalT-shaped MetallisationPatterns :~i:~i~!~i~ 4 ~ N~'.:~N~~i ~g~ .................... 1~ ':.... :J~
[
~:~i~ ~ii~iiii:~!~~i: Figure 1" Examples of a recurrent pattern
The 'T'-shapes in figure 1 account for only a fraction of the total feature material; other patterns exist and can also be identified. The ability to differentiate between their individual shapes is of great significance, since the CA can be evaluated as the sum of the Partial CA (PCA) associated with each distinct pattern. To calculate the CA, the layout description is first transformed from its original CAD-tool generated outline image, into a pattern-based representation. This new, modified format contains all the topological information to calculate the CA accurately.
Investigations have shown that the topology of any rectilinear layout can be represented by a specific combination of simple geometrical structures, that are selected from a finite list of predefined patterns; the 'T'-shape highlighted in figure 1 being an example. The PCA associated with each pattern is unique, and thus a mathematical function can be formulated to calculate its value exactly. It is then a simple task to evaluate the CA from the pattern-based representation, by summation of the individual PCA. The proposed pattern-recognition technique has the potential to reduce significantly the time taken to compute the CA for VLSIC layouts. P A T T E R N - R E C O G N I T I O N BY LAYOUT PARTITIONING Fundamental to the CA analysis technique is a procedure referred to as Partitioning - the division of a layout into precise arrangements of rectangular regions, called Partitioning Rectangles (PRs). The partitioning procedure detailed in this section, identifies the boundaries of those PRs associated with an intra-layer Short-circuit failure CA Analysis (SCA). The SCA partitioning algorithm is explained with the aid of the layout illustrated in figure 2; the layout contains three, unconnected metallisation features labelled A, E and J. The primary stage of partitioning is the extension of every edge of all features, colinearly with their original edges, until the extended-edges intersect orthogonally either with the unextended-edge of any feature, or with
Pattern recognition techniques
1817
the boundary of the layout itself. Consider first the two features A and E, as illustrated in figure 2. When sides 'ab' and 'ef' of features A and E respectively are exYmax . . . . . tended vertically, they intersect with the boundary of the layout at coordinates (xl, 0) and (:rt, Ymax). By contrast, the extended sides 'fg' Y2 and 'gh' (feature E) intersect with features J (at co-ordinate (:r3, Y2)) and A (z2, Yt) respectively. It is important to note that neither edge Yl extends through features J and A, nor do they intersect with the boundary of the layout. After this operation has been performed for 0 o XI X2 X3 every feature, the hypothetically extended sides (as denoted by the Figure 2: Partitioning dashed lines in figure 2) will denote the outlines of the PRs. Classification o f the P R s
Each PR is classified according to the topology of the region of the layout in which it is located. Consider for example the PR illustrated in figure 3. Cor,er-~ TO categorise the PRs, an elemental grid (of unit division equal to • _ .... ~ the minimum feature resolution) is first superimposed upon the par~ ~ ~ titioned layout. There is then a single grid-cell located at each of the ~]ii ~ four comers of the PR; these are labelled in figure 3. A value, referred ~-i , v i , © to as the Comer-Cell Count (CCC) and equal to the number of adjai ~ cent grid-cells composed of a dissimilar material, is now assigned to each of these four cells. The particular shape of the PR in figure 3 is classified by its ordered Figure 3: PRs and CCCs set of the CCCs and can thus be specified uniquely as {2233}. In fact, the topology of all rectilinear-style layouts can be described exactly by a combination of only 16 different patterns, where each pattern is composed of a particular arrangement of PRs. The representation of the layout is therefore transformed from its original co-ordinate-based geometry, into a precise combination of inter-connected rectangular regions (PRs). A PCA function is then associated with each pattern (as described in the next section) and used to evaluate the contribution to the overall CA, due to its constituent PRs. By application of this partitioning technique, a quick and accurate CA analysis is feasible, by virtue of this unique, simplified representation. CRITICAL AREAS AND DEFECT MODELS The popular CA analysis techniques applied today, are inherently restricted to an investigation of square-shaped defects with fixed-orientation. However, experimental evidence suggests that the irregular shapes exhibited by defects are seldom square; in fact they more closely resemble circles or ellipses [2]. Although circles have often been cited as models, they typically (see for example [3]) have not be applied beyond an investigation of the simple topologies exhibited by arrays of straight, parallel conductors. It is important that CA analysis techniques apply the most realistic models because, as will be demonstrated, this choice has a significant effect on the resulting CA prediction. If a defect of 'diameter' d is to cause a short-circuit failure between the constituent metallisation features (separated by a distance s) of two different electrical nets of a circuit, then at some location d > s. To evaluate the corresponding PCAs, it is necessary to envisage the path circumscribed by the centre of the defect around every feature; the PCAs are then defined as the closed regions whose perimeters are delineated by the loci of the defects around at least two separate nets. The
1818
J.H.N.
Mattick et al.
fraction of this region that lies within the confines of a particular PR therefore denotes its associated PCA. For both square and circular defect models, the PCAs are functions of the dimensions of the PRs and the characteristics of the specific defect model. Since the number of different types of PR is finite, the PCA function associated with each can be modified to account for any chosen (realistic) defect model, whilst the underlying pattern-recognition methodology is maintained. The capability of the proposed technique to anal: 2w : Partial Critical A r e a s yse simultaneously more than one defect model is a major advantage and enables the difference beii!ii~!" ::ii::ii:~i;:ii:!iJ- - ' . . ~. . . . .]. 2. .w i;:~l~~. tween the CAs due to circular and square defect models to be quantified. Consider an SCA of the 'L'-shaped regions (located between two conductors) illustrated in figFigure 4: PCAs of 'L'-shaped patterns ure 4. The hatched regions identify the PCAs as6o - 80 ~-- - PCA-square .~ sociated with this particular pattern, due to the ~" 5O o PCA-circle o~tr ~ CJ • o" 60 circular and square defects shown. • - PCAdifference tr.a" o ° t Q. < 40 • t~ tr o ° I It can be seen from the graph in figure 5, that for ~) 30 • • a --a~ . o ° ( 40 'E • .~ __a" o ° [ the particular pattern in figure 4, the PCA due to o 20 a square defect is in excess of 20% greater than ~tl T- 20 10 ----1 o.~o~=oo (0 that due to a circular defect. Indeed, the differ0.. 2,0 2.5 3.0 3.5 ence between the PCAs for each model when cal4.0 Defect radius (w) culated for many of the other fifteen PR patterns Figure 5: PCA for figure 4 is of comparable magnitude. DISCUSSION There is an unavoidable inaccuracy in the CA prediction made by the majority of techniques applied today due to the application of an overly simplistic square defect model. It is evident from figure 5 that, in comparison with a circular defect model, a square model results in a notable overestimation of the PCA. As a consequence, there will be significant differences between the CAs for the two defect models, when calculated for an entire layout. For example, the CA for the layout in figure 1 is calculated to be ,,~ 9% greater when a square, as opposed to a circular defect, is applied. There is an urgent requirement for a CA analysis technique with the capability to investigate realistic defect models. The proposed pattern-recognition approach fills this deficiency. Because a layout is first partitioned into smaller regions, each with an identifiable geometry, the subsequent CA prediction is simplified. Furthermore, since the pattern-based representation is a complete description of the topology of the original layout, the accuracy of the CA prediction is not compromised. By predefining the CA functions associated with each pattern, the computational effort is appreciably reduced. REFERENCES [1]
T.L.Michalka, R.C.Varshney, J.D.Meindl, A discussion of yield modeling with defect clustering, circuit repair, and circuit redundancy, IEEE Trans. on Semicon. Manu. 3-3, 116127 (1990). [2] C.Hess, A.P.Stroele, Modeling of real defect outlines and parameter extraction using a checkerboard test structure .... IEEE Trans. on Sernicon. Manu. 7-3, 284-292 (1994), [3] W.Maly, H.T.Heineken, EAgricola, A simple new yield model, Semiconductor International, 148-154 (July 1994).