- Email: [email protected]
Improved nanotriode fabrication process for multiple gates and reduced leakage current
Microelectronic Engineering 73–74 (2004) 797–802 www.elsevier.com/locate/mee
Improved nanotriode fabrication process for multiple gates and reduced leakage current A.M. Blackburn a
a,*
, D.G. Hasko a, D.A. Williams
b
Microelectronics Research Centre, Cavendish Laboratory, University of Cambridge, Madingley Road, Cambridge CB3 0HE, UK b Hitachi Cambridge Laboratory, Hitachi Europe Ltd., Cavendish Laboratory, Madingley Road, Cambridge CB3 0HE, UK Available online 19 March 2004
Abstract The nanotriode is a novel vacuum microelectronic device, in which electrons are emitted from a metal nanopillar with tip radius <1 nm in an integrated vacuum chamber, over a distance of about 100 nm. In this work, the nanotriode fabrication process has been revised, with the aim of creating nanotriode-type devices with additional gates. The resultant structure has smooth steps on the outer edges of the RF magnetron-sputtered tungsten–silicon dioxide multilayer stack, which aids the isolation of the electrode layers. This improved structure contributes reduced inter-electrode leakage currents. The form of the nanopillars has also been investigated by cross-sectional TEM. 2004 Elsevier B.V. All rights reserved. Keywords: Vacuum microelectronics; Multilayer films; Field emitters
1. Introduction Vacuum microelectronics offers a number of advantages over conventional solid-state microelectronics. In particular, the transport of electrons is always ballistic and devices have greatly improved radiation hardness. The use of field emission electron sources of nanometre size in vacuum microelectronics introduces effects such as selfcollimation, high brightness and beam coherence. Reducing the overall scale of the device enables operation at low voltage, so that the wave properties of the electron can influence the character*
Corresponding author. E-mail address: [email protected] (A.M. Blackburn).
istics of the device. In the nanotriode the use of nanoscale tungsten field emitters with an anode– cathode separation of only about 100 nm resulted in a particularly low turn-on voltage for field emission of around 8 V [1]. Conventional triode characteristics were obtained from the nanotriode, superimposed with repeatable fluctuations in the current, which were attributed to quantum interference [2]. However, the small separation between electrodes in the nanotriode leads to significant problems with leakage currents and breakdown, due to surface tracking over the isolating dielectric. Recent work has looked at increasing the isolating dielectric path length, without increasing the separation between the cathode and extractor electrode, by using a pedestal structure [3].
0167-9317/$ - see front matter 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2004.03.054
798
A.M. Blackburn et al. / Microelectronic Engineering 73–74 (2004) 797–802
This work reports on progress made in extending the nanotriode fabrication process to include further gates. These additional gates will allow greater control of the electron transport by using separate extractor and gate electrodes. The formation of nanopillars has also been investigated using a transmission electron microscope (TEM), to enable a clearer characterisation of the device structure.
2. Fabrication In the nanotriode fabrication process, RF magnetron-sputter deposited tungsten is used to form the cathode, gate and anode layers with thicknesses of 50, 30 and 150 nm, respectively. Similarly, sputtered silicon dioxide, of thickness 30 nm, forms the dielectric separation between these electrode layers. Selective etching is used to form the device chamber, which is subsequently sealed under vacuum using a layer of titanium deposited by thermal evaporation. However, the RF magnetron-sputter process used to deposit all of these layers produces mechanically stressed films, and the magnitude of this stress is influenced by the deposition conditions and by the film thickness. The effects of this stress are significant in thicker films and a high stress can lead to the deposited film tearing or buckling, to the distortion of pat-
terned features and to the eventual detachment of the film from the substrate. When depositing the tungsten and silicon dioxide layers, to form four electrode layers, it was found necessary to sputter the tungsten at a high argon pressure (1.5 · 102 mbar) in order to reduce the compressive stress in the film. Previous work has shown that using a high argon pressure decreases the stress in tungsten films greatly [4]. The SiO2 layer was deposited at a much lower pressure (4 · 104 mbar); although this condition produces compressive stress, the films are of high density and electrical quality, which is essential for this application. However, the higher argon pressure, used for the tungsten deposition process, makes lift-off difficult, even when using a dual layer resist with large undercut. This leads to a ‘lilypad’ edge effect on features remaining on the substrate after liftoff. Any thin conformal dielectric film deposited over a lilypad edge offers poor isolation to a metal layer subsequently deposited on top. Depositing the multilayer tungsten–silicon dioxide stack as continuous films, and subsequently carrying out any coarse patterning of the individual films by selective wet etching, using photoresist as a mask, was used to overcome this problem. Tungsten layers were wet etched using an alkaline-buffered potassium ferricyanide solution, containing K3 Fe(CN)6 , KOH and KH2 PO4 [5].
Fig. 1. Fabrication sequence for the external structure of a device with two gates: (a) wet etch of top tungsten anode layer, through a photoresist mask; (b–d) BHF etch of inter-electrode SiO2 layers, followed by wet etch of tungsten electrode layers; (e) RF magnetronsputter deposition of SiO2 , followed by a selective BHF etch down to the tungsten electrode layer; (f) RF magnetron-sputter deposition of aluminium contacts. The contact to the upper gate is illustrated (e and f); contacts to the other electrode layers are formed in the same way.
A.M. Blackburn et al. / Microelectronic Engineering 73–74 (2004) 797–802
Silicon dioxide layers were wet etched using buffered hydrofluoric acid (BHF). Shipley S1813 photoresist was used for the mask, with HMDS vapour priming employed to improve resist adhesion to SiO2 . A tetrode structure (i.e. four electrodes) was patterned by firstly wet etching the anode through a photoresist mask (Fig. 1(a)), then wet etching through another mask to define the outline of the underlying electrode, using BHF and ferricyanide etches (Fig. 1(b)). This was repeated until the bottom electrode was defined (Fig. 1(c) and (d)). Following this, SiO2 was deposited, through which windows were etched using BHF to reach the metal electrode layers (Fig. 1(e)). To enable external connection to the device, aluminium bondpads were sputter deposited to contact the electrode layers (Fig. 1(f)). After completion of the external structure, the chamber was formed in a manner similar to that used for the fabrication of the nanotriode. First, aluminium was deposited onto the top anode layer, through a lift-off mask (Fig. 2(a)). Then, an aperture was formed by reactive ion etching (SiCl4 ) through a polymethylmethacrylate (PMMA) mask defined by high-resolution electron-beam lithography (Fig. 2(b)). Next, a dual
799
layer resist of low and high molecular weight PMMA was spun over the device, and a window exposed within the boundary of the underlying aluminium (Fig. 2(c)). This performed the dual functions of protecting the rest of the device during subsequent processing and acting as a lift-off mask for the final sealing stage of the process. Reactive ion etching using CF4 and O2 was then used to etch the anode aperture, aluminium being a very effective mask for this etch process. This was followed by an isotropic BHF etch to remove the SiO2 and the aluminium (Fig. 2(d)). The aluminium was then replaced, by thermal evaporation at an angle while rotating the sample. Protection of the underlying SiO2 edges from subsequent BHF etching was also given at this stage by spin coating the sample with photoresist and then carrying out an anisotropic oxygen plasma etch, which leaves a plug of photoresist under the edge of each etched tungsten layer (Fig. 2(e)). These etching and mask reapplication stages were then repeated until the bottom tungsten layer was reached (Fig. 2(f) and (g)), after which the photoresist plugs were removed by an isotropic oxygen plasma etch. Tungsten was then sputtered to form a pedestal structure at the base of the chamber (Fig. 2(h))
Fig. 2. Fabrication process for the chamber of a device with two gates: (a) Al deposited through a lift-off process; (b) Al aperture mask defined by RIE through a PMMA mask; (c) application of a thick PMMA mask, to protect the rest of the device during subsequent processing; (d) formation of the aperture by RIE, followed by BHF etching of the dielectric and Al; (e) angled evaporation of Al, carried out while rotating the device in the substrate plane, followed by spin coating with photoresist and anisotropic oxygen plasma etching, to leave a plug of resist under the free edge of the electrode; (f) the next electrode aperture is formed, as in (d), this being repeated until the bottom electrode is reached (g); (h) deposition of tungsten pedestal; (i) ionised beam evaporation of AuPd grains, followed by a short RIE to form nanopillars; (j) rotating angled evaporation of Ti to seal the structure and resist strip.
800
A.M. Blackburn et al. / Microelectronic Engineering 73–74 (2004) 797–802
after a short argon-sputter etch, which was applied to improve film adhesion [3]. AuPd (composition 60/40 by weight) was then deposited by a special ionised beam evaporation process, discussed elsewhere [6], to a nominal thickness of less than 1 nm as measured on a film thickness monitor. This formed a granular film, which was used as a selfaligned mask for a short reactive ion etch process (15 s, CF4 :O2 of 10:1, pressure 10 mTorr, power density 0.35 W/cm2 ) to form the nanopillars (Fig. 2(i)). Finally, the device was encapsulated under a vacuum of 10 6 mbar, using a rotating angled evaporation of titanium, with the unwanted titanium being lifted off using the undercut resist layer produced earlier (Fig. 2(j)).
3. Results and discussion 3.1. Device structure A montage of scanning electron micrograph (SEM) images of cleaved cross-sections from a test structure with five tungsten electrode layers is shown in Fig. 3. All of the silicon dioxide–tungsten interfaces remained intact during the considerable number of processing stages required to produce the structure. In addition, the SiO2 layers are undercut due to the wet etching of the tungsten layers (Fig 3(b)–(d)). The overhanging SiO2 layers are bent down at the outer edge providing a smooth step for the overlying layers to traverse. This enables good step coverage by subsequently deposited dielectric and metal layers, so greatly
improving the reliability of the fabrication and providing good electrical isolation between the electrodes. The leakage current and breakdown voltage of the extractor–cathode gap have previously been improved by the use of a pedestal structure [3]. The use of the pedestal structure reduced the leakage current from around 300 pA (at 7 V extractor–cathode potential difference) in the original nanotriode structure to around 100 pA in the pedestal structure, at a similar electric field. 3.2. Nanopillar examination The nanopillars are formed using the randomly distributed gold–palladium grains, of diameter 2–3 nm and slightly greater separation, deposited by the ionised evaporation method directly as an etch mask for RIE [1]. The exposed tungsten is anisotropically etched at a higher rate than the gold– palladium grains, with the distribution of grain sizes leading to a range of pillar sizes and shapes. The remaining grains are reduced in size and the separation between pillars is much greater than that of the original grains, some of which are completely undercut. Bright spots seen in SEM observations of etched samples indicate the locations of AuPd grains at the tops of the nanopillars (Fig. 4(a)). However, little additional information about the structure of the nanopillars can be obtained since the feature size is close to the ultimate resolution of the SEM and there is poor contrast between the tungsten pillars and tungsten supporting substrate, though the gold–palladium grains do show good contrast with the tungsten.
Fig. 3. SEM cross-section images of the anode (a), gate (b–d) and cathode (e) layer edges of the external structure of a three-gate device.
A.M. Blackburn et al. / Microelectronic Engineering 73–74 (2004) 797–802
801
Fig. 4. (a) SEM image of nanopillars, viewed normal to the substrate. (b) Cross-section TEM image of nanopillars formed in a tungsten layer. (c) Schematic diagram of the nanopillars.
Transmission electron microscopy was carried out on a nanopillar sample in order to gain further insight into their formation. Nanopillars were prepared over a large area of tungsten deposited on a GaAs substrate. These pillars were coated with thermally evaporated aluminium shortly after preparation to reduce contamination and to allow the sample to be sectioned and thinned without damaging the nanopillars. Aluminium was chosen for this purpose as the low atomic number allows good contrast with the nanopillar tungsten in the TEM. Cross-sections from the sample were prepared; however, even a very thin region (typically 100 nm thick) contains many nanopillars overlying each other. The bright field TEM image (Fig. 4(b)) shows a series of narrow (<1 nm) dark bands running horizontally across the image and parallel to the substrate. It is believed these bands indicate the location of the remaining gold–palladium grains. Unfortunately, reliable energy dispersive X-ray (EDX) measurements on this layer were deemed unobtainable with our sample and TEM setup, and hence were not collected. Approximately, 5– 7 nm below these bands an abrupt change in the contrast is seen, indicating the location of the underlying tungsten substrate. The region between is occupied by tungsten nanopillars and aluminium. Faint dark vertical bands (of width 1 nm) reach upwards from the base tungsten, becoming fainter as they near the gold–palladium layers. Numerous darker triangular shapes, of width 1 nm, are seen close to the base tungsten, both overlapping and adjacent to each
other. The bases of these bands show some tendency to align upon the triangular forms, though the band edges of some are too soft to see this alignment. A schematic view of the expected structure of the nanopillars is shown in Fig. 4(c). The conical and truncated pillar shape gives a decreasing tungsten density as the separation from the underlying tungsten substrate increases, until the AuPd layer is reached, where the tungsten density falls to zero. The contrast seen in the TEM image is modified from that expected using this simple model since the surface of the underlying tungsten is not quite flat. The effect of the non-flatness can be clearly seen in the contrast due to the AuPd grains, which now give rise to several bands rather than one single band. The various darker shapes between the AuPd layer and the underlying tungsten layer are due to the overlap between pillars of various heights. In summary, the TEM image indicates a pillar height of between 5 and 8 nm, which is slightly less than the value expected from unmasked etching under these conditions.
4. Conclusion The nanotriode fabrication process has been improved in order to increase inter-electrode breakdown voltages, reduce leakage currents and to reduce the effects of compressive strain in the deposited layers, which leads to mechanical failure of the structure. The modified process has yielded structures with up to five electrode layers, with
802
A.M. Blackburn et al. / Microelectronic Engineering 73–74 (2004) 797–802
good mechanical integrity and high inter-electrode isolation. The average height of the nanopillars has been characterised by TEM examination.
Acknowledgements The authors thank Simon Newcomb at the University of Limerick for the TEM examination of the nanopillars. A.M. Blackburn is grateful for financial support from EPSRC and an industrial CASE studentship from Hitachi.
References [1] A.A.G. Driskill-Smith, D.G. Hasko, H. Ahmed, Appl. Phys. Lett. 75 (1999) 2845. [2] A.A.G. Driskill-Smith, D.G. Hasko, H. Ahmed, J. Vac. Sci. Technol. B 18 (6) (2000) 3481. [3] A.M. Blackburn, D.G. Hasko, H. Ahmed, J. Vac. Sci. Technol. B 22 (2004), in press. [4] C.C. Fang, F. Jones, R.R. Kola, G.K. Celler, V. Prasad, J. Vac. Sci. Technol. B 11 (6) (1993) 2947. [5] T.A. Shankoff, E.A. Chandross, J. Electrochem. Soc. 122 (2) (1975) 295. [6] W. Chen, H. Ahmed, J. Vac. Sci. Technol. B 11 (1993) 2519.
Improved nanotriode fabrication process for multiple gates and reduced leakage current A.M. Blackburn a
a,*
, D.G. Hasko a, D.A. Williams
b
Microelectronics Research Centre, Cavendish Laboratory, University of Cambridge, Madingley Road, Cambridge CB3 0HE, UK b Hitachi Cambridge Laboratory, Hitachi Europe Ltd., Cavendish Laboratory, Madingley Road, Cambridge CB3 0HE, UK Available online 19 March 2004
Abstract The nanotriode is a novel vacuum microelectronic device, in which electrons are emitted from a metal nanopillar with tip radius <1 nm in an integrated vacuum chamber, over a distance of about 100 nm. In this work, the nanotriode fabrication process has been revised, with the aim of creating nanotriode-type devices with additional gates. The resultant structure has smooth steps on the outer edges of the RF magnetron-sputtered tungsten–silicon dioxide multilayer stack, which aids the isolation of the electrode layers. This improved structure contributes reduced inter-electrode leakage currents. The form of the nanopillars has also been investigated by cross-sectional TEM. 2004 Elsevier B.V. All rights reserved. Keywords: Vacuum microelectronics; Multilayer films; Field emitters
1. Introduction Vacuum microelectronics offers a number of advantages over conventional solid-state microelectronics. In particular, the transport of electrons is always ballistic and devices have greatly improved radiation hardness. The use of field emission electron sources of nanometre size in vacuum microelectronics introduces effects such as selfcollimation, high brightness and beam coherence. Reducing the overall scale of the device enables operation at low voltage, so that the wave properties of the electron can influence the character*
Corresponding author. E-mail address: [email protected] (A.M. Blackburn).
istics of the device. In the nanotriode the use of nanoscale tungsten field emitters with an anode– cathode separation of only about 100 nm resulted in a particularly low turn-on voltage for field emission of around 8 V [1]. Conventional triode characteristics were obtained from the nanotriode, superimposed with repeatable fluctuations in the current, which were attributed to quantum interference [2]. However, the small separation between electrodes in the nanotriode leads to significant problems with leakage currents and breakdown, due to surface tracking over the isolating dielectric. Recent work has looked at increasing the isolating dielectric path length, without increasing the separation between the cathode and extractor electrode, by using a pedestal structure [3].
0167-9317/$ - see front matter 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2004.03.054
798
A.M. Blackburn et al. / Microelectronic Engineering 73–74 (2004) 797–802
This work reports on progress made in extending the nanotriode fabrication process to include further gates. These additional gates will allow greater control of the electron transport by using separate extractor and gate electrodes. The formation of nanopillars has also been investigated using a transmission electron microscope (TEM), to enable a clearer characterisation of the device structure.
2. Fabrication In the nanotriode fabrication process, RF magnetron-sputter deposited tungsten is used to form the cathode, gate and anode layers with thicknesses of 50, 30 and 150 nm, respectively. Similarly, sputtered silicon dioxide, of thickness 30 nm, forms the dielectric separation between these electrode layers. Selective etching is used to form the device chamber, which is subsequently sealed under vacuum using a layer of titanium deposited by thermal evaporation. However, the RF magnetron-sputter process used to deposit all of these layers produces mechanically stressed films, and the magnitude of this stress is influenced by the deposition conditions and by the film thickness. The effects of this stress are significant in thicker films and a high stress can lead to the deposited film tearing or buckling, to the distortion of pat-
terned features and to the eventual detachment of the film from the substrate. When depositing the tungsten and silicon dioxide layers, to form four electrode layers, it was found necessary to sputter the tungsten at a high argon pressure (1.5 · 102 mbar) in order to reduce the compressive stress in the film. Previous work has shown that using a high argon pressure decreases the stress in tungsten films greatly [4]. The SiO2 layer was deposited at a much lower pressure (4 · 104 mbar); although this condition produces compressive stress, the films are of high density and electrical quality, which is essential for this application. However, the higher argon pressure, used for the tungsten deposition process, makes lift-off difficult, even when using a dual layer resist with large undercut. This leads to a ‘lilypad’ edge effect on features remaining on the substrate after liftoff. Any thin conformal dielectric film deposited over a lilypad edge offers poor isolation to a metal layer subsequently deposited on top. Depositing the multilayer tungsten–silicon dioxide stack as continuous films, and subsequently carrying out any coarse patterning of the individual films by selective wet etching, using photoresist as a mask, was used to overcome this problem. Tungsten layers were wet etched using an alkaline-buffered potassium ferricyanide solution, containing K3 Fe(CN)6 , KOH and KH2 PO4 [5].
Fig. 1. Fabrication sequence for the external structure of a device with two gates: (a) wet etch of top tungsten anode layer, through a photoresist mask; (b–d) BHF etch of inter-electrode SiO2 layers, followed by wet etch of tungsten electrode layers; (e) RF magnetronsputter deposition of SiO2 , followed by a selective BHF etch down to the tungsten electrode layer; (f) RF magnetron-sputter deposition of aluminium contacts. The contact to the upper gate is illustrated (e and f); contacts to the other electrode layers are formed in the same way.
A.M. Blackburn et al. / Microelectronic Engineering 73–74 (2004) 797–802
Silicon dioxide layers were wet etched using buffered hydrofluoric acid (BHF). Shipley S1813 photoresist was used for the mask, with HMDS vapour priming employed to improve resist adhesion to SiO2 . A tetrode structure (i.e. four electrodes) was patterned by firstly wet etching the anode through a photoresist mask (Fig. 1(a)), then wet etching through another mask to define the outline of the underlying electrode, using BHF and ferricyanide etches (Fig. 1(b)). This was repeated until the bottom electrode was defined (Fig. 1(c) and (d)). Following this, SiO2 was deposited, through which windows were etched using BHF to reach the metal electrode layers (Fig. 1(e)). To enable external connection to the device, aluminium bondpads were sputter deposited to contact the electrode layers (Fig. 1(f)). After completion of the external structure, the chamber was formed in a manner similar to that used for the fabrication of the nanotriode. First, aluminium was deposited onto the top anode layer, through a lift-off mask (Fig. 2(a)). Then, an aperture was formed by reactive ion etching (SiCl4 ) through a polymethylmethacrylate (PMMA) mask defined by high-resolution electron-beam lithography (Fig. 2(b)). Next, a dual
799
layer resist of low and high molecular weight PMMA was spun over the device, and a window exposed within the boundary of the underlying aluminium (Fig. 2(c)). This performed the dual functions of protecting the rest of the device during subsequent processing and acting as a lift-off mask for the final sealing stage of the process. Reactive ion etching using CF4 and O2 was then used to etch the anode aperture, aluminium being a very effective mask for this etch process. This was followed by an isotropic BHF etch to remove the SiO2 and the aluminium (Fig. 2(d)). The aluminium was then replaced, by thermal evaporation at an angle while rotating the sample. Protection of the underlying SiO2 edges from subsequent BHF etching was also given at this stage by spin coating the sample with photoresist and then carrying out an anisotropic oxygen plasma etch, which leaves a plug of photoresist under the edge of each etched tungsten layer (Fig. 2(e)). These etching and mask reapplication stages were then repeated until the bottom tungsten layer was reached (Fig. 2(f) and (g)), after which the photoresist plugs were removed by an isotropic oxygen plasma etch. Tungsten was then sputtered to form a pedestal structure at the base of the chamber (Fig. 2(h))
Fig. 2. Fabrication process for the chamber of a device with two gates: (a) Al deposited through a lift-off process; (b) Al aperture mask defined by RIE through a PMMA mask; (c) application of a thick PMMA mask, to protect the rest of the device during subsequent processing; (d) formation of the aperture by RIE, followed by BHF etching of the dielectric and Al; (e) angled evaporation of Al, carried out while rotating the device in the substrate plane, followed by spin coating with photoresist and anisotropic oxygen plasma etching, to leave a plug of resist under the free edge of the electrode; (f) the next electrode aperture is formed, as in (d), this being repeated until the bottom electrode is reached (g); (h) deposition of tungsten pedestal; (i) ionised beam evaporation of AuPd grains, followed by a short RIE to form nanopillars; (j) rotating angled evaporation of Ti to seal the structure and resist strip.
800
A.M. Blackburn et al. / Microelectronic Engineering 73–74 (2004) 797–802
after a short argon-sputter etch, which was applied to improve film adhesion [3]. AuPd (composition 60/40 by weight) was then deposited by a special ionised beam evaporation process, discussed elsewhere [6], to a nominal thickness of less than 1 nm as measured on a film thickness monitor. This formed a granular film, which was used as a selfaligned mask for a short reactive ion etch process (15 s, CF4 :O2 of 10:1, pressure 10 mTorr, power density 0.35 W/cm2 ) to form the nanopillars (Fig. 2(i)). Finally, the device was encapsulated under a vacuum of 10 6 mbar, using a rotating angled evaporation of titanium, with the unwanted titanium being lifted off using the undercut resist layer produced earlier (Fig. 2(j)).
3. Results and discussion 3.1. Device structure A montage of scanning electron micrograph (SEM) images of cleaved cross-sections from a test structure with five tungsten electrode layers is shown in Fig. 3. All of the silicon dioxide–tungsten interfaces remained intact during the considerable number of processing stages required to produce the structure. In addition, the SiO2 layers are undercut due to the wet etching of the tungsten layers (Fig 3(b)–(d)). The overhanging SiO2 layers are bent down at the outer edge providing a smooth step for the overlying layers to traverse. This enables good step coverage by subsequently deposited dielectric and metal layers, so greatly
improving the reliability of the fabrication and providing good electrical isolation between the electrodes. The leakage current and breakdown voltage of the extractor–cathode gap have previously been improved by the use of a pedestal structure [3]. The use of the pedestal structure reduced the leakage current from around 300 pA (at 7 V extractor–cathode potential difference) in the original nanotriode structure to around 100 pA in the pedestal structure, at a similar electric field. 3.2. Nanopillar examination The nanopillars are formed using the randomly distributed gold–palladium grains, of diameter 2–3 nm and slightly greater separation, deposited by the ionised evaporation method directly as an etch mask for RIE [1]. The exposed tungsten is anisotropically etched at a higher rate than the gold– palladium grains, with the distribution of grain sizes leading to a range of pillar sizes and shapes. The remaining grains are reduced in size and the separation between pillars is much greater than that of the original grains, some of which are completely undercut. Bright spots seen in SEM observations of etched samples indicate the locations of AuPd grains at the tops of the nanopillars (Fig. 4(a)). However, little additional information about the structure of the nanopillars can be obtained since the feature size is close to the ultimate resolution of the SEM and there is poor contrast between the tungsten pillars and tungsten supporting substrate, though the gold–palladium grains do show good contrast with the tungsten.
Fig. 3. SEM cross-section images of the anode (a), gate (b–d) and cathode (e) layer edges of the external structure of a three-gate device.
A.M. Blackburn et al. / Microelectronic Engineering 73–74 (2004) 797–802
801
Fig. 4. (a) SEM image of nanopillars, viewed normal to the substrate. (b) Cross-section TEM image of nanopillars formed in a tungsten layer. (c) Schematic diagram of the nanopillars.
Transmission electron microscopy was carried out on a nanopillar sample in order to gain further insight into their formation. Nanopillars were prepared over a large area of tungsten deposited on a GaAs substrate. These pillars were coated with thermally evaporated aluminium shortly after preparation to reduce contamination and to allow the sample to be sectioned and thinned without damaging the nanopillars. Aluminium was chosen for this purpose as the low atomic number allows good contrast with the nanopillar tungsten in the TEM. Cross-sections from the sample were prepared; however, even a very thin region (typically 100 nm thick) contains many nanopillars overlying each other. The bright field TEM image (Fig. 4(b)) shows a series of narrow (<1 nm) dark bands running horizontally across the image and parallel to the substrate. It is believed these bands indicate the location of the remaining gold–palladium grains. Unfortunately, reliable energy dispersive X-ray (EDX) measurements on this layer were deemed unobtainable with our sample and TEM setup, and hence were not collected. Approximately, 5– 7 nm below these bands an abrupt change in the contrast is seen, indicating the location of the underlying tungsten substrate. The region between is occupied by tungsten nanopillars and aluminium. Faint dark vertical bands (of width 1 nm) reach upwards from the base tungsten, becoming fainter as they near the gold–palladium layers. Numerous darker triangular shapes, of width 1 nm, are seen close to the base tungsten, both overlapping and adjacent to each
other. The bases of these bands show some tendency to align upon the triangular forms, though the band edges of some are too soft to see this alignment. A schematic view of the expected structure of the nanopillars is shown in Fig. 4(c). The conical and truncated pillar shape gives a decreasing tungsten density as the separation from the underlying tungsten substrate increases, until the AuPd layer is reached, where the tungsten density falls to zero. The contrast seen in the TEM image is modified from that expected using this simple model since the surface of the underlying tungsten is not quite flat. The effect of the non-flatness can be clearly seen in the contrast due to the AuPd grains, which now give rise to several bands rather than one single band. The various darker shapes between the AuPd layer and the underlying tungsten layer are due to the overlap between pillars of various heights. In summary, the TEM image indicates a pillar height of between 5 and 8 nm, which is slightly less than the value expected from unmasked etching under these conditions.
4. Conclusion The nanotriode fabrication process has been improved in order to increase inter-electrode breakdown voltages, reduce leakage currents and to reduce the effects of compressive strain in the deposited layers, which leads to mechanical failure of the structure. The modified process has yielded structures with up to five electrode layers, with
802
A.M. Blackburn et al. / Microelectronic Engineering 73–74 (2004) 797–802
good mechanical integrity and high inter-electrode isolation. The average height of the nanopillars has been characterised by TEM examination.
Acknowledgements The authors thank Simon Newcomb at the University of Limerick for the TEM examination of the nanopillars. A.M. Blackburn is grateful for financial support from EPSRC and an industrial CASE studentship from Hitachi.
References [1] A.A.G. Driskill-Smith, D.G. Hasko, H. Ahmed, Appl. Phys. Lett. 75 (1999) 2845. [2] A.A.G. Driskill-Smith, D.G. Hasko, H. Ahmed, J. Vac. Sci. Technol. B 18 (6) (2000) 3481. [3] A.M. Blackburn, D.G. Hasko, H. Ahmed, J. Vac. Sci. Technol. B 22 (2004), in press. [4] C.C. Fang, F. Jones, R.R. Kola, G.K. Celler, V. Prasad, J. Vac. Sci. Technol. B 11 (6) (1993) 2947. [5] T.A. Shankoff, E.A. Chandross, J. Electrochem. Soc. 122 (2) (1975) 295. [6] W. Chen, H. Ahmed, J. Vac. Sci. Technol. B 11 (1993) 2519.