Improved planar isolation with buried-channel MOS FET's

Microelectron. Reliab., Vol. 24, No. 3, pp. 555-577, 1984. Printed in Great Britain.

IMPROVED

PLANAR

0026-2714/8453.00 + .00 © Pergamon Press Ltd.

ISOLATION MOS

H. S U N A M I ,

Y. K A W A M O T O ,

WITH

FET

BURIED-CHANNEL

's

K. SHIMOHIGASHI,

and N. H A S H I M O T O

Central Research Laboratory, H I T A C H I LIMITED, Kokubunji, TOKYO

185,

JAPAN. (Received for publication 9th January 1984) ABSTRACT A potential graded-drain is

using

field-oxide

directional

implantation. and

channel

Fundamental

performances

parasitic

width

effects are

techniques and its

dry etching and through-

It features simultaneous channel

almost

are

and

an

to nominal one.

such as short-channel

investigated.

demonstrated

formation

stoppers

equivalent

device characteristics

narrow-channel

with planar isolation

This planar isolation approach has been

highly

punchthrough

effective

stopper)

BGP (buried-channel

in terms of fabrication

performance.

realized

M0S device called

with punchthrough

characterized

device

of

VLSI

Good

in devices having

and

isolation 1~m feature

size at standard 5V operation. I. INTRODUCTION

Four access

times

greater

memories(dRAM's),

densest

integration

integration

which always provides currently the

level,

years in the past decade. feature breakdown high dRAM' s

size

also

voltage

packing

respectively.

been

achieved every three

Along with the integration,

lowerings

of In

has

device

decreases causing constraints of variOus

density.

consist

of MOS dynamic random

and

Present 3~m-

this

and

difficulties

64Kb and near future 256Kb 2~m- feature

regard, device 555

in achieving

size

devices,

isolation as well as

556

H. SUNAMI,Y. KAWAMOTO,K. SH1MOHIGASHIand N. HASHIMOTO

active device is also of serious concern with respect to VLSI and

ULSI

isolations.

oxidation

of

feature

In

size

reduction

effects

resulting

sense,

traditional

local

silicon (LOCOS I)) will have a certain limit in

oxidation (bird's beak) These

this

below

an

due

to

lateral

and diffusion of channel-stop doping.

certainly

in

1.5 - 2~m

hinder

ultimate

closer

packing of devices

limit to integration in the near

future. Several

attempts 2-4)

detrimental they

effects

require

lopmental PLANAR,

have

caused

An

reported

to

by traditional LOCOS.

sophisticated

work.

been

processings

alternative

reduce However,

and a lot of deve-

isolation approach called

which is very similar to the direct moat isolation 5)

developed

by

compared

with

a concept

of

isolation

extensively used in 1960's, this has been improved

to and

Wang and his coworkers, has been characterized conventional this

LOCOS

approach

came

approach.

from

Although

traditional planar

great extent by the use of highly directional dry etching very

high-energy

ion-implantation

techniques.

It

features simultaneous formation of punchthrough and parasitic channel

stoppers

equivalent

to

and

the

an

effective

nominal

one,

formation

been reported

for isolation performance 6)

to

device

discusses

about

the

almost I.

This

two stoppers had previously

performance

scalability

width

as shown in Fig.

simultaneous

various

of

channel

of

This paper refers

and

new

processings

the

planar

isolation

and in

addition to the previous results 6)

II. FABRICATION PROCESS WITH PLANAR ISOLATION

In

place

of wet etching in traditional planar process,

a reactive

sputter etching using CF~+H 2 gas has been used to

delineate

thick

condition

realizes

field

oxide

pattern.

Ordinary

etching

a steep profile of the field oxide which

may result in difficulties in patterning of gate overlayed on the

stepped

field oxide.

A large vertical thickness of the

MOSFETs

557

[PHOTOMASK/ ~-

.

~

....

"

i

' r -

LIP/2

<

.

I

)

iLIP/2

~

\

____]

,

,~.

t

\

: ..,i~.:::,:~"::i ~:~.~.-':;:':,'_,:~L~'n''////z ~::"~:':~-~:".~:";':N •

. .

,

.

.

.

.

.

.

.

.

.

I LOcos_ I •

.~

/~'/Z**

I :"~i"i~"":':'~'i~':"'~!i'~ :~ 'I 5OLATIO We' NP "~''ITCH'I~P~;;":"' '''i' 'I LIP :~ Fig.

I

Periodical and

isolation

LOCOS.

effective

parasitic-channel effective

tively.

Cross section of LOCOS is moved

excess

half isolation

etching

overcome

regard,

tapered packing A poly-Si

on

resulting

ratio,

the

gate

oxide

microwave

to

horizontally

field oxide on the

substrate

gate etching

material

subsequent

is

to

oxide.

patternings.

tapered

To

excellent In this

to facilitate

may impede closer

enlarged

of thin

shorting.

requires

gate

preferred

various

profile

due to relatively

gate

gate

etching 5)

and

field

width, respec-

the field oxide side wall requires

in

problem

tapered

patterning

pitch to locate

field oxide

which possibly causes excess etching

this

rate

active-channel

pitch,

of that of PLANAR.

deposited

oxide

etch

length(actual

and

film

by PLANAR

Lip , Lpe , and Wef f are isolation

same position

gate

realized

width),

by

gate

structures

gate

However, field oxide

region.

plasma etcher 7) has been used to delineate

in this work.

This etcher

is characterized

by

558

H. SUNAMI,Y. KAWAMOTO,K. SHIMOHIGASHIand N. HASHIMOTO

microwave-enhanced

plasma

species

low energy

with

very

very

high etch rate ratio.

SiO 2

has

etching

been

condition.

patterning the

obtained

with

gate.

covering

generation

(less than 50V)

to

This

be

i~

greater

large

delineated

a field

oxide

Si

and resultant

are

observed

1.5~m

shown for

in

in

edges

of

c h a r a c t e r i s t i c s have shown no d e t r i m e n t a l

Silicon

gate stripes

oxide

1 I

overlayed

have been d e l i n e a t e d

2.

the

electrical

I

gate

width and

Fig.

In addition

0

to

strength of

on the

2

step.

make

overlayed

Fig.

field oxide

to

breakdown

gates

step

been

etching

than 50 in actual

enough

sufficient electrical

has

to

An etch rate ratio of poly-Si

The

irregularity

leading

No gate

to geometry, effect.

2pro !

on 800nm s t e p p e d

field

by m i c r o w a v e plasma e c t h -

ing 7) .

A. P r o c e s s Sequence The process isolation described (I)

is

sequence

for fabricating

presented

devices

in this section.

with

PLANAR

Key p r o c e s s e s are

as follows.

Field with 600nm

Oxide (100) thick

ventional, step.

Formation surface SiO 2.

field

: Silicon

are Being

oxidized

wafers

of

10ohm-cm

at I000°C.

to grow

different

implantation

with

the

is not operated

con-

in this

MOSFETs

(2) Field

Oxide Etching

559

: After delineating

AZ1350 photo-

resist thick field SiO 2 is etched by a reactive etch

using

50nm/min.

CH4+H 2 gas. An

Resultant

sputter

etch rate is around

etched depth of Si substrate

surface

is

less than 40nm. (3) Gate Oxide Formation mixed

solution

of

thermally oxidized (4) Boron

: After a NH4OH ,

profile

at

depth

and

channel

threshold

the

doped

poly-Si

resulting

ratio,

Si

with

to

at 0.1~m

the field oxide and the

This serves as the parasitic stopper 8)

Then, an to adjust

and to form buried-channel.

then

etching

dose of

are formed

: A 350nm thick poly-Si

plasma

is

Boron in-depth-

at 2x1011cm -2, 80keV is performed

voltage

and

depth under

and punchthrough

(5) Gate Formation LPCVD

to

is performed.

respectively.

stopper

As+-implant

and H20 the wafer

B2+-implant

in the Si substrate

0.65~m

gate oxide,

: A

130kV

peaks

H202,

at 80°C using

at I000°C to grow 2Onto SiO 2.

Implantation

1-2x1012cm -2

cleaning

with phosphorus. SF 6

gas 7)

in 100nm/min

SiO2,

is deposited

is

by

The microwave

used to etch the

etch rate.

An etch rate

is in excess of 50, as previously

mentioned. (6) Source is

and Drain Formation

performed

serves

as

sent 8)

which

to

: An As+-P + double

implant

form 0.36~m deep graded-drain.

source-to-drain is expected

breakdown

voltage

This

enhance-

for 2~m or less feature

size

MOS F ET 's. Subsequent performed

fabricate

MOS

devices

Si gate technology having

are no

process.

B. Dry Ecthing

M.R. 24/~-M

to

with well-established

sophisticated

Since

processes

dry

Damage Characterization etching

is performed

in plasma surrounded

by

H. SUNAMI,Y, KAWAMOTO,K. SHIMOHIGASHIand N. HASHIMOTO

560

10

& 5 u

0

I

l

I

1

0

5

10

15

t Fig.

3

Experimental capacitor

etching

it

C-t characteristics

is

contaminations

crystalline

defect

degradation

and

environment

susceptible

of

alkali

generation long-term

and

subsequent

substrate

surface

layer

quality.

A typical

isolation

process

means

inversion

an

current

is

result are

in

layer

however,

vicinity

than

that

of

carrier

lifetime

instability.

Clean

etching

etching

needed

to remove thin Si

to have good

in Fig. formation

layer.

3.

substrate

for the PLANAR

A recovery

which

time tf

is made by g-r

Even if a peculiar mound

in

region due to

a recovery time tf is long enough to low leakage.

10

this

stepped

at present.

sec

Values of tf obtained

for that of 2x1012cm -2.

behavior

resulting

generation.

clarified

heavy metals causing

from 9 to 15 min for a B implant of 1x1012cm -2,

concentration

center

implant,

less

speculated

and

possible damages,

from high concentration

sufficiently

ranging

to

C-t curve obtained

shown

in the depletion

deep boron

of 200~m [] MOS

and minority

wet

are

pulsed

C-t curve is originated the

(min)

with PLANAR isolation.

chamber,

i.e.,

pulsed

~.~

in

field However,

is caused

by increased

weak avalanche

breakdown

It is boron in the

oxide edge, not by enhanced this

speculation

g-r

is not yet

MOSFETs

561

III. DEVICE PERFORMANCE

Device

characteristics

regarding

are investigated

active and parasitic

in this chapter

FET's and compared

with LOCOS

devices.

A. Threshold

Voltage

Devices

Characteristics

fabricated

are buried

punchthrough

stopper

gate

For active devices,

oxide.

difference PLANAR,

in

as

the

shown

drain

AVTH-Le f f

VDD

in

a 0.43~m In Since the in

as a gate voltage

to

There

be

addition,

to

a disadvantage

back

standpoint.

bias

BGP

effects

shown

observed

in

Fig. 7.

by the fact that lateral

for

PLANAR

Fig.

8.

channel

in PLANAR.

diffusion

from

compared

width,

Weff,

under

This is

level)

narrow channel

or

The narrow channel oxidation

relation,

that

PLANAR

almost equivalent

effects

narrow channel effect is

of field oxide and

doping.

An offset ~W,

of -0.1~m

to that of 1.0~m for LOCOS,

implies

6.

to some extent

stopper.

A smaller

of channel-stop

the gm(max)-WG

This

is negative,

in deep region

is enhanced

effect,

caused

derived

a VTH

char-

lower than -5V in this case.

is

lateral

abnormal

from circuit operation margin

effect

the

of PLANAR are

to use VBB of 0V (ground

the short-channel

are

at 5V

are shown in Fig.

is formed

device

low voltage

Besides

no

dose of punchthrough

It is better

sufficiently

width devices

Although

stopper

a B of

Threshold

which induces a 10nA

exists

the back bias effect

response

and

works well at 5V operation.

a punchthrough channel,

device.

channel

also

LOCOS

is a deviation

characteristics

noticed.

Lef f device

obtained

(5~m gate length)

Subthreshold

Fig. 5.

acteristics

with

significant

between

A notation •VTH

I D for 10~m nominal

and -3V VBB.

shown

there is little

relation

in Fig. 4.

VTH is defined

current

graded-drain

(BGP) MOS devices 8) and have 20nm thick

of VTH from long channel voltage

channel

leads

is obtained as shown

in

to an effective

to the designed

width

H. SUNAMI,Y. KAWAMOTO,K. SHIMOFIIGASHIand N. HASHIMOTO

562

ff

- 0.2

/,vp

/H

0.58(PLANAR) 0.88(LOCOS)

ocos I

VDD = 5V VBB =-3V

-0.4

-0.6

0

1

2

3

4

Left

Fig. 4

Obtained VTH.

short-channel

VTH is defined

a drain

current

of

5

()Jm)

effect

on threshold voltage

as a gate voltage which induces 10nA

for

10~m nominal channel

width devices at 5V VDD and -3V VBB. is

a deviation

length)

device.

of

6

VTH

A notation ~VTH

from long channel

(5~m gate

MOSFETs

563

10-4 I (vDD = 5V kVBB -3V

!0 -6

Leff(~m! kg (~m)

0.43 10_8

1"3t

D

i0 -IC

10

-11 -I

0

VG

Fig. 5

Experimental devices Slopes

subthreshold

with of

greater than Io5~m. I

(V)

characteristics

PLANAR isolation.

70-75mV/decade

I

are

for active

Fdose = 2x1012cm "2. obtained

for

L G of

564

H. SUNAMI,Y. KAWAMOTO,K. SHIMOHIGASHIand N. HASHIMOTO

VBB

-

0 1.0 r

,

/

2 ,

,

4 ,

,

(V) 6 ,

8 ,

,

10 ,

12 , ....,

I

Fdose (cm -2)

LOCOS

0.6

-- ~ - ' " "

•,_,.

lx1012

.... ~ -

0.4

/"/

..,.

/ t

0.2 [PLANAR 0

] Lg

= 2)Jm

VDD = 5 V -

]D = 10nA

0.2

-0.4

0

1

2

J-VBB* 2J~'FJ - 2,]2"i-~FI

Fig. 6

Back

bias

3

( v ~2)

effects of active transistors

and LOCOS isolations.

with PLANAR

MOSFETs

565

1.2 VDD = 5V

1.0

VBB = -3V lD=10n l

Aw(jum) ~.

0.8

1Loc0sl

~ A

0.6 "-

I--

N

>

AR]

-0-

0.4

0.2

0

i

0

I,

I

i

2

I

4

I

i

Weff Fig. 7

Obtained width

narrow

is

evaluated

~10

(pro)

as (W G - A W ) .

by gm(max)

i

8

channel e f f e c t s .

defined

I

6

Effective

channel

The offset of AW is

vs W G relation

shown in Fig. 8.

50

Leff= 1.0~m 40

( VDD = 0.1V VBB: -3V

//

u3

='30

[P

E E 20

<"

/

~0

~i//°/ //

O

i

-

Fig.

8

/1~

I

LOCOSi

i

0 1 2 3 4 NOMINAL CHANNEL WIDTH, Wg

Effective

channel

width evaluation

by gm(max)

•

5 (~m) vs W G.

H. SUNAMI,Y. KAWAMOTO,K. SHIMOHIGASHIand N. HASH1MOTO

566

of the photomask. ranging

from

reduction

Maximum effective carrier mobility ~eff

520

to

540

cm2/Vs

in ~eff was observed

is not clarified

for

compared

PLANAR.

Around

to LOCOS.

is 10%

Its reason

yet at present.

B. Parasitic Device Characteristics Subthreshold shown

in

charcteristics

Figs. 9

respectively.

of

and 10 for poly-Si

Solid

and

parasitic

devices are

(Si)-gate

and Al-gate,

broken lines are those

for PLANAR

10 -4

VDD: 5V It

/ / //

Iiii

I'~lt

10 -6

10 -8

I-i

II/I

I lil/// I III

"-"

113 111

I,I

II II

/11II ~ II II

I '

'

10 -12

I

0

I II! I 10

, 20

vG Fig. 9

Subthreshold

leakage

currents

30 (v) for parasitic devices

with Si-gate of which cross-section Fig.

11.

Solid

LOCOS devices,

is illustrated

in

and broken lines are for PLANAR and

respectively.

MOSFETs

567

10-4 AI g a t e ~

.

VDD5V'/ = /

VBB=O 7

/

i

h.3 /

I I 11.5 /

•- "

!

00

I"

I //

/ 2/ 3/, I

/P /

I

,,/ /

I0-12

/

0

10

20 VG

Fig.

10

Subthreshold with in

30 (v)

leakage currents for parasitic devices

Al-gate of which cross-sections are illustrated Fig. 12.

Solid

and broken lines are for PLANAR

and LOCOS devices, respectively.

and will

LOCOS, respectively. be

shown

illustrate voltage

VG

a parameter. of

1.3pm,

indicating voltage

is

in

the

Figs.

drain

with

Cross-sections of these structures 12 and 13 later.

current

Figures 9 and 10

ID as a function of the gate

the nominal parasitic channel length Lp as

For Si-gate parasitic device of PLANAR with Lp a maximum good

leakage

current (I D) is less than IpA

isolation is obtained.

limited

When a power supply

to less than 4V, an Lp of even 1~m also

provides the good isolation performance.

H. SUNAMI,Y. KAWAMOTO,K. SHIMOHIOASH1and N. HASHIMOTO

568

PLANAR

LOCOS

~poly I

n,,. i

L

I

Si J

, tn

~-ff~J

~

Lpe

Lpe

30 Fdose(cm-2 )

.-.

5xi012

PLANAR I

>.F--

11x1012

10 VDD = 5V

VBB - 3V I D=10hA I

0

Fig.

11

I

I

I

I

1 2 3 4 5 EFFECTIVE PARASITIC CHANNEL LENGTH , Lpe ()Jm)

Threshold devices. around

voltage Measurable

23V

VTH P voltage

for

parasitic

is limited

due to catastrophic

20nm thick gate oxide overlayed

6

Si-gate

to less than

breakdown

of nominal

by parasitic

Si-gate.

MOSFETs

569

PLANAR

LOCOS /.; . b

I

J

Lpe

i °"

VDD= 5V VBB = -3V

6O

Fdose (cm-2)

I D :10nA

2 x1012

50

A

/

"-" 4 0

<

30

LOCOS

i5x1012

a...~--

_..--o

-I" 2O

,o

/ I

0

Fig.

12

[PLANARI I

I

I

I

1 2 3 4 5 EFFECTIVE PARASITIC-CHANNEL LENGTH , Lpe (~m) Threshold

voltage

VTH P

for

6

parasitic

Al-gate

devices.

However, lead

to

Fig.

10.

An

the Figs.

Lp

to

some

current

parasitic 11

of

low

leakage

greater

than

isolation performance.

reduced

leakage

A1 gate of PLANAR, an Lp of 1.3~m can not

sufficiently

desirable is

for

and

extent,

12.

A

leakage

I. 5~m

is

as

shown

in

required

for

If a depth of graded drain

significant

would be expected. channel

current,

decrease

in the

Experimental results of

current

are

summarized

in

notation of VTH P is defined as a gate

H. SUNAMI, Y. KAWAMOTO,K. SFI1MOHIGASHIand N. HASHIMOTO

570

voltage

which

Being

somewhat

effective length as

of

tion

stop

channel

in Figs.

doping deep

of 10hA.

nomenclature,

length Lpe indicates

is

an

the physical

not the source-to-drain

spacing,

One fifth the field implanta-

This is because

LOCOS

current

usual

in PLANAR performance

devices. of

the

11 and 12.

results

gate

however,

to

the field oxide,

dose Si

a leakage (drain)

different

parasitic

shown

for

induces

to LOCOS

that most of channel

incorporated

through-field-oxide

equivalent

in the field oxide,

implant mostly remains

in

the substrate.

C. Substrate Current Experimental shown

in

Fig.

13

channel

length

current

consists

key

parameters

hot

carrier

loading value

defined

difference result

of

from

devices

the effective

hot electon-hole

pairs, this is one of

be taken into consideration 9) concerning latch

up

phenomena

on-chip VBB generator. IBB(max)

as

are shown in Fig. between

IBB(max) that

with

are

Since the substrate

as

difference

IBB characteristics

a parameter.

immunity I0) , of

current

PLANAR as

of to

characteristics notable

for

Lef f

effect is

substrate

for

If a maximum

a function

14.

LOCOS

in CMOS, and

V G , IBB

There has not existed

and

Fdose

of

IBB

PLANAR.

A

slight

of I and 2x1012cm -2 may

of magnitude of electric

field near drain

causing weak avalanche multiplication.

D. Source to Drain Breakdown The of

minimum

source-to-drain

PLANAR is slightly inferior

Fig.

15.

the

field

high

This

feature

oxide

edges.

Accompanying sizes

to that of LOCOS,

would be due to higher Though, these

enough with 5 V operation

0.5~m.

breakdown voltage

device

BVDS(min)

as shown in

B concentration BVDs(min)

values are

in an Lef f range greater down-scaling,

along

devices

than with

1.5~m and below would be difficult to stand up

MOSFETs

10-5 I_

571

~

"

LeffC~m-)

i

~

.o.96.

10-~ "

1.L,6 \ \ C~.5

10_9 _

10-~1

VDD : 5 V

3.._99

VBB=OV

5

I

-1

0

2

4

vG

Fig. 13

Substrate devices

current

with

IBB

6

(v)

characteristics

PLANAR isolation.

is defined as IBB(max).

8

for active

A peak value of IBB

H. SUNAMI,Y. KAWAMOTO,K, SHIMOHIGASHIand N. HASHIMOTO

572

5

ILocosl 10 -5

(I012cm-2)

_

×

LANAR

£ CD 2 10_ 6

5

(VDD = 5V VBB=0V , , i,l

0.5

~'~,., 'k~'#k,k~ ,

I

14

IBB(max)

vs.

,

,

I 5

L~ff Fig.

J

, , ,, 10

(~m)

effective channel length curves

MOSFETs

573

/I

12 / /

JUNCTION

TyPE /II LOCOSl

""

PHO.S/

//

10.

///

/~

Fdose=2x102cm-2

/

8

COS I m

6-

/

! 5

I 1

0

Fig.

15

Minimum

i 2

source

to

i 3

i 4

Left

Oum)

drain

breakdown

5

voltage char-

acteristics.

to

5V

operation

devices as

to

tolerable

LDD 11)

been

for

to 5V operation,

are needed

the industrial continue

voltage

in

conventional

similar

future,

in

capacitances

attempts

because

breakdown

such

A 5V voltage has

change of power

supply

by many users.

voltages

of

200~m Q n+-p junctions

by PLANAR field oxide are 23 and 29V for Fdose of

2 and 1x1012cm -2, respectively. found

innovative

Performance

Obtained surrounded

small

for a long time and is required

will hardly be accepted

E. Junction

To make

to this BGP.

standard

the

devices.

low

leakage

simultaneously

No notable behavior

current measured

regime.

The

has been junction

for these devices

are

574

H. SUNAMI,Y. KAWAMOTO,K. SHIMOHIGASHIand N. HASHIMOTO

51.0

and

33.8 ~F/cm 2,

capacitance

sacrifices

capacitance

value,

parasitic

respectively.

As increased

junction

the circuit speed in response

smaller

to the

Fdose is preferrable as long as

channel leakage is sufficiently

suppressed.

5O v

30

"~"

v

CL -II--

10

>

0

I

I

I

I

0.3 .-.

\

> 0.2

\

\

I.-.~

0.1 &VTH= VTH(LIp) - VTH ( k l p = 1 6 p m )

0 3

E

2

• I

0

i

0

Fig.

16

Comparison to

i

1 2 3 ]SOLATION PITCH, LIp

4

5 (jJm)

of PLANAR and LOCOS devices with respect

threshold voltage VTH P of parasitic device,

channel

effects,

and effective channel

short

width Weff.

MOSFETs

575

IV. DISCUSSION Thus, LOCOS Fig.

device

with respect 16.

for

repetitive region

generated

tion

would be formed

for

pitch

with

doubled the

packing

In addition, than

the

density is

of LOCOS.

in LOCOS by field

innovative

attempts 2-4)

possible

field

zero

2tim isolation

pitch,

with acceptable

isola-

1tim Wef f. can

In other words,

be realized

by PLANAR

roughly proportional

to the

effect of PLANAR is more

An o f f s e t A W

offset

can be reduced

and pad oxides'

However,

crystallographic

oxide,

1tim has been

pitch.

some extent

to

effective

In this case LOCOS needs 3tim

the narrow-channel

that

an

about

of

same

density

as shown in

are of the same size

of

a case

PLANAR.

packing

square of isolation

gentle

devices,

as of almost the same size

offset

In

for PLANAR and

stripes,

1tim can be obtained

performance

since

an

LOCOS.

around

isolation

isolation

Though,

for

of

almost

active and parasitic

field

photomask.

a Wef f

are compared

If line and space on photomask

isolation of

performances

considering

defect seems

thinning

and/or

the immunity

generation

considerably

to

along the

difficult

to

realize. Meanwhile, enhanced shown

parasitic

in

Fig.

considerably penetration fore,

a notable

in

10,

leakage

for Al-gate

Al-gate

inferior of

disadvantage

that

n+-junction

actual

of

device LOCOS

underneath

LSI layout,

overlaying

on

is

an

device.

As

of PLANAR is to

deeper

field oxide.

There-

due

some design rules to reduce the

effect have to be taken into consideration. electrode

PLANAR

parasitic

parasitic

to

of

periodical

For instance,

n+-layer- field

oxide

patterns

with

a minimum

to

rule

an Lp of 0.5flm-a Wef f of 1.5~m pitch would be

this

better

to

be

and requirement

M.R, 2413--N

designed

pitch has to be avoided.

AI

to satisfy an isolation

to Al-gate

parasitic

device

According

pitch of 2~m

performance.

576

H. SUNAMI,Y. KAWAMOTO,K. SHIMOHIGASHIand N. HASHIMOTO

V. SUMMARY

In summary, a desirable

capability

performances limited

by

performance

with ~t 1~m effective

encountered to

be

by

patterning

planarization

a

serious

of several

step compared

PLANAR

era when

reduction

voltage

isolation

which

will

be

with PLANAR is likely on relatively

A slightly

underneath

present,

more

the

improved

pitch is hin-

field oxide at 5V possible

and operating

promising

supply voltage

with the the geometry

for PLANAR even

in PLANAR isolation

device geometries

power

As

is needed.

at

make

problems

to LOCOS.

power

in

isolation

to LOCOS.

layers overlaying

flowing

reductions

contrary

is

width.

dered by leakage current supply

area reduction

electrical

ULSI fabrication

technique

Because

by

has

with electrical

pitch is attainable

most

in actual

but

An

circuitry,

channel

the

high field-oxide

LOCOS.

patterning

required

of

area reduction

to

a 2~m isolation

One

shown that PLANAR isolation

for

equivalent

not

a result,

it has been

in

overall

voltages

will

the coming

ULSI

will possibly be reduced

along

reduction.

REFERENCES I)

E. Kooi, chem.

2)

Soc.

Appels,

J. Electro-

K. Hirata,

Y. Yoriume,

1117 (1976).

Phys., 20,

T. Chiu,

Electron

K. Y. Chiu,

and J. A.

K. Imai, K. Kikuchi,

J. Appl.

J. C. Hui, Trans.

4)

123,

K. Minegishi, Japan.

3)

J. G. van Lierop,

Supplement

S. S. Wong,

Devices,

ED-29,

20-I,

51 (1981).

and W. G. Oldham,

IEEE

554 (1982).

J. L. Moll, and J. Manoliu,

ibid,

ED-29,

536

(1982). 5)

K. L. Wang, and P. Yang,

6)

S. A. Saller, ibid,

K. H. Christie Devices

Meeting,

and

ED-29,

W. R. Hunter, 541

P. K. Chatterjee,

(1982).

W. S. Johnson,International

Dig. Tech.

Papers,

464 (1973).

Electron

MOSFETs

7)

8)

K. Suzuki,

S. Okudaira,

I. Kanomata,

J. Electrochem.

H. Sunami,

K. Shimohigashi,

Trans. 9)

Electron Devices,

E. Takeda,

577

S. Nishimatsu,

K. Usami,

and

Soc. 129, 2764 (1982). and

N.

Hashimoto,

IEEE

ED-29, 607 (1982).

H. Kume, T. Toyabe, and S. Asai, ibid, ED-29,

611 (1982). 10)

T. C. May and M. H. Woods, ibid, ED-26, 2 (1979).

11)

S. Ogura,

P. J. Tsang,

W. W. Walker,

D. L. Critchlow,

and J. F. Shepard, ibid, ED-27, 1359 (1980).