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Improving the electrical and hysteresis performance of amorphous igzo thin-film transistors using co-sputtered zirconium silicon oxide gate dielectrics
Materials Science in Semiconductor Processing 67 (2017) 84–91
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Improving the electrical and hysteresis performance of amorphous igzo thinfilm transistors using co-sputtered zirconium silicon oxide gate dielectrics
MARK
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Chien-Hsiung Hunga, Shui-Jinn Wanga,b, , Pang-Yi Liua, Chien-Hung Wuc, Hao-Ping Yana, Nai-Sheng Wua, Tseng-Hsing Lina a b c
Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan Advanced Optoelectronic Technology Center, National Cheng Kung University, Tainan 701, Taiwan Department of Electronics Engineering, Chung Hua University, Hsinchu 300, Taiwan
A R T I C L E I N F O
A B S T R A C T
Keywords: Indium gallium zinc oxide Co-sputtering, high-κ dielectric Thin-film transistor Zirconium silicon oxide Interface trap density
The use of co-sputtered Zirconium Silicon Oxide (ZrxSi1−xO2) gate dielectrics to improve the performance of αIGZO TFT is demonstrated. Through modulating the sputtering power of the SiO2 and ZrO2 targets, the control of dielectric constant in a range of 6.9–31.6 is shown. Prevention of polycrystalline formation of the ZrxSi1−xO2 film up to 600 °C annealing and its effectiveness in reducing leakage currents and interface trap density are presented. Moreover, it is revealed that the Zr0.85Si0.15O2 dielectric could lead to significantly improved TFT performance in terms of subthreshold swing (SS=81 mV/dec), field-effect mobility (μFE=51.7 cm2/Vs), and threshold voltage shift (ΔVTH=0.03 V).
1. Introduction Although amorphous indium-gallium-zinc-oxide (α-IGZO) thin-film transistors (TFTs) with superior performance compared with amorphous silicon-based TFTs have been demonstrated [1,2], continuous efforts are still required to further improve the electrical properties for advanced display applications. For next-generation displays, α-IGZO TFTs have obtained considerable attention due to their high mobility, excellent uniformity, low cost, and room temperature process. [3–8] These advantages render α-IGZO a promising material in the display industry, such as for flat panel displays, liquid crystal displays, activematrix organic light-emitting diode displays [9,10], and flexible displays [11,12]. In advancing the performance of α-IGZO TFTs, such as for the field-effect, mobility, and reduced gate leakage current, other alternative high-κ dielectrics for α-IGZO TFTs have been reported [13–15]. The trap density at the high-κ dielectrics/α-IGZO channel interface is large because the α-IGZO channel and high-κ dielectric films have abundant oxygen vacancies and enormous trap densities, respectively [16–19]. As a result, α-IGZO TFTs with a high interface trap density (Dit) at the high-κ dielectrics/α-IGZO channel interface usually suffer from inferior performance due to a high gate leakage current, poor subthreshold swing (SS), and low field-effect mobility (μFE) [20–25]. In recent years, various techniques have been reported for improving the defect issues regarding the high-κ dielectric/α-IGZO channel interface,
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including the use of a more suitable dielectric [11], modifying the device structure [26], surface treatment of the active layer [27], and fabrication of the dielectric via the co-sputtering technique [28]. The advantage of the co-sputtering technique lies in the ability of the compound materials to be simultaneously deposited by multi-targets at room temperature. In this manner, suitable dielectric constants and gate dielectric compositions can be controlled through modulation of the cosputtering power ratio. Recently, reductions in the trap densities for the gate dielectrics of α-IGZO TFTs via the co-sputtering technique have been demonstrated [28,29]. Chen et al. and Song et al. developed αIGZO TFTs with co-sputtered Sm2TiO2 and NbLaO dielectrics to reduce the interface state density at the dielectric/α-IGZO channel interface [28,29]. Their experimental results suggested that the electrical performance could be improved via a suitable co-sputtering power ratio. In this study, to the best of the authors’ knowledge, the use of cosputtered zirconium silicon oxide (ZrxSi1−xO2) dielectrics to improve both the μFE and SS of the α-IGZO TFT is demonstrated for the first time. It is expected that the ZrxSi1−xO2 dielectric could offer a good compromise between the field-effect (dielectric constant) and gate leakage current, because silicon dioxide (SiO2) has the widest bandgap and lowest defect density while zirconium dioxide (ZrO2) provides a much better interface with α-IGZO in comparison with hafnium oxide (HfO2) [30–32]. S. Dueñas et al. and J. C. Park et al. reported that HfO2 dielectric or HfO2/α-IGZO might have a higher trap density at the interface with IGZO channel as compared with the case with ZrO2 or
Corresponding author at: Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan. E-mail address: [email protected] (S.-J. Wang).
http://dx.doi.org/10.1016/j.mssp.2017.05.017 Received 12 December 2016; Received in revised form 23 April 2017; Accepted 10 May 2017 1369-8001/ © 2017 Elsevier Ltd. All rights reserved.
Materials Science in Semiconductor Processing 67 (2017) 84–91
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Fig. 1. Schematics of the α-IGZO TFTs with ZrxSi1−xO2 dielectrics.
ZrO2/α-IGZO interface. It results in an inferior performance of α-IGZO TFTs with HfO2 gate dielectric [30,31]. In addition, N.P. Maity et al. revealed that the MOS device with ZrO2 insulator shows lower Dit than the case with HfO2 insulator [32]. ZrO2 dielectric is expected to provide a better property of interface for IGZO TFT or MOS device. The optimal radio frequency (RF) power ratio for the co-sputtering of the ZrO2 and SiO2 targets at room temperature to maximize the role of the ZrxSi1−xO2 dielectrics is investigated. Experimental study into the suitable RF power ratio (ZrO2:SiO2) to yield ZrxSi1−xO2 dielectrics with good immunity to polycrystalline formation at temperatures up to 600 °C is conducted. In addition, the effects of post deposition annealing (PDA) on device performance, especially on the hysteresis characteristic, are also investigated.
200-nm-thick Titanium (Ti) layer was deposited by electron-beam evaporation as the source and drain contact electrodes. The channel length and width of the TFTs are 20 and 200 µm, respectively. During the fabrication of IGZO TFTs, metal–insulator–metal (M-I-M) capacitors were also prepared to investigate the dielectric constant and leakage characteristic of the gate dielectric. The devices were characterized under open air condition at room temperature using a Keithley 2636A semiconductor parameter analyzer and an HP4284A precision LCR meter, and the material properties were analyzed by X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) using an PHI 5000 Versa Probe and Rigaku D/MAX2500, respectively.
2. Experimental procedure
Fig. 2(a) shows the XPS survey of the ZrxSi1−xO2 films as a function of the co-sputtering power ratio of ZrO2 and SiO2. The atomic ratio shown in Fig. 2(b) was calculated from the XPS survey by the XPS system. Note that the RF sputtering power of the SiO2 target was modulated from 0 to 150 W while the power of the ZrO2 target was kept at 100 W. It indicates that although the atomic ratio of silicon was increased via increasing the co-sputtering power ratio, the atomic ratio of oxygen was almost constant (about 70%). According to the XPS analysis results, the co-sputtered ZrxSi1−xO2 could be defined as ZrO2, Zr0.85Si0.15O2, Zr0.45Si0.55O2, and Zr0.2Si0.8O2 for the SiO2 sputtering powers of 0, 50, 100, and 150 W, respectively. In Fig. 3(a), the peak position of the Zr 3d5/2 spectrum for ZrO2 film appears at 182 eV, which is consistent with the ideal value from the NIST database. In addition, the Zr 3d5/2 peak shifts to lower binding energy for the Zr0.85Si0.15O2 gate dielectric film, which should result
3. Results and discussion
A cross-sectional schematic of the proposed α-IGZO TFTs with cosputtered ZrxSi1−xO2 is shown in Fig. 1. A 10-nm-EOT (equivalent oxide thickness) ZrxSi1−xO2 layer was deposited as the gate dielectric on heavy-doped n-type silicon (n+-Si) substrate through RF co-sputtering of the 3-in ZrO2 (purity of 99.99%) and SiO2 (purity of 99.99%) targets under O2 ambient (purity of 99.99%) at room temperature. RF power ratios (ZrO2 (W):SiO2 (W)) of 100:0, 100:50, 100:100 and 100:150 were used for the co-sputtering processes, which was followed by furnace annealing under O2 ambient (purity of 99.99%) at 600 °C for 10 min. The 25-nm-thick α-IGZO channel layer was deposited by RF sputtering using an 3-in IGZO target (In2O3:Ga2O3:ZnO=1:1:1, and purity of 99.99%) under Ar ambient (purity of 99.99%). Note that the working pressure of all RF sputtering processes was kept at 10 mTorr. Finally, a
Fig. 2. (a) The XPS survey of the ZrxSi1−xO2 films. (b) Atomic ratio of ZrxSi1−xO2 as a function of the co-sputtering ratio of ZrO2 and SiO2.
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Fig. 3. The (a) Zr 3d and (b) Si 2p XPS spectra of ZrxSi1−xO2 films.
increased to 55% and 80%, respectively, which should be also due to the increase in oxygen vacancy in the gate dielectric. Fig. 4 shows the O 1s XPS spectra of ZrxSi1−xO2 films. The O 1s spectra can be deconvoluted into three different peaks, which are assigned as follows: the “lattice oxygen peak without oxygen vacancies” 530 eV, the “lattice oxygen peak in the oxygen-deficient region” 531.1 eV, and a metal hydroxide peak” (531.9 eV) [34]. It can be clearly seen that the relative area of the oxygen vacancy-related peak at 531.1 eV decreased with increasing Si content in the ZrxSi1−xO2 film. The values are 26.46%, 21.09%, 30.14% and 39.74% for the ZrO2,
from the suppression of oxygen vacancy by the Si incorporation. The reduction in the positively charged oxygen vacancies results in a decrease in the electric field, thus leading to a shift the Zr 3d5/2 peak to a lower binding energy [33]. However, for the Zr0.45Si0.55O2 and Zr0.2Si0.8O2 gate dielectric films, a different situation is seen. On the contrary, the increase in oxygen vacancies in gate dielectric with excess Si incorporation causes an increase in the binding energy. In Fig. 3(b), with the peak of Si 2p spectrum (101.8 eV) of the Zr0.85Si0.15O2 case as a reference, the peak position of the Si 2p spectrum for ZrxSi1−xO2 shows a positive energy shift of 0.2 and 1.1 eV as Si content was
Fig. 4. The O 1s XPS spectra of ZrxSi1−xO2 films.
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Fig. 5. XRD analysis of the co-sputtered ZrxSi1−xO2 films at various annealing temperatures.
Zr0.85Si0.15O2, Zr0.45Si0.55O2, and Zr0.2Si0.8O2 films, respectively. The results indicates that a suitable co-sputtered power ratio of ZrO2 and SiO2 could decrease the trap density of ZrxSi1−xO2, but higher cosputtered power could possibly incur plasma damage on the surface. In this study, the RF sputtering power of the SiO2 target was modulated from 0 to 150 W while the power of the ZrO2 target was kept at 100 W. The XPS results indicate that the trap density increases through increasing the sputtering power of the SiO2 upon 100 W, suggesting that the high sputtering power could possibly cause plasma damage and increase the trap density on the gate dielectric surface. Note that the relative area of the metal hydroxide peak at 531.9 eV was increased with increasing Si incorporation in the ZrxSi1−xO2 films except Zr0.85Si0.15O2. It suggests that the OH-impurities from the ambient atmosphere might be preferentially adsorbed on the surface of ZrxSi1−xO2 with high sputtering power of SiO2, which can be attributed to the high trap density on surface caused by the plasma damage. Fig. 5 shows the XRD analysis results for ZrxSi1−xO2 with different co-sputtering power ratios. It can be seen that for the co-sputtered ZrxSi1−xO2 dielectrics with Si/(Si+Zr) ratio, more than 15% still remains in an amorphous-like structure even after PDA up to 600 °C under O2 ambient. However, the ZrO2 film appears to be a polycrystalline structure after the 600 °C PDA, which is likely to incur leakage current under a gate bias and thereby deteriorate device performance. It could be attributed to the transition temperature of ZrxSi1−xO2 gate dielectrics is higher than that of the ZrO2 film with dopant [35]. Our results suggest that the co-sputtered ZrxSi1−xO2 layer with a suitable composition could suppress the high-temperature annealing crystallization process. The oxide capacitance and dielectric constant were measured and evaluated from a metal/insulator/metal (M-I-M) structure of n+-Si/ ZrxSi1−xO2/Ti. For a fair comparison in device performance, the same EOT of dielectric of 10 nm (corresponding to Cox≈3.1×10−7 F/cm2) was used in experiments. Fig. 6 (inset) shows the C-V characteristic of n+-Si/Zr0.85Si0.15O2/Ti capacitor through PDA process at 600 °C for
Fig. 6. Dielectric constant and Si/(Si+Zr) ratio of the ZrxSi1−xO2 films as a function of the co-sputtering ratio of ZrO2 and SiO2. (inset) The C-V characteristic of n+-Si/ Zr0.85Si0.15O2/Ti capacitor.
10 min under O2 ambient. The dielectric constant of the ZrxSi1−xO2 dielectrics were 31.6, 22.8, 12.3, and 6.9 via 600 °C PDA process for the samples prepared with the Si/(Si+Zr) ratios of 0% (ZrO2), 15% (Zr0.85Si0.15O2), 55% (Zr0.45Si0.55O2), and 80% (Zr0.2Si0.8O2), respectively. The dependence on the dielectric constant and Si/(Si+Zr) ratio for the ZrxSi1−xO2 films with the co-sputtering power ratio of ZrO2 and SiO2 is shown in Fig. 4, which indicates that the dielectric constant of the ZrxSi1−xO2 dielectrics could be well controlled through the cosputtering power ratio of ZrO2 and SiO2. Note that the ZrO2 with 600 °C PDA shows the higher dielectric constant of 31.6 than the conventional case of 25, it could be attributed that ZrO2 with 600 °C PDA has a cubic phase as confirmed XRD analysis. In essential, the dielectric constant of ZrO2 can be enhanced with improved crystallinity [36,37]. The AFM surface-roughness analysis of the prepared ZrO2 and ZrxSi1−xO2 dielectrics are listed in Table 1. Typical surface roughness 87
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Table 1 Comparison of device performance characteristics for the α-IGZO TFTs with ZrxSi1−xO2 dielectrics. Devices
VTH (V)
μFE (cm2 V−1 s−1)
SS (V/dec)
Ion/Ioff
Dit (cm−2 eV−1)
ΔVTH (V)
Surface Roughness (nm)
ZrO2 Zr0.85Si0.15O2 Zr0.45Si0.55O2 Zr0.2Si0.8O2 [29]a) [39]b) [60]c) [61]d) [62]e)
1.25 0.45 0.53 0.22 1.84 3.5 12.9 0.7 2.8
31.79 51.70 27.21 9.70 28.00 30.90 24.50 13.70 12.90
0.111 0.081 0.116 0.152 0.170 0.170 ~1.5 0.380 0.090
1.05×107 1.24×108 1.47×107 1.08×105 5.30×107 2.00×106 6.10×107 109 109
1.85×1012 7.70×1011 2.03×1012 3.33×1012 3.00×1012 2.60×1012 – – –
0.52 0.03 0.57 0.79 −0.07 0.80 – – –
2.40 0.16 0.17 0.18 – – – – –
Note: IGZO TFT with a) co-sputtered NbLaO dielectric, b) co-sputtered TaLaO dielectric, c) thermally growth SiO2 dielectric, d) SiNx dielectric (PECVD), and e) sputtered Al2O3 dielectric.
should be due to the lowest trap density at the channel/dielectric interface. The transfer characteristics of the α-IGZO TFTs with ZrO2 and ZrxSi1−xO2 dielectrics prepared under different co-sputtering power ratios with the PDA are shown in Fig. 9, with the extracted device electrical parameters listed in Table 1. Our results reveal that the αIGZO TFTs with Zr0.85Si0.15O2 had the best properties with the highest on-off current ratio (Ion/Ioff) of 1.24×108, lowest SS of 81 mV/dec, highest μFE of 51.70 cm2 V−1 s−1, and lowest Dit of 7.05×1011 cm−2 eV−1. The μFE induced from transconductance (gm ) measurement at a low drain voltage VDS=0.1 V was determined as following Eq. (1):
μFE =
+
Lgm WCox VDS
(1)
where Cox and gm are the gate capacitance density and transconductance, respectively. Note that the κ-IGZO TFT with Zr0.85Si0.15O2 gate dielectric shows the best performance of μFE, the Cox and gm are 3.12×10−7 F/cm2 and 1.613×10−5 (A/V), respectively. The improved μFE and Ion/Ioff performances are mainly ascribed to the proposed ZrxSi1−xO2 dielectrics having an amorphous-like structure and good dielectric/channel interface, which suppresses gate leakage current. Of note, the sample with the Zr0.85Si0.15O2 dielectric exhibited the best gate control capability (lowest SS of 81 mV/dec), which could be attributed to a considerable suppression in trap density through a suitable SiO2 insertion in the Zr0.85Si0.15O2 film. To clarify the dependence on the Dit and TFT performance, the values of Dit at the interface of the ZrO2/α-IGZO and ZrxSi1−xO2/α-IGZO structures were extracted from the capacitance-voltage measurement and SS values. Note that Dit was evaluated by the following Eq. (2):
+
Fig. 7. Leakage current properties of the n -Si/ZrO2/Ti and n -Si/ZrxSi1−xO2/Ti capacitors.
values of the co-sputtered Zr0.85Si0.15O2 films range from 0.16 to 0.18 nm, while that of the ZrO2 film is about 2.4 nm. This indicates that the surface of the co-sputtered ZrxSi1−xO2 films is much smoother than that of the ZrO2 layer, which is mainly attributed to the ZrxSi1−xO2 films being immune from polycrystalline structure formation; by contrast, grain growth in the ZrO2 film leads to a rougher surface [38], which is consistent with results of the XRD analysis. Fig. 7 shows the leakage current properties of the n+-Si/ZrO2/Ti and n+-Si/ZrxSi1−xO2/Ti capacitors. Note that the thickness of each dielectric layer was scaled to have the same EOT of 10 nm. It can be seen that the cases with Zr0.85Si0.15O2 and Zr0.45Si0.55O2 insulator both have a lower current density than that of with the ZrO2 layer. The ZrO2 and ZrxSi1−xO2 XRD analysis results shown in Fig. 5 reveal that the amorphous-like structure of ZrxSi1−xO2 remains intact, even after thermal annealing at temperatures up to 600 °C; in comparison, ZrO2 shows a polycrystalline structure without thermal annealing. Moreover, the abundant grain boundaries in a polycrystalline structure dielectric inevitably increase the probability of carrier transport and leakage current [39]. The measured leakage current densities shown in the figure indicate that, with a suitable composition, the co-sputtered ZrxSi1−xO2 layer could be used as a suitable gate dielectric for α-IGZO TFTs. Note that the case with Zr0.2Si0.8O2 has a higher leakage current which could be due to it has a higher trap density [40]. Based on O 1s XPS spectra of the Zr0.2Si0.8O2 gate dielectric, the film shows the highest oxygen vacancies density than other samples. The result could be attributed to the increase in the composition of SiO2 in the ZrxSi1−xO2 gate have consumed a considerable amount of oxygen and the occurrence of plasma-related damages. Fig. 8 shows the output characteristics of α-IGZO TFTs with ZrxSi1−xO2 gate dielectrics. Enhancement mode behaviours with good saturation characteristics were observed with a low operation voltage of 4 V. It can be seen that the α-IGZO TFT with Zr0.85Si0.15O2 gate dielectric shows the highest drain current at saturation region, which
SS ≈
⎛ qDit ⎞ kT ln (10) ⎜1 + ⎟ ⎝ q Cox ⎠
(2)
where k is Boltzmann's constant and Cox is the gate insulator capacitance [41]. Many studies reported that both the TFT performances of SS and μFE are considerably degraded by a high Dit, which suppresses gate control capability [42–44]. In general, SS might be an indicator of the Dit value at the dielectric/channel interface. In our experiments, the αIGZO TFT with the Zr0.85Si0.15O2 dielectric shows an excellent SS of 81 mV/dec with the lowest Dit of 7.70×1011 cm−2 eV−1, which is about one third of that in the α-IGZO TFT with ZrO2 gate dielectric. Accordingly, these results suggest that the Dit of the ZrxSi1−xO2/α-IGZO interface can be substantially decreased through a suitable co-sputtered power ratio. To further confirm the effectiveness of the proposed Zr1−xSixO2 dielectric layers, the hysteresis characteristics of the α-IGZO TFTs with the ZrO2 and ZrxSi1−xO2 dielectrics after PDA at 600 °C for 10 min under O2 ambient were examined, as shown in Fig. 10. Essentially, the hysteresis performance of the α-IGZO TFT might be affected by a number of factors, including carrier trapping in the gate dielectric/ channel interface [45–49], oxygen vacancies on the surface of high-κ dielectric and α-IGZO channel [50–54], and/or the donor like defects in 88
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Fig. 8. The output characteristics of α-IGZO TFTs with ZrxSi1−xO2 gate dielectrics.
suitable co-sputtering power for ZrO2 and SiO2. It is expected that, with an optimized ZrxSi1−xO2 layer to further suppress Dit, advanced α-IGZO FETs with reduced gate leakage current, enhanced SS, and improved hysteresis characteristics can be realized. Fig. 11 shows the transfer characteristic of α-IGZO TFTs with Zr0.85Si0.15O2 gate dielectric after bias stress. The bias stress condition is VGS= ± 4 V for a maximum time period of 1000 s. The threshold voltage shift (ΔVTH) of the device under positive bias stress (PBS) and negative bias stress (NBS) conditions is investigated as a function of stress time, as shown in Fig. 12. Our results indicate that PBS and NBS lead to a positive and negative ΔVTH, respectively. It could be attributed to excess electrons are accumulated and captured by oxygen molecules in the α-IGZO channel under PBS, as a result, buildup of negative charge (O2-) causes a positive VTH shift [55,56]. While under NBS, the adsorbed moisture from the atmosphere might change into positively charged species (H2O+) in the α-IGZO channel. Hence the accumulation of H2O+ thus leads to a negative VTH shift [56]. Similar explanations were reported in the literature [55–59]. Fig. 13 shows the dependence of the interface trap density Dit on the Si/(Zr+Si) ratio of ZrxSi1−xO2 gate dielectric. It reveals that, as the Si/ (Zr+Si) ratio was increased from 0% to 80%, the interface trap density Dit decreases at the initial stage, reaches a minimum value at around 15% and then increase. Based on the fact that trap density at SiO2/αIGZO interface is much less than that at ZrO2/α-IGZO interface [32], the increase of SiO2 content in the ZrxSi1−xO2 gate dielectric might be responsible for the suppression of Dit in the experiment. However, a higher sputtering power was needed to increase the SiO2 content, which would cause plasma-related damages at around interface. Accordingly, a tread-off between the decrease in Dit and increase in plasma-related
Fig. 9. Transfer characteristics of the α-IGZO TFTs with ZrxSi1−xO2 gate dielectrics.
the α-IGZO channel [50–53]. When the gate voltage (VGS) was swept from −1 V to 4 V, it was found that the threshold voltage shifts (ΔVTH) of the α-IGZO TFTs with ZrxSi1−xO2 dielectric layers were much smaller than those measured from the device with the ZrO2 dielectric layer. Note that the α-IGZO TFT with Zr0.85Si0.15O2 after PDA had the lowest ΔVTH of 0.03 V among all prepared devices. The difference in ΔVTH can be explained by the degrees of electron trapping in the dielectric/αIGZO channel interface. The amount of electrons that can be repeatedly trapped and released depends on the applied voltage, which is proportional to the magnitude of Dit. As compared with a conventional ZrO2 dielectric layer, our experimental results indicate that the Dit at the ZrxSi1−xO2/α-IGZO interface can be considerably reduced by a 89
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Fig. 10. Hysteresis characteristics of the α-IGZO TFTs with ZrxSi1−xO2 gate dielectrics.
prepared at a power ratio of ZrO2:SiO2=100 W:50 W allows the amorphous-like structure and smooth surface to be retained even after PDA at 600 °C, which is very beneficial for reducing gate leakage current. Experimental results revealed that α-IGZO TFT with the proposed Zr0.85Si0.15O2 dielectric could lead to the highest Ion/Ioff of 1.24×108, best SS of 81 V/dec, highest μFE of 51.7 cm2 V−1 s−1, lowest Dit of 7.70×1011 cm−2 eV−1, and smallest ΔVTH of 0.03 V. These improvements are attributed to the use of co-sputtered ZrxSi1−xO2 dielectric, which enhances the suppression of both Dit and the gate leakage current.
damage through increase the sputtering power for the SiO2 target should be made with discretion. In our experiment, it is found that the Si/(Zr+Si) ratio of 15% could be the best choice for ZrxSi1−xO2 gate dielectric for α-IGZO TFTs to have lowest Dit, which shows the lowest oxygen vacancy (OV/OT=21.09%), Dit of 7.70×1011 cm−2 eV−1, and SS of 0.081 mV/dec for IGZO TFT. 4. Conclusions A dielectric constant in the range of 6.9–31.6 has been obtained from the co-sputtering of ZrO2 and SiO2 through control of the RF power ratio. It was found that co-sputtered Zr0.85Si0.15O2 dielectrics
Fig. 11. Transfer characteristic of α-IGZO TFTs with Zr0.85Si0.15O2 gate dielectric under (a) PBS and (b) NBS.
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Fig. 12. Threshold voltage shift as a function of stress time for α-IGZO TFT with Zr0.85Si0.15O2 gate dielectric under PBS and NBS conditions.
Fig. 13. The dependence of Dit and Si/(Zr+Si) ratio of ZrxSi1−xO2 gate dielectric.
Acknowledgments This work was supported by the Ministry of Science and Technology (MOST), Taiwan, under contract Nos. MOST 105-2221-E-006-196-MY3 and MOST 104-2221-E-006-130-MY3. References [1] H.H. Hsieh, H.H. Lu, H.C. Ting, C.S. Chuang, C. Yu Chen, Y. Lin, J. Inf. Disp. 11 (2010) 160. [2] Y.G. Mo, M. Kim, C.K. Kang, J.H. Jeong, Y.S. Park, C.G. Choi, H.D. Kim, S.S. Kim, J. Soc. Inf. Disp. 19 (2011) 16. [3] T.C. Chen, T.C. Chang, T.Y. Hsieh, W.S. Lu, F.Y. Jian, C.T. Tsai, S.Y. Huang, C.S. Lin, Appl. Phys. Lett. 99 (2011) 022104. [4] T. Kamiya, K. Nomura, H. Hosono, Sci. Technol. Adv. Mater. 11 (2010) 044305. [5] J.S. Park, W.J. Maeng, H.S. Kim, J.S. Park, Thin Solid Films 520 (2012) 1679. [6] H.C. Wu, C.H. Chien, Appl. Phys. Lett. 102 (2013) 062103. [7] X. Li, D. Geng, M. Mativenga, J. Jang, IEEE Electron Device Lett. 35 (2014) 461. [8] G.J. Lee, J. Kim, J.H. Kim, S.M. Jeong, J.E. Jang, J. Jeong, Semicond. Sci. Technol. 29 (2014) 035003. [9] N. Gong, C. Park, J. Lee, I. Jeong, H. Han, J. Hwang, J. Park, K. Park, H. Jeong, Y. Ha, Y. Hwang, SID Symp. Dig. Tech. Pap. 43 (2012) 784. [10] Y.G. Mo, M. Kim, C.K. Kang, J.H. Jeong, Y.S. Park, C.G. Choi, H.D. Kim, S.S. Kim, J. Soc. Inf. Disp. 19 (2011) 16. [11] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, H. Hosono, Nature 432 (2004) 488. [12] J. Kyeong, J.H. Jeong, H.W. Yang, J.S. Park, Y.G. Mo, H.D. Kim, Appl. Phys. Lett. 91 (2007) 113505. [13] J.S. Lee, S. Chang, S.M. Koo, S.Y. Lee, IEEE Electron Device Lett. 31 (2010) 225. [14] Y.H. Lin, J.C. Chou, J. Nanomater. 2014 (1) (2014). [15] N.C. Su, S.J. Wang, A. Chin, IEEE Electr. Device L. 30 (2009) 1317. [16] L. Han, University of Kentucky UKnowledge, 2015, p. 9.
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Improving the electrical and hysteresis performance of amorphous igzo thinfilm transistors using co-sputtered zirconium silicon oxide gate dielectrics
MARK
⁎
Chien-Hsiung Hunga, Shui-Jinn Wanga,b, , Pang-Yi Liua, Chien-Hung Wuc, Hao-Ping Yana, Nai-Sheng Wua, Tseng-Hsing Lina a b c
Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan Advanced Optoelectronic Technology Center, National Cheng Kung University, Tainan 701, Taiwan Department of Electronics Engineering, Chung Hua University, Hsinchu 300, Taiwan
A R T I C L E I N F O
A B S T R A C T
Keywords: Indium gallium zinc oxide Co-sputtering, high-κ dielectric Thin-film transistor Zirconium silicon oxide Interface trap density
The use of co-sputtered Zirconium Silicon Oxide (ZrxSi1−xO2) gate dielectrics to improve the performance of αIGZO TFT is demonstrated. Through modulating the sputtering power of the SiO2 and ZrO2 targets, the control of dielectric constant in a range of 6.9–31.6 is shown. Prevention of polycrystalline formation of the ZrxSi1−xO2 film up to 600 °C annealing and its effectiveness in reducing leakage currents and interface trap density are presented. Moreover, it is revealed that the Zr0.85Si0.15O2 dielectric could lead to significantly improved TFT performance in terms of subthreshold swing (SS=81 mV/dec), field-effect mobility (μFE=51.7 cm2/Vs), and threshold voltage shift (ΔVTH=0.03 V).
1. Introduction Although amorphous indium-gallium-zinc-oxide (α-IGZO) thin-film transistors (TFTs) with superior performance compared with amorphous silicon-based TFTs have been demonstrated [1,2], continuous efforts are still required to further improve the electrical properties for advanced display applications. For next-generation displays, α-IGZO TFTs have obtained considerable attention due to their high mobility, excellent uniformity, low cost, and room temperature process. [3–8] These advantages render α-IGZO a promising material in the display industry, such as for flat panel displays, liquid crystal displays, activematrix organic light-emitting diode displays [9,10], and flexible displays [11,12]. In advancing the performance of α-IGZO TFTs, such as for the field-effect, mobility, and reduced gate leakage current, other alternative high-κ dielectrics for α-IGZO TFTs have been reported [13–15]. The trap density at the high-κ dielectrics/α-IGZO channel interface is large because the α-IGZO channel and high-κ dielectric films have abundant oxygen vacancies and enormous trap densities, respectively [16–19]. As a result, α-IGZO TFTs with a high interface trap density (Dit) at the high-κ dielectrics/α-IGZO channel interface usually suffer from inferior performance due to a high gate leakage current, poor subthreshold swing (SS), and low field-effect mobility (μFE) [20–25]. In recent years, various techniques have been reported for improving the defect issues regarding the high-κ dielectric/α-IGZO channel interface,
⁎
including the use of a more suitable dielectric [11], modifying the device structure [26], surface treatment of the active layer [27], and fabrication of the dielectric via the co-sputtering technique [28]. The advantage of the co-sputtering technique lies in the ability of the compound materials to be simultaneously deposited by multi-targets at room temperature. In this manner, suitable dielectric constants and gate dielectric compositions can be controlled through modulation of the cosputtering power ratio. Recently, reductions in the trap densities for the gate dielectrics of α-IGZO TFTs via the co-sputtering technique have been demonstrated [28,29]. Chen et al. and Song et al. developed αIGZO TFTs with co-sputtered Sm2TiO2 and NbLaO dielectrics to reduce the interface state density at the dielectric/α-IGZO channel interface [28,29]. Their experimental results suggested that the electrical performance could be improved via a suitable co-sputtering power ratio. In this study, to the best of the authors’ knowledge, the use of cosputtered zirconium silicon oxide (ZrxSi1−xO2) dielectrics to improve both the μFE and SS of the α-IGZO TFT is demonstrated for the first time. It is expected that the ZrxSi1−xO2 dielectric could offer a good compromise between the field-effect (dielectric constant) and gate leakage current, because silicon dioxide (SiO2) has the widest bandgap and lowest defect density while zirconium dioxide (ZrO2) provides a much better interface with α-IGZO in comparison with hafnium oxide (HfO2) [30–32]. S. Dueñas et al. and J. C. Park et al. reported that HfO2 dielectric or HfO2/α-IGZO might have a higher trap density at the interface with IGZO channel as compared with the case with ZrO2 or
Corresponding author at: Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan. E-mail address: [email protected] (S.-J. Wang).
http://dx.doi.org/10.1016/j.mssp.2017.05.017 Received 12 December 2016; Received in revised form 23 April 2017; Accepted 10 May 2017 1369-8001/ © 2017 Elsevier Ltd. All rights reserved.
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Fig. 1. Schematics of the α-IGZO TFTs with ZrxSi1−xO2 dielectrics.
ZrO2/α-IGZO interface. It results in an inferior performance of α-IGZO TFTs with HfO2 gate dielectric [30,31]. In addition, N.P. Maity et al. revealed that the MOS device with ZrO2 insulator shows lower Dit than the case with HfO2 insulator [32]. ZrO2 dielectric is expected to provide a better property of interface for IGZO TFT or MOS device. The optimal radio frequency (RF) power ratio for the co-sputtering of the ZrO2 and SiO2 targets at room temperature to maximize the role of the ZrxSi1−xO2 dielectrics is investigated. Experimental study into the suitable RF power ratio (ZrO2:SiO2) to yield ZrxSi1−xO2 dielectrics with good immunity to polycrystalline formation at temperatures up to 600 °C is conducted. In addition, the effects of post deposition annealing (PDA) on device performance, especially on the hysteresis characteristic, are also investigated.
200-nm-thick Titanium (Ti) layer was deposited by electron-beam evaporation as the source and drain contact electrodes. The channel length and width of the TFTs are 20 and 200 µm, respectively. During the fabrication of IGZO TFTs, metal–insulator–metal (M-I-M) capacitors were also prepared to investigate the dielectric constant and leakage characteristic of the gate dielectric. The devices were characterized under open air condition at room temperature using a Keithley 2636A semiconductor parameter analyzer and an HP4284A precision LCR meter, and the material properties were analyzed by X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) using an PHI 5000 Versa Probe and Rigaku D/MAX2500, respectively.
2. Experimental procedure
Fig. 2(a) shows the XPS survey of the ZrxSi1−xO2 films as a function of the co-sputtering power ratio of ZrO2 and SiO2. The atomic ratio shown in Fig. 2(b) was calculated from the XPS survey by the XPS system. Note that the RF sputtering power of the SiO2 target was modulated from 0 to 150 W while the power of the ZrO2 target was kept at 100 W. It indicates that although the atomic ratio of silicon was increased via increasing the co-sputtering power ratio, the atomic ratio of oxygen was almost constant (about 70%). According to the XPS analysis results, the co-sputtered ZrxSi1−xO2 could be defined as ZrO2, Zr0.85Si0.15O2, Zr0.45Si0.55O2, and Zr0.2Si0.8O2 for the SiO2 sputtering powers of 0, 50, 100, and 150 W, respectively. In Fig. 3(a), the peak position of the Zr 3d5/2 spectrum for ZrO2 film appears at 182 eV, which is consistent with the ideal value from the NIST database. In addition, the Zr 3d5/2 peak shifts to lower binding energy for the Zr0.85Si0.15O2 gate dielectric film, which should result
3. Results and discussion
A cross-sectional schematic of the proposed α-IGZO TFTs with cosputtered ZrxSi1−xO2 is shown in Fig. 1. A 10-nm-EOT (equivalent oxide thickness) ZrxSi1−xO2 layer was deposited as the gate dielectric on heavy-doped n-type silicon (n+-Si) substrate through RF co-sputtering of the 3-in ZrO2 (purity of 99.99%) and SiO2 (purity of 99.99%) targets under O2 ambient (purity of 99.99%) at room temperature. RF power ratios (ZrO2 (W):SiO2 (W)) of 100:0, 100:50, 100:100 and 100:150 were used for the co-sputtering processes, which was followed by furnace annealing under O2 ambient (purity of 99.99%) at 600 °C for 10 min. The 25-nm-thick α-IGZO channel layer was deposited by RF sputtering using an 3-in IGZO target (In2O3:Ga2O3:ZnO=1:1:1, and purity of 99.99%) under Ar ambient (purity of 99.99%). Note that the working pressure of all RF sputtering processes was kept at 10 mTorr. Finally, a
Fig. 2. (a) The XPS survey of the ZrxSi1−xO2 films. (b) Atomic ratio of ZrxSi1−xO2 as a function of the co-sputtering ratio of ZrO2 and SiO2.
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Fig. 3. The (a) Zr 3d and (b) Si 2p XPS spectra of ZrxSi1−xO2 films.
increased to 55% and 80%, respectively, which should be also due to the increase in oxygen vacancy in the gate dielectric. Fig. 4 shows the O 1s XPS spectra of ZrxSi1−xO2 films. The O 1s spectra can be deconvoluted into three different peaks, which are assigned as follows: the “lattice oxygen peak without oxygen vacancies” 530 eV, the “lattice oxygen peak in the oxygen-deficient region” 531.1 eV, and a metal hydroxide peak” (531.9 eV) [34]. It can be clearly seen that the relative area of the oxygen vacancy-related peak at 531.1 eV decreased with increasing Si content in the ZrxSi1−xO2 film. The values are 26.46%, 21.09%, 30.14% and 39.74% for the ZrO2,
from the suppression of oxygen vacancy by the Si incorporation. The reduction in the positively charged oxygen vacancies results in a decrease in the electric field, thus leading to a shift the Zr 3d5/2 peak to a lower binding energy [33]. However, for the Zr0.45Si0.55O2 and Zr0.2Si0.8O2 gate dielectric films, a different situation is seen. On the contrary, the increase in oxygen vacancies in gate dielectric with excess Si incorporation causes an increase in the binding energy. In Fig. 3(b), with the peak of Si 2p spectrum (101.8 eV) of the Zr0.85Si0.15O2 case as a reference, the peak position of the Si 2p spectrum for ZrxSi1−xO2 shows a positive energy shift of 0.2 and 1.1 eV as Si content was
Fig. 4. The O 1s XPS spectra of ZrxSi1−xO2 films.
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Fig. 5. XRD analysis of the co-sputtered ZrxSi1−xO2 films at various annealing temperatures.
Zr0.85Si0.15O2, Zr0.45Si0.55O2, and Zr0.2Si0.8O2 films, respectively. The results indicates that a suitable co-sputtered power ratio of ZrO2 and SiO2 could decrease the trap density of ZrxSi1−xO2, but higher cosputtered power could possibly incur plasma damage on the surface. In this study, the RF sputtering power of the SiO2 target was modulated from 0 to 150 W while the power of the ZrO2 target was kept at 100 W. The XPS results indicate that the trap density increases through increasing the sputtering power of the SiO2 upon 100 W, suggesting that the high sputtering power could possibly cause plasma damage and increase the trap density on the gate dielectric surface. Note that the relative area of the metal hydroxide peak at 531.9 eV was increased with increasing Si incorporation in the ZrxSi1−xO2 films except Zr0.85Si0.15O2. It suggests that the OH-impurities from the ambient atmosphere might be preferentially adsorbed on the surface of ZrxSi1−xO2 with high sputtering power of SiO2, which can be attributed to the high trap density on surface caused by the plasma damage. Fig. 5 shows the XRD analysis results for ZrxSi1−xO2 with different co-sputtering power ratios. It can be seen that for the co-sputtered ZrxSi1−xO2 dielectrics with Si/(Si+Zr) ratio, more than 15% still remains in an amorphous-like structure even after PDA up to 600 °C under O2 ambient. However, the ZrO2 film appears to be a polycrystalline structure after the 600 °C PDA, which is likely to incur leakage current under a gate bias and thereby deteriorate device performance. It could be attributed to the transition temperature of ZrxSi1−xO2 gate dielectrics is higher than that of the ZrO2 film with dopant [35]. Our results suggest that the co-sputtered ZrxSi1−xO2 layer with a suitable composition could suppress the high-temperature annealing crystallization process. The oxide capacitance and dielectric constant were measured and evaluated from a metal/insulator/metal (M-I-M) structure of n+-Si/ ZrxSi1−xO2/Ti. For a fair comparison in device performance, the same EOT of dielectric of 10 nm (corresponding to Cox≈3.1×10−7 F/cm2) was used in experiments. Fig. 6 (inset) shows the C-V characteristic of n+-Si/Zr0.85Si0.15O2/Ti capacitor through PDA process at 600 °C for
Fig. 6. Dielectric constant and Si/(Si+Zr) ratio of the ZrxSi1−xO2 films as a function of the co-sputtering ratio of ZrO2 and SiO2. (inset) The C-V characteristic of n+-Si/ Zr0.85Si0.15O2/Ti capacitor.
10 min under O2 ambient. The dielectric constant of the ZrxSi1−xO2 dielectrics were 31.6, 22.8, 12.3, and 6.9 via 600 °C PDA process for the samples prepared with the Si/(Si+Zr) ratios of 0% (ZrO2), 15% (Zr0.85Si0.15O2), 55% (Zr0.45Si0.55O2), and 80% (Zr0.2Si0.8O2), respectively. The dependence on the dielectric constant and Si/(Si+Zr) ratio for the ZrxSi1−xO2 films with the co-sputtering power ratio of ZrO2 and SiO2 is shown in Fig. 4, which indicates that the dielectric constant of the ZrxSi1−xO2 dielectrics could be well controlled through the cosputtering power ratio of ZrO2 and SiO2. Note that the ZrO2 with 600 °C PDA shows the higher dielectric constant of 31.6 than the conventional case of 25, it could be attributed that ZrO2 with 600 °C PDA has a cubic phase as confirmed XRD analysis. In essential, the dielectric constant of ZrO2 can be enhanced with improved crystallinity [36,37]. The AFM surface-roughness analysis of the prepared ZrO2 and ZrxSi1−xO2 dielectrics are listed in Table 1. Typical surface roughness 87
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Table 1 Comparison of device performance characteristics for the α-IGZO TFTs with ZrxSi1−xO2 dielectrics. Devices
VTH (V)
μFE (cm2 V−1 s−1)
SS (V/dec)
Ion/Ioff
Dit (cm−2 eV−1)
ΔVTH (V)
Surface Roughness (nm)
ZrO2 Zr0.85Si0.15O2 Zr0.45Si0.55O2 Zr0.2Si0.8O2 [29]a) [39]b) [60]c) [61]d) [62]e)
1.25 0.45 0.53 0.22 1.84 3.5 12.9 0.7 2.8
31.79 51.70 27.21 9.70 28.00 30.90 24.50 13.70 12.90
0.111 0.081 0.116 0.152 0.170 0.170 ~1.5 0.380 0.090
1.05×107 1.24×108 1.47×107 1.08×105 5.30×107 2.00×106 6.10×107 109 109
1.85×1012 7.70×1011 2.03×1012 3.33×1012 3.00×1012 2.60×1012 – – –
0.52 0.03 0.57 0.79 −0.07 0.80 – – –
2.40 0.16 0.17 0.18 – – – – –
Note: IGZO TFT with a) co-sputtered NbLaO dielectric, b) co-sputtered TaLaO dielectric, c) thermally growth SiO2 dielectric, d) SiNx dielectric (PECVD), and e) sputtered Al2O3 dielectric.
should be due to the lowest trap density at the channel/dielectric interface. The transfer characteristics of the α-IGZO TFTs with ZrO2 and ZrxSi1−xO2 dielectrics prepared under different co-sputtering power ratios with the PDA are shown in Fig. 9, with the extracted device electrical parameters listed in Table 1. Our results reveal that the αIGZO TFTs with Zr0.85Si0.15O2 had the best properties with the highest on-off current ratio (Ion/Ioff) of 1.24×108, lowest SS of 81 mV/dec, highest μFE of 51.70 cm2 V−1 s−1, and lowest Dit of 7.05×1011 cm−2 eV−1. The μFE induced from transconductance (gm ) measurement at a low drain voltage VDS=0.1 V was determined as following Eq. (1):
μFE =
+
Lgm WCox VDS
(1)
where Cox and gm are the gate capacitance density and transconductance, respectively. Note that the κ-IGZO TFT with Zr0.85Si0.15O2 gate dielectric shows the best performance of μFE, the Cox and gm are 3.12×10−7 F/cm2 and 1.613×10−5 (A/V), respectively. The improved μFE and Ion/Ioff performances are mainly ascribed to the proposed ZrxSi1−xO2 dielectrics having an amorphous-like structure and good dielectric/channel interface, which suppresses gate leakage current. Of note, the sample with the Zr0.85Si0.15O2 dielectric exhibited the best gate control capability (lowest SS of 81 mV/dec), which could be attributed to a considerable suppression in trap density through a suitable SiO2 insertion in the Zr0.85Si0.15O2 film. To clarify the dependence on the Dit and TFT performance, the values of Dit at the interface of the ZrO2/α-IGZO and ZrxSi1−xO2/α-IGZO structures were extracted from the capacitance-voltage measurement and SS values. Note that Dit was evaluated by the following Eq. (2):
+
Fig. 7. Leakage current properties of the n -Si/ZrO2/Ti and n -Si/ZrxSi1−xO2/Ti capacitors.
values of the co-sputtered Zr0.85Si0.15O2 films range from 0.16 to 0.18 nm, while that of the ZrO2 film is about 2.4 nm. This indicates that the surface of the co-sputtered ZrxSi1−xO2 films is much smoother than that of the ZrO2 layer, which is mainly attributed to the ZrxSi1−xO2 films being immune from polycrystalline structure formation; by contrast, grain growth in the ZrO2 film leads to a rougher surface [38], which is consistent with results of the XRD analysis. Fig. 7 shows the leakage current properties of the n+-Si/ZrO2/Ti and n+-Si/ZrxSi1−xO2/Ti capacitors. Note that the thickness of each dielectric layer was scaled to have the same EOT of 10 nm. It can be seen that the cases with Zr0.85Si0.15O2 and Zr0.45Si0.55O2 insulator both have a lower current density than that of with the ZrO2 layer. The ZrO2 and ZrxSi1−xO2 XRD analysis results shown in Fig. 5 reveal that the amorphous-like structure of ZrxSi1−xO2 remains intact, even after thermal annealing at temperatures up to 600 °C; in comparison, ZrO2 shows a polycrystalline structure without thermal annealing. Moreover, the abundant grain boundaries in a polycrystalline structure dielectric inevitably increase the probability of carrier transport and leakage current [39]. The measured leakage current densities shown in the figure indicate that, with a suitable composition, the co-sputtered ZrxSi1−xO2 layer could be used as a suitable gate dielectric for α-IGZO TFTs. Note that the case with Zr0.2Si0.8O2 has a higher leakage current which could be due to it has a higher trap density [40]. Based on O 1s XPS spectra of the Zr0.2Si0.8O2 gate dielectric, the film shows the highest oxygen vacancies density than other samples. The result could be attributed to the increase in the composition of SiO2 in the ZrxSi1−xO2 gate have consumed a considerable amount of oxygen and the occurrence of plasma-related damages. Fig. 8 shows the output characteristics of α-IGZO TFTs with ZrxSi1−xO2 gate dielectrics. Enhancement mode behaviours with good saturation characteristics were observed with a low operation voltage of 4 V. It can be seen that the α-IGZO TFT with Zr0.85Si0.15O2 gate dielectric shows the highest drain current at saturation region, which
SS ≈
⎛ qDit ⎞ kT ln (10) ⎜1 + ⎟ ⎝ q Cox ⎠
(2)
where k is Boltzmann's constant and Cox is the gate insulator capacitance [41]. Many studies reported that both the TFT performances of SS and μFE are considerably degraded by a high Dit, which suppresses gate control capability [42–44]. In general, SS might be an indicator of the Dit value at the dielectric/channel interface. In our experiments, the αIGZO TFT with the Zr0.85Si0.15O2 dielectric shows an excellent SS of 81 mV/dec with the lowest Dit of 7.70×1011 cm−2 eV−1, which is about one third of that in the α-IGZO TFT with ZrO2 gate dielectric. Accordingly, these results suggest that the Dit of the ZrxSi1−xO2/α-IGZO interface can be substantially decreased through a suitable co-sputtered power ratio. To further confirm the effectiveness of the proposed Zr1−xSixO2 dielectric layers, the hysteresis characteristics of the α-IGZO TFTs with the ZrO2 and ZrxSi1−xO2 dielectrics after PDA at 600 °C for 10 min under O2 ambient were examined, as shown in Fig. 10. Essentially, the hysteresis performance of the α-IGZO TFT might be affected by a number of factors, including carrier trapping in the gate dielectric/ channel interface [45–49], oxygen vacancies on the surface of high-κ dielectric and α-IGZO channel [50–54], and/or the donor like defects in 88
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Fig. 8. The output characteristics of α-IGZO TFTs with ZrxSi1−xO2 gate dielectrics.
suitable co-sputtering power for ZrO2 and SiO2. It is expected that, with an optimized ZrxSi1−xO2 layer to further suppress Dit, advanced α-IGZO FETs with reduced gate leakage current, enhanced SS, and improved hysteresis characteristics can be realized. Fig. 11 shows the transfer characteristic of α-IGZO TFTs with Zr0.85Si0.15O2 gate dielectric after bias stress. The bias stress condition is VGS= ± 4 V for a maximum time period of 1000 s. The threshold voltage shift (ΔVTH) of the device under positive bias stress (PBS) and negative bias stress (NBS) conditions is investigated as a function of stress time, as shown in Fig. 12. Our results indicate that PBS and NBS lead to a positive and negative ΔVTH, respectively. It could be attributed to excess electrons are accumulated and captured by oxygen molecules in the α-IGZO channel under PBS, as a result, buildup of negative charge (O2-) causes a positive VTH shift [55,56]. While under NBS, the adsorbed moisture from the atmosphere might change into positively charged species (H2O+) in the α-IGZO channel. Hence the accumulation of H2O+ thus leads to a negative VTH shift [56]. Similar explanations were reported in the literature [55–59]. Fig. 13 shows the dependence of the interface trap density Dit on the Si/(Zr+Si) ratio of ZrxSi1−xO2 gate dielectric. It reveals that, as the Si/ (Zr+Si) ratio was increased from 0% to 80%, the interface trap density Dit decreases at the initial stage, reaches a minimum value at around 15% and then increase. Based on the fact that trap density at SiO2/αIGZO interface is much less than that at ZrO2/α-IGZO interface [32], the increase of SiO2 content in the ZrxSi1−xO2 gate dielectric might be responsible for the suppression of Dit in the experiment. However, a higher sputtering power was needed to increase the SiO2 content, which would cause plasma-related damages at around interface. Accordingly, a tread-off between the decrease in Dit and increase in plasma-related
Fig. 9. Transfer characteristics of the α-IGZO TFTs with ZrxSi1−xO2 gate dielectrics.
the α-IGZO channel [50–53]. When the gate voltage (VGS) was swept from −1 V to 4 V, it was found that the threshold voltage shifts (ΔVTH) of the α-IGZO TFTs with ZrxSi1−xO2 dielectric layers were much smaller than those measured from the device with the ZrO2 dielectric layer. Note that the α-IGZO TFT with Zr0.85Si0.15O2 after PDA had the lowest ΔVTH of 0.03 V among all prepared devices. The difference in ΔVTH can be explained by the degrees of electron trapping in the dielectric/αIGZO channel interface. The amount of electrons that can be repeatedly trapped and released depends on the applied voltage, which is proportional to the magnitude of Dit. As compared with a conventional ZrO2 dielectric layer, our experimental results indicate that the Dit at the ZrxSi1−xO2/α-IGZO interface can be considerably reduced by a 89
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Fig. 10. Hysteresis characteristics of the α-IGZO TFTs with ZrxSi1−xO2 gate dielectrics.
prepared at a power ratio of ZrO2:SiO2=100 W:50 W allows the amorphous-like structure and smooth surface to be retained even after PDA at 600 °C, which is very beneficial for reducing gate leakage current. Experimental results revealed that α-IGZO TFT with the proposed Zr0.85Si0.15O2 dielectric could lead to the highest Ion/Ioff of 1.24×108, best SS of 81 V/dec, highest μFE of 51.7 cm2 V−1 s−1, lowest Dit of 7.70×1011 cm−2 eV−1, and smallest ΔVTH of 0.03 V. These improvements are attributed to the use of co-sputtered ZrxSi1−xO2 dielectric, which enhances the suppression of both Dit and the gate leakage current.
damage through increase the sputtering power for the SiO2 target should be made with discretion. In our experiment, it is found that the Si/(Zr+Si) ratio of 15% could be the best choice for ZrxSi1−xO2 gate dielectric for α-IGZO TFTs to have lowest Dit, which shows the lowest oxygen vacancy (OV/OT=21.09%), Dit of 7.70×1011 cm−2 eV−1, and SS of 0.081 mV/dec for IGZO TFT. 4. Conclusions A dielectric constant in the range of 6.9–31.6 has been obtained from the co-sputtering of ZrO2 and SiO2 through control of the RF power ratio. It was found that co-sputtered Zr0.85Si0.15O2 dielectrics
Fig. 11. Transfer characteristic of α-IGZO TFTs with Zr0.85Si0.15O2 gate dielectric under (a) PBS and (b) NBS.
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Fig. 12. Threshold voltage shift as a function of stress time for α-IGZO TFT with Zr0.85Si0.15O2 gate dielectric under PBS and NBS conditions.
Fig. 13. The dependence of Dit and Si/(Zr+Si) ratio of ZrxSi1−xO2 gate dielectric.
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