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Improving the yield and reliability of the bulk-silicon HV-CMOS by adding a P-well
Microelectronics Reliability 45 (2005) 185–190 www.elsevier.com/locate/microrel
Research Note
Improving the yield and reliability of the bulk-silicon HV-CMOS by adding a P-well Weifeng Sun *, Longxing Shi National ASIC System Engineering Research Center, Southeast University, Nanjing, Jiangsu 210096, PR China Received 16 January 2004; received in revised form 19 July 2004 Available online 21 September 2004
Abstract In this paper, a novel high-yield and high-reliability High Voltage CMOS (HV-CMOS) compatible with 0.6 lm rules standard Bulk-Silicon (BS) CMOS process was proposed. The detailed discussion on how to avoid the influence of the lithography misalignment of the High Voltage PMOS (HV-PMOS) was given. The detailed analysis on the validity of the added p-well to prevent the High Voltage Double-Diffusion NMOS (HV-DNMOS) from punching through was also suggested. The experimental results show the yields of the HV-PMOS and the HV-CMOS are more than 98% and 95%, respectively, which are due to adding the p-well to HV-PMOS for eliminating the influence of the lithography misalignment during etching the unwanted thick gate oxide film of the HV-PMOS and that to HV-DNMOS for preventing punch-through. The breakdown voltage of the presented HV-CMOS exceeds 100 V, which can be well applied in high voltage driver ICs, etc. 2004 Elsevier Ltd. All rights reserved.
1. Introduction Since High Voltage CMOS (HV-CMOS) has its wellknown intrinsic advantages: high input impedance, short switching time and thermal stability, HV-CMOS has been developed for variety of applications, such as audio amplifiers, automotive electronics, motor driver and flat display panel driver, etc. [1–3]. In the CMOS technology, the most part of the power driver ICs on the die, until 70%, is taken up by HV-CMOS transistors, so the yield of HV-CMOS is the most important factor for improving the yield of the whole power driver ICs. The instabilities of drain-source leakage, gate oxide breakdown and the adhesive between chip and lead * Corresponding author. Tel.: +86 25 83795811x8401; fax: +86 25 83352764. E-mail address: swff[email protected] (W. Sun).
frame have been found the factors that result in the low reliability of power ICs [4–7]. In many HV-CMOS driver ICs, the HV-PMOS gate is always driven by high voltage level which is equal to the supply high voltage, but the High Voltage NMOS (HV-NMOS) is driven by logic 5v level. So the gate oxide film of the HV-PMOS must be thicker than that of the HV-NMOS [8] and the thick-gate-oxide film of the HV-PMOS should be specially manufactured. Because the HV-DNMOS and LV-CMOS only need thin gate-oxide film for the low threshold voltage, the unwanted thick-gate-oxide film formed in these regions during the thick-gate-oxide film fabrication process must be etched. But etching the unwanted thick-gate-oxide film of the HV-PMOS will reduce the yield of the HV-PMOS for the lithography misalignment. In this paper, a novel HV-CMOS structure compatible with 0.6 lm rules standard BS CMOS process was
0026-2714/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2004.08.007
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given. A novel way to eliminate the influence of the lithography misalignment during etching the unwanted thick-gate-oxide film of the HV-PMOS and to prevent the HV-DNMOS from punching through was proposed. In this way the yield and the reliability of the whole HVCMOS are greatly improved and the breakdown voltage of the HV-CMOS exceeds 100 V.
2. HV-CMOS structure Fig. 1 shows the schematic cross-section of the novel HV-CMOS structure using BS p-substrate, which includes HV-PMOS and HV-DNMOS. The drift length of the HV-PMOS and the HV-DNMOS were 7.5 and 7 lm, respectively. The channel length of the HV-PMOS and the HV-DNMOS were both 2.0 lm. One p-well was added to the HV-PMOS between the p-channel and p+source, and the other p-well was also added to the HVDNMOS surrounding the n-channel and n+-source. The two p-wells were fabricated together. Because the HV-PMOS gates are always driven by high voltage level which is equal to the supply high voltage, on the other hand, HV-DNMOS gates are driven by logic 5 V level in most CMOS power driver ICs, the gate oxide film thickness of the presented HV-PMOS is thicker than that of the HV-DNMOS whose gate oxide film is as thick as the Low Voltage CMOS (LV-CMOS). In the proposed HV-CMOS structure the thickness of the gate oxide film of the HV-PMOS and HV-DNMOS were 200 and 18 nm, respectively.
3. Fabrication process of the HV-CMOS The novel HV-CMOS was based on a 0.6 lm rule BS standard LV-CMOS process. Table 1 shows the idiographic compatible process flows. These high temperature diffusion processes for HV-CMOS were carried out before the LV-CMOS process. All the compatible processes only need 14 photomasks. The deep n-well for HV-PMOS was implanted by using phosphorus with doses of 1.25 · 1013 cm 2 at 180 keV, and was annealed in a N2 ambient at 1150 C
Fig. 1. Schematic cross-section of the novel HV-CMOS.
Table 1 Process flows of the novel HV-CMOS 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.
BS p-substrate Deep n-well of HV-PMOS formation n- and p-drift formation LOCOS formation Channel doping Thick-gate-oxide film of HV-PMOS formation Poly-gate formation p-well formation S/D formation Contact Metallization Pad
for 1200 min. The n-drift was implanted by using phosphorus with doses of 4.0 · 1012 cm 2 at 180 keV, and was annealed in a N2 ambient at 1150 C for 250 min. The p-drift was implanted by using boron with doses of 2.0 · 1013 cm 2 at 160 keV, and was annealed in a N2 ambient at 1150 C for 1300 min. After the unwanted thick-gate-oxide film was etched and the poly-gate was formed the p-well for HV-CMOS was implanted by using boron with doses of 2.3 · 1013 cm 2 at 75 keV, and was annealed in a N2 ambient at 1100 C for 100 min. The following processes were the same as the standard LVCMOS processes.
4. Etching the thick-gate-oxide film of the HV-PMOS discussion Since the gate oxide film thickness of the proposed HV-PMOS was thicker than that of the HV-DNMOS, as shown in Fig. 1, the unwanted thick-gate-oxide film of the HV-PMOS must be etched before the poly-gate deposition. In the conventional design, the left boundary of the poly-gate image on the photomask is aligned with that of the thick-gate-oxide film image. But in the actual process the lithography misalignments always happen. If the finally gained image of the poly-gate of the HVPMOS on the silicon wafer deviates from the original image on the photomask to left-side, the HV-PMOS will breakdown at a low voltage. On the contrary, the conventional HV-PMOS will cut-off if the image of the poly-gate deviates to right-side, as shown in Fig. 2(a) and (b), respectively. When these phenomena happen, the yield of the HV-PMOS will be greatly reduced. In order to avoid the influence of the lithography misalignments of the HV-PMOS, the left boundary of the designed image of the poly-gate on the photomask must be retracted by the absolute value of the maximum misalignment from the left boundary of the thick-gateoxide film image on the photomask. In this way the phenomenon shown in Fig. 2(a) would be completely
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Fig. 3. Physical correlations of the three images (thick-gateoxide film image, poly-gate image and p-well image) on the photomasks of the novel HV-PMOS.
Fig. 2. Breakdown phenomenon (a) and cut-off phenomenon (b) of the onventional HV-PMOS.
avoided, but the phenomenon shown in Fig. 2(b) would more easily happen. In order to keep the phenomenon from taking place, a p-well was added to the conventional HV-PMOS, as shown in Fig. 1. The p-well could be formed with self-alignment process after the polygate was formed. Fig. 3 showed the physical correlations of the three images (thick-gate-oxide film, poly-gate and p-well) on the photomasks. Here we considered that the maximum values of the lithography misalignment error were ±0.2 lm in the given 0.6 lm rules standard BS CMOS process. The junction depth of the added p-well was 1 lm after the diffusion process, so the right boundary of the p-well would be protracted by 0.8 lm from the left boundary of the thick-gate-oxide film on the silicon wafer. When the maximum lithography misalignment (±0.2 lm) happened, the distance between left boundary of the poly-gate image and that of the thick-gate-oxide film image of the novel HV-PMOS on the silicon wafer would be 0 or 0.4 lm, respectively after the whole fabrication processes, as shown in Fig. 4. Even if the distance was 0.4 lm, the HV-PMOS would never cut off because
Fig. 4. Maximum left and right errors of lithography misalignment between the poly-gate and the thick-gate-oxide film on the wafer.
the p-well can be used as the p+-source junction. With the novel design of the poly-gate image on the photomask and the added p-well, even if the maximum lithography misalignment happened, the novel HV-PMOS could always work safely. One step process was added for the additional p-well. The on-resistance of the HVPMOS increased a little, because the junction of the p-well was shallow, which did not greatly influence the application of the ICs with the proposed HV-PMOS. In this way, the influence of the lithography misalignment was completely eliminated and the yield and reliability of the HV-PMOS were greatly improved.
5. Punch-through of the HV-DNMOS discussion It is important to prevent HV-DNMOS from punching through for the low concentration of the p-substrate. So the p-well was added to the HV-DNMOS in the novel HV-CMOS structure to prevent the punchthrough, as shown in Fig. 1. Fig. 5(a) and (b) show the breakdown potential contours of a conventional HVDNMOS without a p-well and the novel HV-DNMOS
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Fig. 5. Simulated breakdown contours of a conventional HV-DNMOS without a p-well (a) and of the proposed HV-DNMOS with a p-well (b).
with a p-well, respectively, which were obtain from 2D device simulations using MEDICI. The applied voltage conditions in the simulations were as follows, Vsub, Vs and Vg were 0 V, and Vd was a positive high voltage of 100 V. The punch-through happened between the source and n-drift regions of the conventional HV-DNMOS without a p-well when Vd was positive 100 V, as shown in Fig. 5(a). But it is clear from Fig. 5(b) that the punch-through was avoided only because the p-well was added to the HV-DNMOS. In this way, the concentration of the channel and source regions of the HVDNMOS was increased. So the punch-through voltage of the HV-DNMOS was greatly increased, moreover the reliability of the novel HV-CMOS was greatly improved compared with the conventional HV-CMOS.
Although the impurity concentration of the channel region increased with the added p-well, the length of the proposed HV-DNMOS channel could be shorted by several microns compared with that of the conventional HV-DNMOS for the same punch-through voltage. So the whole on-resistance of the presented HV-DNMOS would be improved a little.
6. Experimental results of the HV-CMOS discussion The proposed HV-CMOS was fabricated with the mentioned process in Section 3, which was compatible with 0.6 lm rules standard LV-CMOS process. Fig. 6(a) shows that the experimental distance between the
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Fig. 7. Experimental I–V characteristic curves of the novel HVCMOS with W/L=60 and that of the conventional HV-PMOS without a p-well.
the HV-PMOS to avoiding the cut-off caused by the lithography misalignment. The yields of the proposed HV-PMOS and the HV-CMOS are more than 98% and 95% respectively, but the yield of the conventional HV-CMOS is about 66%. 7. Conclusion
Fig. 6. SEM photograph of the novel HV-PMOS channel region (a) and that of the conventional HV-PMOS channel region (b).
left boundary of the poly-gate and that of the thick-gateoxide film of the novel HV-PMOS is 0.30 lm, which is in the error ranges we have considered in Section 4. Fig. 6(b) shows the experimental distance of the conventional HV-PMOS is 0.08 lm. The conventional HV-PMOS broke down with Vd = 20 V. The experimental results prove the proposed design of the image of the poly-gate on the photomask is very effective to eliminate the influence of the lithography misalignment during the etching the unwanted thick-gate-oxide film of the HV-PMOS. The experimental breakdown characteristic proves the added p-well to the HV-DNMOS is also very effective to prevent the HV-DNMOS from punching through. Fig. 7 shows experimental I–V characteristic results of the proposed HV-CMOS. The breakdown voltage of the novel HV-CMOS exceeds 100 V. The current of the measured HV-PMOS and HV-DNMOS, whose ratios of Width/Length are both 60, are 9.5 mA at Vgs = 10 V and 7 mA at Vgs = 5 V, respectively. But the conventional HV-PMOS without a p-well still cut off under the condition of the Vgs = 10 V and Vd = 100 V, as shown in Fig. 7. The experimental result confirms that the added p-well is very effective to
In this paper, a novel HV-CMOS structure and the compatible BS CMOS process have been proposed. The ways to eliminate the lithography misalignment of the HV-PMOS and to prevent the punch-through of the HV-DNMOS are discussed in detail. The experimental results confirm that the yield and the reliability of the proposed HV-CMOS are greatly improved with the novel design of the image of the poly-gate on the photomask, with the added p-well to avoiding the influence of the lithography misalignment and with that to HVDNMOS for preventing the punch-through. The breakdown voltages of the HV-PMOS and the HV-DNMOS all exceed 100 V. The presented HV-CMOS can be well applied in power driver ICs, etc. Acknowledgments The authors thank the National High Technology Research and Development Program of China (‘‘863’’ Program) for the project and the engineers in Wuxi CSMC Company Limited for their fabricating supported. The authors also would like to thank all referees for their helpful comments and good suggestions. References [1] Baliga BJ. Trends in power semiconductor devices. IEEE Trans Electron Dev 1996;43:1717–31. [2] Finco S, Behrens FH, Castro Simas MI. Smart power IC for DC-DC low power regulation. In: Industry applications
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society annual meeting, Conference record of the 1992 IEEE, vol. 1. 1992. p. 1204–11. [3] Sun WF, Wu JH, Yi YB, Lu SL, Shi LX. High-voltage power integrated circuit technology using bulk-silicon for plasma display panels data driver IC. Microelectron Eng 2004;71:112–8. [4] Tosˇic N, Pesˇic B, Stojadinovic N. HTSL and HTRB reliability testing of power VDMOSFETS. In: Proc. 20th MIELÕ95 Conf., Nis, Yugoslavia; 1995. p. 285. [5] Tosˇic N, Pesˇic B, Stojadinovic N. Reliability testing of power VDMOS transistors. In: International Conference on
Microelectronics (MIELÕ97), vol. 2. Nis, Yugoslavia; 1997. p. 14–17. [6] Jimenez M, Nogueira E, Perez Q, Vila J. Accelerated test of powers MOSFET. In: Proc. 5th ESREFÕ94 Conf., Glasgow; 1994. p. 221. [7] Rey-Tauriac Y, Taurin M, Bonnaud O. High reliability power VDMOS Transistors in Bipolar/CMOS/DMOS technology. Microelectron Reliab 2001;42:1707–12. [8] Kim J, Roh TM, Kim SG et al.. High-voltage power integrated circuit technology using SOI for driving plasma display panels. IEEE Trans Electron Dev 2001;48:1256–63.
Research Note
Improving the yield and reliability of the bulk-silicon HV-CMOS by adding a P-well Weifeng Sun *, Longxing Shi National ASIC System Engineering Research Center, Southeast University, Nanjing, Jiangsu 210096, PR China Received 16 January 2004; received in revised form 19 July 2004 Available online 21 September 2004
Abstract In this paper, a novel high-yield and high-reliability High Voltage CMOS (HV-CMOS) compatible with 0.6 lm rules standard Bulk-Silicon (BS) CMOS process was proposed. The detailed discussion on how to avoid the influence of the lithography misalignment of the High Voltage PMOS (HV-PMOS) was given. The detailed analysis on the validity of the added p-well to prevent the High Voltage Double-Diffusion NMOS (HV-DNMOS) from punching through was also suggested. The experimental results show the yields of the HV-PMOS and the HV-CMOS are more than 98% and 95%, respectively, which are due to adding the p-well to HV-PMOS for eliminating the influence of the lithography misalignment during etching the unwanted thick gate oxide film of the HV-PMOS and that to HV-DNMOS for preventing punch-through. The breakdown voltage of the presented HV-CMOS exceeds 100 V, which can be well applied in high voltage driver ICs, etc. 2004 Elsevier Ltd. All rights reserved.
1. Introduction Since High Voltage CMOS (HV-CMOS) has its wellknown intrinsic advantages: high input impedance, short switching time and thermal stability, HV-CMOS has been developed for variety of applications, such as audio amplifiers, automotive electronics, motor driver and flat display panel driver, etc. [1–3]. In the CMOS technology, the most part of the power driver ICs on the die, until 70%, is taken up by HV-CMOS transistors, so the yield of HV-CMOS is the most important factor for improving the yield of the whole power driver ICs. The instabilities of drain-source leakage, gate oxide breakdown and the adhesive between chip and lead * Corresponding author. Tel.: +86 25 83795811x8401; fax: +86 25 83352764. E-mail address: swff[email protected] (W. Sun).
frame have been found the factors that result in the low reliability of power ICs [4–7]. In many HV-CMOS driver ICs, the HV-PMOS gate is always driven by high voltage level which is equal to the supply high voltage, but the High Voltage NMOS (HV-NMOS) is driven by logic 5v level. So the gate oxide film of the HV-PMOS must be thicker than that of the HV-NMOS [8] and the thick-gate-oxide film of the HV-PMOS should be specially manufactured. Because the HV-DNMOS and LV-CMOS only need thin gate-oxide film for the low threshold voltage, the unwanted thick-gate-oxide film formed in these regions during the thick-gate-oxide film fabrication process must be etched. But etching the unwanted thick-gate-oxide film of the HV-PMOS will reduce the yield of the HV-PMOS for the lithography misalignment. In this paper, a novel HV-CMOS structure compatible with 0.6 lm rules standard BS CMOS process was
0026-2714/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2004.08.007
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given. A novel way to eliminate the influence of the lithography misalignment during etching the unwanted thick-gate-oxide film of the HV-PMOS and to prevent the HV-DNMOS from punching through was proposed. In this way the yield and the reliability of the whole HVCMOS are greatly improved and the breakdown voltage of the HV-CMOS exceeds 100 V.
2. HV-CMOS structure Fig. 1 shows the schematic cross-section of the novel HV-CMOS structure using BS p-substrate, which includes HV-PMOS and HV-DNMOS. The drift length of the HV-PMOS and the HV-DNMOS were 7.5 and 7 lm, respectively. The channel length of the HV-PMOS and the HV-DNMOS were both 2.0 lm. One p-well was added to the HV-PMOS between the p-channel and p+source, and the other p-well was also added to the HVDNMOS surrounding the n-channel and n+-source. The two p-wells were fabricated together. Because the HV-PMOS gates are always driven by high voltage level which is equal to the supply high voltage, on the other hand, HV-DNMOS gates are driven by logic 5 V level in most CMOS power driver ICs, the gate oxide film thickness of the presented HV-PMOS is thicker than that of the HV-DNMOS whose gate oxide film is as thick as the Low Voltage CMOS (LV-CMOS). In the proposed HV-CMOS structure the thickness of the gate oxide film of the HV-PMOS and HV-DNMOS were 200 and 18 nm, respectively.
3. Fabrication process of the HV-CMOS The novel HV-CMOS was based on a 0.6 lm rule BS standard LV-CMOS process. Table 1 shows the idiographic compatible process flows. These high temperature diffusion processes for HV-CMOS were carried out before the LV-CMOS process. All the compatible processes only need 14 photomasks. The deep n-well for HV-PMOS was implanted by using phosphorus with doses of 1.25 · 1013 cm 2 at 180 keV, and was annealed in a N2 ambient at 1150 C
Fig. 1. Schematic cross-section of the novel HV-CMOS.
Table 1 Process flows of the novel HV-CMOS 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.
BS p-substrate Deep n-well of HV-PMOS formation n- and p-drift formation LOCOS formation Channel doping Thick-gate-oxide film of HV-PMOS formation Poly-gate formation p-well formation S/D formation Contact Metallization Pad
for 1200 min. The n-drift was implanted by using phosphorus with doses of 4.0 · 1012 cm 2 at 180 keV, and was annealed in a N2 ambient at 1150 C for 250 min. The p-drift was implanted by using boron with doses of 2.0 · 1013 cm 2 at 160 keV, and was annealed in a N2 ambient at 1150 C for 1300 min. After the unwanted thick-gate-oxide film was etched and the poly-gate was formed the p-well for HV-CMOS was implanted by using boron with doses of 2.3 · 1013 cm 2 at 75 keV, and was annealed in a N2 ambient at 1100 C for 100 min. The following processes were the same as the standard LVCMOS processes.
4. Etching the thick-gate-oxide film of the HV-PMOS discussion Since the gate oxide film thickness of the proposed HV-PMOS was thicker than that of the HV-DNMOS, as shown in Fig. 1, the unwanted thick-gate-oxide film of the HV-PMOS must be etched before the poly-gate deposition. In the conventional design, the left boundary of the poly-gate image on the photomask is aligned with that of the thick-gate-oxide film image. But in the actual process the lithography misalignments always happen. If the finally gained image of the poly-gate of the HVPMOS on the silicon wafer deviates from the original image on the photomask to left-side, the HV-PMOS will breakdown at a low voltage. On the contrary, the conventional HV-PMOS will cut-off if the image of the poly-gate deviates to right-side, as shown in Fig. 2(a) and (b), respectively. When these phenomena happen, the yield of the HV-PMOS will be greatly reduced. In order to avoid the influence of the lithography misalignments of the HV-PMOS, the left boundary of the designed image of the poly-gate on the photomask must be retracted by the absolute value of the maximum misalignment from the left boundary of the thick-gateoxide film image on the photomask. In this way the phenomenon shown in Fig. 2(a) would be completely
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Fig. 3. Physical correlations of the three images (thick-gateoxide film image, poly-gate image and p-well image) on the photomasks of the novel HV-PMOS.
Fig. 2. Breakdown phenomenon (a) and cut-off phenomenon (b) of the onventional HV-PMOS.
avoided, but the phenomenon shown in Fig. 2(b) would more easily happen. In order to keep the phenomenon from taking place, a p-well was added to the conventional HV-PMOS, as shown in Fig. 1. The p-well could be formed with self-alignment process after the polygate was formed. Fig. 3 showed the physical correlations of the three images (thick-gate-oxide film, poly-gate and p-well) on the photomasks. Here we considered that the maximum values of the lithography misalignment error were ±0.2 lm in the given 0.6 lm rules standard BS CMOS process. The junction depth of the added p-well was 1 lm after the diffusion process, so the right boundary of the p-well would be protracted by 0.8 lm from the left boundary of the thick-gate-oxide film on the silicon wafer. When the maximum lithography misalignment (±0.2 lm) happened, the distance between left boundary of the poly-gate image and that of the thick-gate-oxide film image of the novel HV-PMOS on the silicon wafer would be 0 or 0.4 lm, respectively after the whole fabrication processes, as shown in Fig. 4. Even if the distance was 0.4 lm, the HV-PMOS would never cut off because
Fig. 4. Maximum left and right errors of lithography misalignment between the poly-gate and the thick-gate-oxide film on the wafer.
the p-well can be used as the p+-source junction. With the novel design of the poly-gate image on the photomask and the added p-well, even if the maximum lithography misalignment happened, the novel HV-PMOS could always work safely. One step process was added for the additional p-well. The on-resistance of the HVPMOS increased a little, because the junction of the p-well was shallow, which did not greatly influence the application of the ICs with the proposed HV-PMOS. In this way, the influence of the lithography misalignment was completely eliminated and the yield and reliability of the HV-PMOS were greatly improved.
5. Punch-through of the HV-DNMOS discussion It is important to prevent HV-DNMOS from punching through for the low concentration of the p-substrate. So the p-well was added to the HV-DNMOS in the novel HV-CMOS structure to prevent the punchthrough, as shown in Fig. 1. Fig. 5(a) and (b) show the breakdown potential contours of a conventional HVDNMOS without a p-well and the novel HV-DNMOS
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Fig. 5. Simulated breakdown contours of a conventional HV-DNMOS without a p-well (a) and of the proposed HV-DNMOS with a p-well (b).
with a p-well, respectively, which were obtain from 2D device simulations using MEDICI. The applied voltage conditions in the simulations were as follows, Vsub, Vs and Vg were 0 V, and Vd was a positive high voltage of 100 V. The punch-through happened between the source and n-drift regions of the conventional HV-DNMOS without a p-well when Vd was positive 100 V, as shown in Fig. 5(a). But it is clear from Fig. 5(b) that the punch-through was avoided only because the p-well was added to the HV-DNMOS. In this way, the concentration of the channel and source regions of the HVDNMOS was increased. So the punch-through voltage of the HV-DNMOS was greatly increased, moreover the reliability of the novel HV-CMOS was greatly improved compared with the conventional HV-CMOS.
Although the impurity concentration of the channel region increased with the added p-well, the length of the proposed HV-DNMOS channel could be shorted by several microns compared with that of the conventional HV-DNMOS for the same punch-through voltage. So the whole on-resistance of the presented HV-DNMOS would be improved a little.
6. Experimental results of the HV-CMOS discussion The proposed HV-CMOS was fabricated with the mentioned process in Section 3, which was compatible with 0.6 lm rules standard LV-CMOS process. Fig. 6(a) shows that the experimental distance between the
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Fig. 7. Experimental I–V characteristic curves of the novel HVCMOS with W/L=60 and that of the conventional HV-PMOS without a p-well.
the HV-PMOS to avoiding the cut-off caused by the lithography misalignment. The yields of the proposed HV-PMOS and the HV-CMOS are more than 98% and 95% respectively, but the yield of the conventional HV-CMOS is about 66%. 7. Conclusion
Fig. 6. SEM photograph of the novel HV-PMOS channel region (a) and that of the conventional HV-PMOS channel region (b).
left boundary of the poly-gate and that of the thick-gateoxide film of the novel HV-PMOS is 0.30 lm, which is in the error ranges we have considered in Section 4. Fig. 6(b) shows the experimental distance of the conventional HV-PMOS is 0.08 lm. The conventional HV-PMOS broke down with Vd = 20 V. The experimental results prove the proposed design of the image of the poly-gate on the photomask is very effective to eliminate the influence of the lithography misalignment during the etching the unwanted thick-gate-oxide film of the HV-PMOS. The experimental breakdown characteristic proves the added p-well to the HV-DNMOS is also very effective to prevent the HV-DNMOS from punching through. Fig. 7 shows experimental I–V characteristic results of the proposed HV-CMOS. The breakdown voltage of the novel HV-CMOS exceeds 100 V. The current of the measured HV-PMOS and HV-DNMOS, whose ratios of Width/Length are both 60, are 9.5 mA at Vgs = 10 V and 7 mA at Vgs = 5 V, respectively. But the conventional HV-PMOS without a p-well still cut off under the condition of the Vgs = 10 V and Vd = 100 V, as shown in Fig. 7. The experimental result confirms that the added p-well is very effective to
In this paper, a novel HV-CMOS structure and the compatible BS CMOS process have been proposed. The ways to eliminate the lithography misalignment of the HV-PMOS and to prevent the punch-through of the HV-DNMOS are discussed in detail. The experimental results confirm that the yield and the reliability of the proposed HV-CMOS are greatly improved with the novel design of the image of the poly-gate on the photomask, with the added p-well to avoiding the influence of the lithography misalignment and with that to HVDNMOS for preventing the punch-through. The breakdown voltages of the HV-PMOS and the HV-DNMOS all exceed 100 V. The presented HV-CMOS can be well applied in power driver ICs, etc. Acknowledgments The authors thank the National High Technology Research and Development Program of China (‘‘863’’ Program) for the project and the engineers in Wuxi CSMC Company Limited for their fabricating supported. The authors also would like to thank all referees for their helpful comments and good suggestions. References [1] Baliga BJ. Trends in power semiconductor devices. IEEE Trans Electron Dev 1996;43:1717–31. [2] Finco S, Behrens FH, Castro Simas MI. Smart power IC for DC-DC low power regulation. In: Industry applications
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society annual meeting, Conference record of the 1992 IEEE, vol. 1. 1992. p. 1204–11. [3] Sun WF, Wu JH, Yi YB, Lu SL, Shi LX. High-voltage power integrated circuit technology using bulk-silicon for plasma display panels data driver IC. Microelectron Eng 2004;71:112–8. [4] Tosˇic N, Pesˇic B, Stojadinovic N. HTSL and HTRB reliability testing of power VDMOSFETS. In: Proc. 20th MIELÕ95 Conf., Nis, Yugoslavia; 1995. p. 285. [5] Tosˇic N, Pesˇic B, Stojadinovic N. Reliability testing of power VDMOS transistors. In: International Conference on
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