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Impurity ionization in MOSFETs at very low temperatures
Impurity ionization in MOSFETs at very low temperatures Daniel P. Foty IBM General Technology Division, Essex Junction, VT 05452, USA The physics of freeze-out in conventionally doped silicon is examined. A dynamic equilibrium theory, similar to that used in deep level transient spectroscopy, is developed to describe the time dependence of thermal ionization. The theory is extended to include field-dependent ionization, which accounts for impurity ionization at very low temperatures. The specific mechanisms (Poole - Frenkel ionization and tunnelling) are discussed, and the temperature and field dependences of the mechanisms are described. It is then shown that MOS capacitors and MOSFETs have very different behaviour at very low temperatures. Experimental results are examined, showing a distinct change in the behaviour of long term current transients at very low temperatures, as predicted by the model. The theoretical model developed here, when used in a simple one-dimensional simulation, agrees with substrate current measurements. Finally, some implications for very low temperature MOSFET operation are considered.
Keywords: low temperature electronics; transistors; tunnelling
A decrease in the ambient temperature improves the performance of field effect devices (such as MOSFETs and MODFETs~-7). Some interest has been shown in FET operation at extremely low temperatures (such as liquid helium temperature, 4.2 K) for physical studies 8-~°, to interface with electronics requiring these temperatures ~1-~3 and to gain performance enhancements 14-17. Some studies indicate that MOSFET performance will be optimized in this temperature region j6"~7, However, very low temperatures produce a unique physical environment for MOSFETs; the effect of these conditions must be clearly understood to evaluate accurately MOSFET performance at very low temperatures.
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Physics of freeze-out In conventional silicon MOSFETs, n-channel and pchannel devices are doped with boron and phosphorus. Both phosphorus donor levels and boron acceptor levels are located 0.045 eV from the corresponding band edge ~. At room temperature, this small difference in energy between the dopant level and the band permits the electrons and holes introduced by doping to be excited into the band and to take part in conduction, leaving behind ionized impurities. The carrier concentration as a function of temperature is easily determined by computing the charge neutrality condition in doped silicon ~8. A calculation of the ionized acceptor concentration in non-degenerately boron doped silicon (2.8 × 1016 cm 3) is illustrated in Figure 1. As the temperature drops below ~ 100 K, the ionized impurities act as shallow traps; due to the decrease in ther0011 - 2 2 7 5 / 9 0 / 1 2 1 0 5 6 - 0 8 © 1990 Butterworth - Heinemann ktd
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Cryogenics 1990 Vol 30 December
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100
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Temperature (*K) Figure 1 Ionized impurity concentration non-degenerately boron doped silicon
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mal energy, carriers begin to occupy these shallow levels. As the temperature is lowered further, an increasing fraction of the impurity-introduced carriers are frozen out in these levels. At 0 K, no carriers remain in the bands. For T < 100 K, at any given time a significant fraction of the carriers are frozen out in the shallow traps as discussed above. However, the equilibrium situation is not static, but dynamic. Due to thermal motion, trapped carriers are continually being released into the band. At the same rate, carriers are dropping from the band into the shallow levels.
Impurity ionization in MOSFETs: D.P. Foty Concentrating on an individual electron or hole, when a carrier becomes trapped in a shallow level, it will remain in the trap for a given average amount of time before picking up enough thermal energy to escape. It is necessary to compute the dynamics involved to describe the process properly. This physical situation is very similar to that encountered in deep level transient spectroscopy m, and the dynamic equilibrium theory employed there by Lang can also be used here. A trap level, by it nature, has an emission rate; the average length of time that a carrier spends in a trap before it manages to escape can be found from its inverse I
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where tDT is the dwell time, en.p is the emission rate, U is the energy difference between the shallow trap and the band edge, G.p is a cross section, Vn.p is the thermal velocity, and Nc, v is the density of states. The cross section G.p is a constant for a particular dopant atom 18. Using Equations (1)-(3), the dwell time as a function of temperature for any given dopant can be found. The dwell time for holes in boron doped silicon is presented in Figure 2. The strong temperature dependence is evident; as the temperature decreases, the dwell time rises rapidly. At 10 K, the dwell time for holes has reached --- 1015 s, which is approximately 10 million years. From the data of Figure 2, it is notable (with no field applied) that for T _> 30 K, the dwell time is short in device terms. If a weak field is applied in this temperature range, any free carriers present will be swept out of the region by the applied field. Due to the very short dwell time, any trapped carriers will escape by the thermal cycling process described earlier and be swept out of the field region as well. A depletion region is able to form rapidly. This situation is known as soft or weak freeze-out. This behaviour clearly explains why freeze-out is not a serious concern under normal circumstances at 77 K. Although --- 90 % of the carriers are frozen out in the substrate bulk, a depletion region forms so rapidly that freeze-out introduces no complications to device performance.
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However, when T_< 30 K, the dwell time is very long 2°. If a weak field is applied, there are few free carriers to be swept out of the field region due to nearly complete freeze-out. Due to the long dwell time, the carriers remain in the shallow traps. This is known as hard or strong freeze-out. A depletion region will be unable to form until a time tDT has passed.
Field dependent ionization For device purposes, a MOSFET in the hard freeze-out temperature regime will remain frozen out indefinitely if thermal energy provides the only means of releasing the carriers from the shallow traps. However, while reducing the temperature suppresses thermal mechanisms, fielddependent mechanisms usually (T --- 300 K) too weak to be observed become important 2~. In a frozen-out MOSFET, the application of a field of sufficient strength can induce ionization of trapped carriers and depletion region formation. Two types of field dependent ionization are possible. One mechanism is Poole-Frenkel ionization 22. Consider a carrier trapped in a shallow level (Figure 3). With no field applied, the trapped carrier is in a funnel shaped potential with ionization energy U. When a field is applied, the potential well tilts; the barrier to thermal ionization is lowered by AU to U'. The change in the magnitude of the barrier depends entirely on the field; the magnitude of the barrier is calculated f r o m 22
(4)
U' = U - A U = U - 2q(qF/~si) ''~
where q is the magnitude of the electron charge, ~s~ is the silicon dielectric constant, and F is the field strength. The carrier can now be thermally excited over the barrier (Figure 3b). Although the applied field lowers the potential barrier, the actual carrier escape mechanism is still a thermal one; for this reason, Poole-Frenkel ionization can be referred to (for present purposes) as field-assisted thermal ionization. For a given applied field F, AU and U' can be computed; the value of U' can then be inserted into Equation (2) (in place of U) and the effect of the application of a field on the dwell time examined. A plot of the dwell time for holes in boron doped silicon under various applied fields is shown in Figure 4. It can readily be observed that, as expected, as the field is increased, the dwell time decreases. The interplay between temperature and field
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Cryogenics 1990 Vol 30 December
1057
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is also apparent. At higher temperatures, the (relatively) large amount of thermal energy leads to a short dwell time; the field serves mainly to remove the escaping holes. At the limit of F = 3 . 3 x 103V cm -], the field has eliminated the potential well and the formerly trapped hole is free to be swept away. At lower temperatures, there is little thermal energy to excite the trapped hole out of the well. The lowering of the barrier by the applied field is required if the hole is to escape. It is obvious from Figure 4 that at very low temperatures the dwell time is a sensitive function of the applied field. This is made clear in Figure 5; the dwell time is strongly affected by the magnitude of the field at lower temperatures. This applied field makes ionization possible under these conditions. A second possible field-dependent ionization mechanism is tunnelling. As in the case of field-assisted thermal ionization, an applied field alters the funnel-shaped potential presented to the trapped carrier; at sufficient field strength, the carrier is able to tunnel through the barrier into the band and be swept away by the field (Figure 6). Tunnelling is a weakly temperature-dependent process, and can thus be labelled as field-induced ionization.
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Cryogenics 1990 Vol 30 December
As the particle travels back and forth in the well, it will strike both walls. However, it will be unable to tunnel through the side of the well raised by the applied field (since there are no states for the particle to tunnel into). It can tunnel through the lowered barrier side of the well (as described above). Thus the mean free path for tunnelling is twice the conf'mement length (i.e. twice the width of the well). Combining Equations (7) and (8), the mean time between collisions with the tunnelling barrier is (t) = 2r/(v)
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The dwell time is found from the inverse of en.p as in Equation (1). This approach is approximate, but allows a simple calculation (instead of an exact solution using Fermi's second 'golden rule'24). The tunnelling dwell time as a function of field is presented in Figure 7. As discussed above, tunnelling is a weakly temperature dependent mechanism. However, in contrast to the Poole-Frenkel dwell time, the tunnelling dwell time is an extremely sensitive function of field. The barrier presented to the trapped hole must be very small for significant tunnelling to occur. In Poole-Frenkel ionization, the 'escape mechanism' is thermal excitation, whereas tunnelling is almost entirely a field dependent process. It would be expected that, as
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Figure 8 Poole - Frenkel dwell time v e r s u s applied field for holes in boron doped silicon: - - , tunnelling limit; . . . . . , T = 4 K; ---, T = 3 O K ; . . . . , T = 2 O K ; - - - - - - , T = 10 K; . . . . . , T=4K
the temperature decreases, Poole-Frenkel ionization diminishes in importance, allowing tunnelling to become more prominent. An attempt is made to demonstrate this occurrence in Figure 8. The solid line represents the (relatively) temperature independent tunnelling dwell time, while the dashed lines represent the Poole--Frenkel dwell time for 40, 30, 20, 10 and 4 K. Low fields and higher temperatures favour Poole-Frenkel ionization, while high fields and low temperatures favour tunnelling. Particular temperature/field combinations exist at which the predominant mechanism will change; the crossing points in Figure 8 are examples. During field dependent ionization, the temperature is held constant, while the field at some point in the protodepletion region is increasing as ionization proceeds. The dwell time for a trapped carrier is found by sliding along an isotherm in Figure 8 until the tunnelling limit is reached; lor larger field strengths, the tunnelling dwell time describes the process. MOS
capacitors
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MOSFETs
The simplest system in which to study field dependent ionization is the MOS capacitor; this was the subject of an earlier work by Saks and Nordbryhn 25. Consider an nMOS capacitor. Before the application of a gate bias at very low temperature, the structure is in equilibrium; the substrate is in hard freeze-out and there is no field in the structure. When a positive d.c. gate bias is applied, no depletion region forms: the substrate dopant atoms retain their carriers (in the initial condition). Also, since there are no minority carriers present in the substrate, no inversion layer forms. Thus there are neither free carriers nor ionized impurities in the substrate, and it remains neutral with respect to charge. However, there is now a voltage drop between the positively charged gate contact and the grounded substrate contact. Since the substrate is much thicker than the oxide, most of the voltage is dropped across the substrate. This leads to a uniform field across the substrate (the field is larger in the oxide due to the different dielectric constant there). As field-dependent ionization begins, a few carriers reach the substrate contact. As the process proceeds, the uncovered ions in the substrate increase the field strength, which increases the ionization. This is detected as an increase in the substrate current. As ionization approaches completion (full depletion region formation), there are no longer any substrate dopant atoms to ionize, and the substrate current decreases. This peaking of the substrate current is one of the hallmarks of field dependent ionization. In the earlier study 25, it was found that, by monitoring the substrate current, the time to the completion of field dependent ionization increased from nanoseconds at 25 K to milliseconds at 14 K. This variation with temperature correlates with the theoretical contention presented above that, in the temperature range studied in Reference 25 and here, the field dependent ionization process is dominated by Poole-Frenkel ionization (field assisted thermal ionization). In a MOS capacitor, the process of field dependent depletion region formation is rapid. The formation of an inversion layer will be a more lengthy process 26. A study of transient behaviour in diodes led to similar
Cryogenics 1990 Vol 30 December
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Impurity ionization in MOSFETs: D.P. Foty results zT'zS. When a reverse bias is applied (which will have the effect of enlarging the depletion region), the depletion region does not form immediately. The field in the region lowers the barrier to ionization, allowing trapped carrier emission by the Poole-Frenkel process. This increases the field strength, which increases the ionization rate, with the process continuing until the steady-state depletion region is formed. As in the case of the MOS capacitor, the increasing ionization rate, followed by an exhaustion of the supply of trapped carriers, leads to a transient peak in the observed current. Since, as in a MOS capacitor, there is a substantial field in the frozenout region at t = 0, the process of ionization is relatively rapid; transients of the order of hundreds of microseconds were observed at T = 20 K (References 27, 28). Although the basic physical processes are the same, the structure of a MOSFET leads to a very different field distribution from that found in a MOS capacitor, and a very different situation. Consider an n-channel MOSFET in hard freeze-out. When a positive gate bias is applied, no depletion region forms in the substrate under the gate as discussed above. However, the source/drain wells are degenerately doped and are not frozen out for any temperature. The applied positive gate bias pulls electrons out of the source/drain wells, forming a sheet of negative charge under the gate. In this manner, an inversion layer has formed without any contribution from the bulk substrate. This process produces a unique situation. The negative charge sheet under the gate compensates entirely for the positive charge on the gate contact. Below the negative charge sheet, there is no free or fixed charge and, therefore, no field. The applied bias is dropped entirely across the oxide. As a consequence, the field in the structure is contained entirely in the oxide as well. In this situation, field-dependent ionization in the substrate will be slow to begin; additionally, a considerable amount of time will be required for the process to approach completion.
MOSFET steady state In the hard freeze-out regime, a MOSFET will be operating in a non-steady state condition. If sufficient time is allowed to pass, the device will eventually reach a steady state (fully formed inversion layer and depletion regions whose charge concentrations no longer vary with time) for the given operating conditions. For field-dependent ionization of substrate dopants to be complete, a given volume of material must be swept clean of frozen-out carriers. The extent of the depletion region when thisprocess is complete (steady state) may be found easily'L The dimensions of the depletion region are not strongly dependent on temperature, and no unusual conditions occur. There is a slight increase in the depletion region volume as the temperature is lowered; a slightly larger volume of substrate material must be depleted to reach a steady state at low temperature than at room temperature.
Experimental Up to this point, this discussion has only dealt with the theory of field dependent ionization. When an attempt is
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Cryogenics 1990 Vol 30 December
made to observe experimentally the results of this phenomenon in MOSFETs, a problem arises which greatly complicates the measurement. When d.c. gate and drain biases are applied to a MOSFET at very low temperatures, the greatly reduced value (from room temperature) of the substrate heat capacity leads to large rises in device temperature due to power dissipation 3°'31. This phenomenon manifests itself in large changes in the drain current with time as the device temperature rises. Under these conditions, the device is not in a steady state due to thermal variation. The nonsteady-state behaviour due to field-dependent ionization cannot be observed for two reasons: the changes in the drain current due to device self-heating make it impossible to isolate changes due to field dependent ionization; and the change in the device temperature alters the conditions of substrate ionization. If the d.c. gate bias is replaced with a square wave gate bias, the power dissipation is obviously reduced by 50%. Additionally, it has been found experimentally that as the frequency of the square wave is increased, the magnitude of device self-heating is reduced. It is postulated that the alternating bias reduces localized heating near the drain and thus prevents a sharp rise in device temperature. When the frequency of the square wave gate bias has reached 1 MHz, heating is reduced sufficiently to permit observation of current transients due to field-dependent ionization; the gate bias was employed throughout these experiments, while a d.c. drain bias is used. Devices used in this study had the following parameters: tox = 120 nm; n-channel W/L = 190/4.00 #m; p-channel W/L = 495/6.35 #m; NA = 2.8 × 10 ~6 cm-3; N D = 3.0 × 1015 cm -3
Experiment and model When device self-heating is removed as a concern, transient behaviour due to hard freeze-out and slow fielddependent ionization can be observed. A full presentation of experimental results was published earlier 1°. At 13 K, the device drain current decreases with time (as shown for an nFET in Figure 9). This is due to the slow formation of the depletion layer, which leads to a transient higher conductivity inversion layer. This is the
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opposite behaviour to the increasing current transient that is produced by device self-heating 3°. These results agree with those reported by Grupen and Viswanathan 32, who developed a Poole-Frenkel model, which they used in a full-scale device simulation to describe the measured results with good accuracy. Similar results were also reported by Tewksbury 33. At 30 K, the Poole-Frenkel dwell time is very short. Since the substrate is not in the hard freeze-out regime, field dependent ionization should not play a role in device behaviour. Instead of a decreasing current transient due to field dependent ionization, an increasing current transient due to device self-heating is produced (Figure 10) 3°'31. This is consistent with the theoretical predictions presented earlier. As noted above, carriers released by field dependent ionization reach the substrate contact and are detected as substrate current 25. Thus, the substrate current serves as a monitor of the ionization process. A typical experimental result for a pFET is found in Figure 11. The peak in the
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substrate current due to field-dependent ionization is clearly evident. Using the model developed earlier for field-dependent ionization, a one-dimensional simulation of the process can be carried out. It is assumed that, at t = 0, all the carriers in the substrate are frozen out. The time is incremented and, from the field distribution and the equations presented earlier, the ionization probability and the ionized impurity profile are computed. From this profile, a new field distribution is calculated. This iterative process continues until the depletion region is fully formed. A typical result is presented in Figure 12. The model is able to reproduce the key feature of the experimental result, a transient which peaks at a time of the order of tens of seconds. Note that the model does not take into account substrate current due to impact ionization in the operating device.
Discussion
Due to the basic physics of semiconductor materials, a dynamic equilibrium exists during freeze-out. In conventionally doped material, this leads to a hard freeze-out regime for T < 30 K, in which the dwell time for a frozenout carrier is very long. Instead, field dependent ionization is required to release frozen-out carriers. The theoretical approach developed here clearly shows that Poole-Frenkel ionization is the predominant ionization mechanism at 'intermediate' temperatures (10-30 K). Tunnelling dominates when the temperature is too low for Poole-Frenkel ionization (field-assisted thermal ionization). In some situations, Poole-Frenkel ionization will dominate up to a particular field strength, after which tunnelling dominates for higher fields. The equations developed here interpret field dependent ionization on the basis of temperature and field, in a fashion similar to that developed for deep level transient spectroscopy. These equations describe the physical phenomena locally in the material; in this form, they should be readily applicable in typical large-scale device simulation programs. Examination of the theoretical framework and the
Cryogenics 1990 Vol 30 December
1061
Impurity ionization in MOSFETs: D.P. Foty experimental results indicate that conventionally doped MOSFETs will behave very differently for T _< 30 K. In particular, significant long-term transient effects (as discussed in References 10, 30 and 31) will be a major factor in device behaviour. Besides field dependent ionization t° and thermal effects 3°'3~, other difficulties (such as Anderson localization 34 and I - V hysteresis due to interface trapping 35) are encountered, leading to potentially illusory indications of sharp improvements in device performance for T < 30 K. These effects must be understood and taken into account in both studies and applications of MOSFETs at very low temperatures.
2 Yao, C., Tzou, J., Cheung, R. and Chan, II. Temperature
Summary
8
This paper has examined the effect of substrate freezeout on MOSFET behaviour at very low temperatures. After a brief discussion of freeze-out, dynamic equilibrium theory similar to that used for deep level transient spectroscopy was applied to identify the hard freeze-out regime in conventionally doped MOSFETs for T <_ 30 K, in which a depletion region is unable to form normally due to the long time required for thermal ionization. Field dependent ionization was then discussed, with Poole-Frenkel ionization (field assisted thermal ionization) and tunnelling (field induced ionization) examined as the specific mechanisms. Calculations were presented showing the effect of temperature and field on the dwell time. Specific values of temperature and field that favoured either Poole-Frenkel ionization or tunnelling were identified. To compare the theoretical development with experimental results, it was shown that the field distribution under hard freeze-out is very different in MOS capacitors and MOSFETs, leading to a prediction of slow depletion region formation in MOSFETs at very low temperatures. These predictions were verified by demonstrating a sharp difference in the behaviour of long-term drain current transients at and below 30 K. The long-term substrate current transient, a monitor of field dependent ionization, was presented, and it was shown that the model developed here can be used in a simple one-dimensional simulation to produce results similar to those found experimentally. Finally, some of the implications for basic semiconductor physics and very low temperature MOSFET operation were discussed.
Acknowledgements Thanks are due to P. Wyns of Hewlett-Packard, Colorado Integrated Circuit Division, Fort Collins, CO, D. Cole of IBM General Technology Division, Essex Junction, VT, and M. Wordeman of the IBM T.J. Watson Research Center, Yorktown Heights, NY, for extensive discussions of this work. Thanks are also due to M. Marceau, P. Cottrell, and J. Hiltebeitel of IBM General Technology Division, Essex Junction, VT, for interest and helpful assistance and to D. Gentes of IBM General Technology Division, Essex Junction, VT, for editorial assistance.
References Gildenblat, G., Colonna-Romano, L., Lau, D. and Nelsen, D. Investigation of cryogenic CMOS performance IEDM Tech Dig (1985) 268-271
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Cryogenics 1990 Vol 30 December
dependence of latch-up characteristics in LDD CMOS devices IEEE Elec Dev Lett (1986) EDL-7 92-94 3 Colonna-Romano, L. and Deverell, D. Operation of a CMOS microprocessor while immersed in liquid nitrogen IEEE J Sol St Circ (1986) SC-21 491-492 4 Woo, J. and Hummer, J. Short-channel-effectsin MOSFETs at liquidnitrogen temperature IEEE Trans Elec Dev (1986) ED-33 1012 - 1019 5 Aoki, M., Hanamura, S., Masuhara, T. and Yano, K. Performance and hot carrier effects of small CRYO-CMOS devices, IEEE Trans Elec Dev (1987) ED-34 8-18 6 0 n g , T., Ko, P. and Hu, C. 50-A gate oxide MOSFETs at 77 K IEEE Trans Elec Dev (1987) ED-34 2129-2135
7 Nishiuchi, K., Kobayashi, N., Kuroda, S., Notami, S., Mimura,
9
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13
14
15
T., Abe, M. and Kobayashi, M. A subnanosecondHEMT 1-kbit static RAM 1EEE J Sol St Circ (1986) SC-21 869-874 Tewksbury, S., Biazzo, M., Harrison, T., Lindstrom, T., Tennant, D. and Storz, F. Static and nonequilibrium transient conductance at strong freeze-out in a buried channel metal-oxide-semiconductor transistor J Appl Phys (1984) 56 511-516 Balestra, F., Audaire, L. and Lucas, C. Influence of substrate freezeoat on the characteristics of MOS transistors at very low temperatures Sol St Elec (1987) 30 321-327 Foty, D. and Titcomb, S. Substrate freeze-out and field dependent donor acceptor ionization in MOSFETs at very low temperatures Proc Symposium on Low Temperature Electronics and High Temperature Superconductors The Electrochemical Society Inc., Pennington, NJ, USA (1988) 151-160 Mannhart, J., Parisi, J., Mayer, K. and Huebener, R. A new cryoelectronic device family IEEE Trans Elec Dev (1987) ED-34 1802 - 1806 Broadbent, S. Operation of CMOS devices at 10 Kelvin Proc Symposium on Low Temperature Electronics and High Temperature Superconductors The Electrochemical Society Inc., Pennington, NJ, USA (1988) 170-176 Seib, D. Cryogenic electronics for infrared focal plane arrays Proc Symposium on Low Temperature Electronics and High Temperature Superconductors The Electrochemical Society Inc., Pennington, NJ, USA (1988) 499-517 Robertson, P. and Dumin, D. Ballistic transport and properties of submicrometer silicon MOSFETs from 300 to 4.2 K IEEE Trans Elec Dev (1986) ED-33 494-498 Heiblum, M., Nathan, M., Thomas, D. and Knoedler, K. Direct observation of ballistic transport in GaAs Phys Rev Lett (1985) 55 2200- 2203
16 Hanamura, S., Aoki, M., Masuhara, T., Minato, O., Sakai, Y. and Hayashida, T. Operation of bulk CMOS devices at very low temperatures lEEE J. Sol. St. Circ (1986) SC-21 484-490 17 Laramee, J., Aubin, M. and Cheeke, J. Behaviour of CMOS inverters at cryogenic temperatures Sol St Elec (1985) 28 453-456 18 Sze, S. Physics of Semicooductor Devices 2nd Edn, John Wiley & Sons Inc., New York, USA (1981) 19 Lang, D. Deep-level transient spectroscopy: a new method to characterize traps in semiconductorsJ Appl Phys (1974) 45 3023 -3032 20 Tewksbury, S., Biazzo, M. and Lindstrom, T. Strong carrier freezeout above 77 K in tellurium-dopedburied-channelMOS transistors IEEE Trans Elec Dev (1985) ED-32 67-69 21 Wyns, P. and Anderson, R. Low-temperature operation of silicon dynamic randon-access memories IEEE Trans Elec Dev (1989) ED-36 1423-1428 22 Frenkel, J. On the breakdown phenomena in insulators and electronic semiconductors Phys Rev (1938) 54 647-648 23 Anderson, E. Modern Physics and Quantum Mechanics W.B. Saunders Company, Philadelphia, USA (1971) 24 Schiff, L. Quantum Mechanics 3rd Edn, McGraw-Hill Inc., New York, USA (1968) 25 Saks, N. and Nordbryhn, A. Time dependence of depletion region formation in phosphorus doped silicon MOS devices at cryogenic temperatures J Appl Phys (1979) 50 6962-6968 26 Goetzberger, A. Behavior of MOS inversion layers at low temperture IEEE Trans Elec Dev (1967) ED-14 787-789 27 Rosencher, E., Mosser, V. and Vincent, G. Ionization transients of shallow levels in silicon space charge layer at low temperature Sol St Commun (1983) 45 629-632 28 Rosencher, E., Mosser, V. and Vincent, G. Transient-current study of field-assisted emission from shallow levels in silicon Phys Rev B (1984) 29 1135-1147 29 Nguyen-Doc, Ch., Cristoloveanu, S. and Ghibaudo, G. Low temperature mobility behavior in submicron MOSFETs and related
Impurity ionization in MOSFETs: D.P. Foty determination of channel length and series resistance Sol St Elec (1986) 29 1271 - 1277 30 Foty, D. and Titcomb, S. Thermal effects in n-channel enhancement MOSFETs operated at cryogenic temperatures 1EEE Trans Elec Dev (1987) ED-34 1 0 7 - 113 31 Foty, D. Thermal effects in p-channel MOSFETs at low temperatures IEEE Trans Elec Dev (1989) ED-36 1542-1544 32 Grupen, M. and Viswanathan, C. A numerical simulation of the transient drain current in a MOST at cryogenic temperatures Proc Workshop on Low Temperature Electronics IEEE, Piscataway, NJ, USA (1989) 63 - 6 7
33 Tewksbury, S. Formation of high density electron-hole plasma in silicon metal-oxide-semiconductor transistors below 25 K J Appl Phys (1983) 54 8 6 8 - 8 7 5 34
Kawaguchi, Y., Suzuki, T. and Kawaji, S. Carrier concentration dependence and temperature dependence of mobility in silicon (100) n-channel inversion layers at low temperatures Sol St Commun (1980) 36 2 5 7 - 2 5 9
35 Rogers, C. MOSTs at cryogenic temperatures Sol St Elec (1968) 11 1079- 1091
Cryogenics 1990 Vol 30 December
1063
Keywords: low temperature electronics; transistors; tunnelling
A decrease in the ambient temperature improves the performance of field effect devices (such as MOSFETs and MODFETs~-7). Some interest has been shown in FET operation at extremely low temperatures (such as liquid helium temperature, 4.2 K) for physical studies 8-~°, to interface with electronics requiring these temperatures ~1-~3 and to gain performance enhancements 14-17. Some studies indicate that MOSFET performance will be optimized in this temperature region j6"~7, However, very low temperatures produce a unique physical environment for MOSFETs; the effect of these conditions must be clearly understood to evaluate accurately MOSFET performance at very low temperatures.
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Physics of freeze-out In conventional silicon MOSFETs, n-channel and pchannel devices are doped with boron and phosphorus. Both phosphorus donor levels and boron acceptor levels are located 0.045 eV from the corresponding band edge ~. At room temperature, this small difference in energy between the dopant level and the band permits the electrons and holes introduced by doping to be excited into the band and to take part in conduction, leaving behind ionized impurities. The carrier concentration as a function of temperature is easily determined by computing the charge neutrality condition in doped silicon ~8. A calculation of the ionized acceptor concentration in non-degenerately boron doped silicon (2.8 × 1016 cm 3) is illustrated in Figure 1. As the temperature drops below ~ 100 K, the ionized impurities act as shallow traps; due to the decrease in ther0011 - 2 2 7 5 / 9 0 / 1 2 1 0 5 6 - 0 8 © 1990 Butterworth - Heinemann ktd
1056
Cryogenics 1990 Vol 30 December
1
100
200
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Temperature (*K) Figure 1 Ionized impurity concentration non-degenerately boron doped silicon
versus
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mal energy, carriers begin to occupy these shallow levels. As the temperature is lowered further, an increasing fraction of the impurity-introduced carriers are frozen out in these levels. At 0 K, no carriers remain in the bands. For T < 100 K, at any given time a significant fraction of the carriers are frozen out in the shallow traps as discussed above. However, the equilibrium situation is not static, but dynamic. Due to thermal motion, trapped carriers are continually being released into the band. At the same rate, carriers are dropping from the band into the shallow levels.
Impurity ionization in MOSFETs: D.P. Foty Concentrating on an individual electron or hole, when a carrier becomes trapped in a shallow level, it will remain in the trap for a given average amount of time before picking up enough thermal energy to escape. It is necessary to compute the dynamics involved to describe the process properly. This physical situation is very similar to that encountered in deep level transient spectroscopy m, and the dynamic equilibrium theory employed there by Lang can also be used here. A trap level, by it nature, has an emission rate; the average length of time that a carrier spends in a trap before it manages to escape can be found from its inverse I
/DT = en, p en. p =
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(2)
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where tDT is the dwell time, en.p is the emission rate, U is the energy difference between the shallow trap and the band edge, G.p is a cross section, Vn.p is the thermal velocity, and Nc, v is the density of states. The cross section G.p is a constant for a particular dopant atom 18. Using Equations (1)-(3), the dwell time as a function of temperature for any given dopant can be found. The dwell time for holes in boron doped silicon is presented in Figure 2. The strong temperature dependence is evident; as the temperature decreases, the dwell time rises rapidly. At 10 K, the dwell time for holes has reached --- 1015 s, which is approximately 10 million years. From the data of Figure 2, it is notable (with no field applied) that for T _> 30 K, the dwell time is short in device terms. If a weak field is applied in this temperature range, any free carriers present will be swept out of the region by the applied field. Due to the very short dwell time, any trapped carriers will escape by the thermal cycling process described earlier and be swept out of the field region as well. A depletion region is able to form rapidly. This situation is known as soft or weak freeze-out. This behaviour clearly explains why freeze-out is not a serious concern under normal circumstances at 77 K. Although --- 90 % of the carriers are frozen out in the substrate bulk, a depletion region forms so rapidly that freeze-out introduces no complications to device performance.
102 s
However, when T_< 30 K, the dwell time is very long 2°. If a weak field is applied, there are few free carriers to be swept out of the field region due to nearly complete freeze-out. Due to the long dwell time, the carriers remain in the shallow traps. This is known as hard or strong freeze-out. A depletion region will be unable to form until a time tDT has passed.
Field dependent ionization For device purposes, a MOSFET in the hard freeze-out temperature regime will remain frozen out indefinitely if thermal energy provides the only means of releasing the carriers from the shallow traps. However, while reducing the temperature suppresses thermal mechanisms, fielddependent mechanisms usually (T --- 300 K) too weak to be observed become important 2~. In a frozen-out MOSFET, the application of a field of sufficient strength can induce ionization of trapped carriers and depletion region formation. Two types of field dependent ionization are possible. One mechanism is Poole-Frenkel ionization 22. Consider a carrier trapped in a shallow level (Figure 3). With no field applied, the trapped carrier is in a funnel shaped potential with ionization energy U. When a field is applied, the potential well tilts; the barrier to thermal ionization is lowered by AU to U'. The change in the magnitude of the barrier depends entirely on the field; the magnitude of the barrier is calculated f r o m 22
(4)
U' = U - A U = U - 2q(qF/~si) ''~
where q is the magnitude of the electron charge, ~s~ is the silicon dielectric constant, and F is the field strength. The carrier can now be thermally excited over the barrier (Figure 3b). Although the applied field lowers the potential barrier, the actual carrier escape mechanism is still a thermal one; for this reason, Poole-Frenkel ionization can be referred to (for present purposes) as field-assisted thermal ionization. For a given applied field F, AU and U' can be computed; the value of U' can then be inserted into Equation (2) (in place of U) and the effect of the application of a field on the dwell time examined. A plot of the dwell time for holes in boron doped silicon under various applied fields is shown in Figure 4. It can readily be observed that, as expected, as the field is increased, the dwell time decreases. The interplay between temperature and field
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Potential profiles for acarrler frozen out in an impurity well: (a) no applied field; (b) with an applied field, showing barrier lowering and P o o l e - Frenkel ionization
Cryogenics 1990 Vol 30 December
1057
Impurity ionization in MOSFETs: D.P. Foty 1025 102°
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Figure 4
Poole - Frenkel d w e l l t i m e v e r s u s t e m p e r a t u r e f o r h o l e s in b o r o n d o p e d s i l i c o n w i t h an applied field: - - , F = O; . . . . . , F = 10 V c m - 1 ; - - - , F = 1 0 0 V c m - 1 ; .... , F = 1000 V cm-1; -----, F = 3000 V cm-1; ..... , F = 3 3 0 0 V c m -1
is also apparent. At higher temperatures, the (relatively) large amount of thermal energy leads to a short dwell time; the field serves mainly to remove the escaping holes. At the limit of F = 3 . 3 x 103V cm -], the field has eliminated the potential well and the formerly trapped hole is free to be swept away. At lower temperatures, there is little thermal energy to excite the trapped hole out of the well. The lowering of the barrier by the applied field is required if the hole is to escape. It is obvious from Figure 4 that at very low temperatures the dwell time is a sensitive function of the applied field. This is made clear in Figure 5; the dwell time is strongly affected by the magnitude of the field at lower temperatures. This applied field makes ionization possible under these conditions. A second possible field-dependent ionization mechanism is tunnelling. As in the case of field-assisted thermal ionization, an applied field alters the funnel-shaped potential presented to the trapped carrier; at sufficient field strength, the carrier is able to tunnel through the barrier into the band and be swept away by the field (Figure 6). Tunnelling is a weakly temperature-dependent process, and can thus be labelled as field-induced ionization.
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With tunnelling as the ionization mechanism, the dwell time for a trapped hole presents a more complicated problem than that found for Poole-Frenkel ionization; however, a reasonable result may be computed as follows. The applied bias alters the shape of the potential well (as in Poole-Frenkel ionization); this stipulates that Equation (4) be used to produce the probability of tunnelling occurring per collision with the well wall under the applied bias. The effective well width may be found from Bohr theory for hydrogen-like atoms. The effective Bohr radius may be found by using the effective mass
Cryogenics 1990 Vol 30 December
As the particle travels back and forth in the well, it will strike both walls. However, it will be unable to tunnel through the side of the well raised by the applied field (since there are no states for the particle to tunnel into). It can tunnel through the lowered barrier side of the well (as described above). Thus the mean free path for tunnelling is twice the conf'mement length (i.e. twice the width of the well). Combining Equations (7) and (8), the mean time between collisions with the tunnelling barrier is (t) = 2r/(v)
(9)
The probability of a tunnelling event occurring per collision with the appropriate wall of the well is found from
Impurity ionization in MOSFETs: D.P. Foty 1025 1020 1015 I .~
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the WKB approximation for a parabolic potential barrier t8 Tt = exp [ - 7r(m*)1/2U'3/2/2(2)t/2qhF]
(10)
where U' is inserted from Equation (4). Therefore, the tunnelling emission rate is
en,p = ~ / ( t )
(l l)
The dwell time is found from the inverse of en.p as in Equation (1). This approach is approximate, but allows a simple calculation (instead of an exact solution using Fermi's second 'golden rule'24). The tunnelling dwell time as a function of field is presented in Figure 7. As discussed above, tunnelling is a weakly temperature dependent mechanism. However, in contrast to the Poole-Frenkel dwell time, the tunnelling dwell time is an extremely sensitive function of field. The barrier presented to the trapped hole must be very small for significant tunnelling to occur. In Poole-Frenkel ionization, the 'escape mechanism' is thermal excitation, whereas tunnelling is almost entirely a field dependent process. It would be expected that, as
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Figure 8 Poole - Frenkel dwell time v e r s u s applied field for holes in boron doped silicon: - - , tunnelling limit; . . . . . , T = 4 K; ---, T = 3 O K ; . . . . , T = 2 O K ; - - - - - - , T = 10 K; . . . . . , T=4K
the temperature decreases, Poole-Frenkel ionization diminishes in importance, allowing tunnelling to become more prominent. An attempt is made to demonstrate this occurrence in Figure 8. The solid line represents the (relatively) temperature independent tunnelling dwell time, while the dashed lines represent the Poole--Frenkel dwell time for 40, 30, 20, 10 and 4 K. Low fields and higher temperatures favour Poole-Frenkel ionization, while high fields and low temperatures favour tunnelling. Particular temperature/field combinations exist at which the predominant mechanism will change; the crossing points in Figure 8 are examples. During field dependent ionization, the temperature is held constant, while the field at some point in the protodepletion region is increasing as ionization proceeds. The dwell time for a trapped carrier is found by sliding along an isotherm in Figure 8 until the tunnelling limit is reached; lor larger field strengths, the tunnelling dwell time describes the process. MOS
capacitors
and
MOSFETs
The simplest system in which to study field dependent ionization is the MOS capacitor; this was the subject of an earlier work by Saks and Nordbryhn 25. Consider an nMOS capacitor. Before the application of a gate bias at very low temperature, the structure is in equilibrium; the substrate is in hard freeze-out and there is no field in the structure. When a positive d.c. gate bias is applied, no depletion region forms: the substrate dopant atoms retain their carriers (in the initial condition). Also, since there are no minority carriers present in the substrate, no inversion layer forms. Thus there are neither free carriers nor ionized impurities in the substrate, and it remains neutral with respect to charge. However, there is now a voltage drop between the positively charged gate contact and the grounded substrate contact. Since the substrate is much thicker than the oxide, most of the voltage is dropped across the substrate. This leads to a uniform field across the substrate (the field is larger in the oxide due to the different dielectric constant there). As field-dependent ionization begins, a few carriers reach the substrate contact. As the process proceeds, the uncovered ions in the substrate increase the field strength, which increases the ionization. This is detected as an increase in the substrate current. As ionization approaches completion (full depletion region formation), there are no longer any substrate dopant atoms to ionize, and the substrate current decreases. This peaking of the substrate current is one of the hallmarks of field dependent ionization. In the earlier study 25, it was found that, by monitoring the substrate current, the time to the completion of field dependent ionization increased from nanoseconds at 25 K to milliseconds at 14 K. This variation with temperature correlates with the theoretical contention presented above that, in the temperature range studied in Reference 25 and here, the field dependent ionization process is dominated by Poole-Frenkel ionization (field assisted thermal ionization). In a MOS capacitor, the process of field dependent depletion region formation is rapid. The formation of an inversion layer will be a more lengthy process 26. A study of transient behaviour in diodes led to similar
Cryogenics 1990 Vol 30 December
1059
Impurity ionization in MOSFETs: D.P. Foty results zT'zS. When a reverse bias is applied (which will have the effect of enlarging the depletion region), the depletion region does not form immediately. The field in the region lowers the barrier to ionization, allowing trapped carrier emission by the Poole-Frenkel process. This increases the field strength, which increases the ionization rate, with the process continuing until the steady-state depletion region is formed. As in the case of the MOS capacitor, the increasing ionization rate, followed by an exhaustion of the supply of trapped carriers, leads to a transient peak in the observed current. Since, as in a MOS capacitor, there is a substantial field in the frozenout region at t = 0, the process of ionization is relatively rapid; transients of the order of hundreds of microseconds were observed at T = 20 K (References 27, 28). Although the basic physical processes are the same, the structure of a MOSFET leads to a very different field distribution from that found in a MOS capacitor, and a very different situation. Consider an n-channel MOSFET in hard freeze-out. When a positive gate bias is applied, no depletion region forms in the substrate under the gate as discussed above. However, the source/drain wells are degenerately doped and are not frozen out for any temperature. The applied positive gate bias pulls electrons out of the source/drain wells, forming a sheet of negative charge under the gate. In this manner, an inversion layer has formed without any contribution from the bulk substrate. This process produces a unique situation. The negative charge sheet under the gate compensates entirely for the positive charge on the gate contact. Below the negative charge sheet, there is no free or fixed charge and, therefore, no field. The applied bias is dropped entirely across the oxide. As a consequence, the field in the structure is contained entirely in the oxide as well. In this situation, field-dependent ionization in the substrate will be slow to begin; additionally, a considerable amount of time will be required for the process to approach completion.
MOSFET steady state In the hard freeze-out regime, a MOSFET will be operating in a non-steady state condition. If sufficient time is allowed to pass, the device will eventually reach a steady state (fully formed inversion layer and depletion regions whose charge concentrations no longer vary with time) for the given operating conditions. For field-dependent ionization of substrate dopants to be complete, a given volume of material must be swept clean of frozen-out carriers. The extent of the depletion region when thisprocess is complete (steady state) may be found easily'L The dimensions of the depletion region are not strongly dependent on temperature, and no unusual conditions occur. There is a slight increase in the depletion region volume as the temperature is lowered; a slightly larger volume of substrate material must be depleted to reach a steady state at low temperature than at room temperature.
Experimental Up to this point, this discussion has only dealt with the theory of field dependent ionization. When an attempt is
1060
Cryogenics 1990 Vol 30 December
made to observe experimentally the results of this phenomenon in MOSFETs, a problem arises which greatly complicates the measurement. When d.c. gate and drain biases are applied to a MOSFET at very low temperatures, the greatly reduced value (from room temperature) of the substrate heat capacity leads to large rises in device temperature due to power dissipation 3°'31. This phenomenon manifests itself in large changes in the drain current with time as the device temperature rises. Under these conditions, the device is not in a steady state due to thermal variation. The nonsteady-state behaviour due to field-dependent ionization cannot be observed for two reasons: the changes in the drain current due to device self-heating make it impossible to isolate changes due to field dependent ionization; and the change in the device temperature alters the conditions of substrate ionization. If the d.c. gate bias is replaced with a square wave gate bias, the power dissipation is obviously reduced by 50%. Additionally, it has been found experimentally that as the frequency of the square wave is increased, the magnitude of device self-heating is reduced. It is postulated that the alternating bias reduces localized heating near the drain and thus prevents a sharp rise in device temperature. When the frequency of the square wave gate bias has reached 1 MHz, heating is reduced sufficiently to permit observation of current transients due to field-dependent ionization; the gate bias was employed throughout these experiments, while a d.c. drain bias is used. Devices used in this study had the following parameters: tox = 120 nm; n-channel W/L = 190/4.00 #m; p-channel W/L = 495/6.35 #m; NA = 2.8 × 10 ~6 cm-3; N D = 3.0 × 1015 cm -3
Experiment and model When device self-heating is removed as a concern, transient behaviour due to hard freeze-out and slow fielddependent ionization can be observed. A full presentation of experimental results was published earlier 1°. At 13 K, the device drain current decreases with time (as shown for an nFET in Figure 9). This is due to the slow formation of the depletion layer, which leads to a transient higher conductivity inversion layer. This is the
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Impurity ionization in MOSFETs: D.P. Foty 4
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opposite behaviour to the increasing current transient that is produced by device self-heating 3°. These results agree with those reported by Grupen and Viswanathan 32, who developed a Poole-Frenkel model, which they used in a full-scale device simulation to describe the measured results with good accuracy. Similar results were also reported by Tewksbury 33. At 30 K, the Poole-Frenkel dwell time is very short. Since the substrate is not in the hard freeze-out regime, field dependent ionization should not play a role in device behaviour. Instead of a decreasing current transient due to field dependent ionization, an increasing current transient due to device self-heating is produced (Figure 10) 3°'31. This is consistent with the theoretical predictions presented earlier. As noted above, carriers released by field dependent ionization reach the substrate contact and are detected as substrate current 25. Thus, the substrate current serves as a monitor of the ionization process. A typical experimental result for a pFET is found in Figure 11. The peak in the
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substrate current due to field-dependent ionization is clearly evident. Using the model developed earlier for field-dependent ionization, a one-dimensional simulation of the process can be carried out. It is assumed that, at t = 0, all the carriers in the substrate are frozen out. The time is incremented and, from the field distribution and the equations presented earlier, the ionization probability and the ionized impurity profile are computed. From this profile, a new field distribution is calculated. This iterative process continues until the depletion region is fully formed. A typical result is presented in Figure 12. The model is able to reproduce the key feature of the experimental result, a transient which peaks at a time of the order of tens of seconds. Note that the model does not take into account substrate current due to impact ionization in the operating device.
Discussion
Due to the basic physics of semiconductor materials, a dynamic equilibrium exists during freeze-out. In conventionally doped material, this leads to a hard freeze-out regime for T < 30 K, in which the dwell time for a frozenout carrier is very long. Instead, field dependent ionization is required to release frozen-out carriers. The theoretical approach developed here clearly shows that Poole-Frenkel ionization is the predominant ionization mechanism at 'intermediate' temperatures (10-30 K). Tunnelling dominates when the temperature is too low for Poole-Frenkel ionization (field-assisted thermal ionization). In some situations, Poole-Frenkel ionization will dominate up to a particular field strength, after which tunnelling dominates for higher fields. The equations developed here interpret field dependent ionization on the basis of temperature and field, in a fashion similar to that developed for deep level transient spectroscopy. These equations describe the physical phenomena locally in the material; in this form, they should be readily applicable in typical large-scale device simulation programs. Examination of the theoretical framework and the
Cryogenics 1990 Vol 30 December
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Impurity ionization in MOSFETs: D.P. Foty experimental results indicate that conventionally doped MOSFETs will behave very differently for T _< 30 K. In particular, significant long-term transient effects (as discussed in References 10, 30 and 31) will be a major factor in device behaviour. Besides field dependent ionization t° and thermal effects 3°'3~, other difficulties (such as Anderson localization 34 and I - V hysteresis due to interface trapping 35) are encountered, leading to potentially illusory indications of sharp improvements in device performance for T < 30 K. These effects must be understood and taken into account in both studies and applications of MOSFETs at very low temperatures.
2 Yao, C., Tzou, J., Cheung, R. and Chan, II. Temperature
Summary
8
This paper has examined the effect of substrate freezeout on MOSFET behaviour at very low temperatures. After a brief discussion of freeze-out, dynamic equilibrium theory similar to that used for deep level transient spectroscopy was applied to identify the hard freeze-out regime in conventionally doped MOSFETs for T <_ 30 K, in which a depletion region is unable to form normally due to the long time required for thermal ionization. Field dependent ionization was then discussed, with Poole-Frenkel ionization (field assisted thermal ionization) and tunnelling (field induced ionization) examined as the specific mechanisms. Calculations were presented showing the effect of temperature and field on the dwell time. Specific values of temperature and field that favoured either Poole-Frenkel ionization or tunnelling were identified. To compare the theoretical development with experimental results, it was shown that the field distribution under hard freeze-out is very different in MOS capacitors and MOSFETs, leading to a prediction of slow depletion region formation in MOSFETs at very low temperatures. These predictions were verified by demonstrating a sharp difference in the behaviour of long-term drain current transients at and below 30 K. The long-term substrate current transient, a monitor of field dependent ionization, was presented, and it was shown that the model developed here can be used in a simple one-dimensional simulation to produce results similar to those found experimentally. Finally, some of the implications for basic semiconductor physics and very low temperature MOSFET operation were discussed.
Acknowledgements Thanks are due to P. Wyns of Hewlett-Packard, Colorado Integrated Circuit Division, Fort Collins, CO, D. Cole of IBM General Technology Division, Essex Junction, VT, and M. Wordeman of the IBM T.J. Watson Research Center, Yorktown Heights, NY, for extensive discussions of this work. Thanks are also due to M. Marceau, P. Cottrell, and J. Hiltebeitel of IBM General Technology Division, Essex Junction, VT, for interest and helpful assistance and to D. Gentes of IBM General Technology Division, Essex Junction, VT, for editorial assistance.
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