InAs quantum dots as charge storing elements for applications in flash memory devices

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InAs quantum dots as charge storing elements for applications in flash memory devices

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Sk Masiul Islam a , Pranab Biswas a , P. Banerji a,∗ , S. Chakraborty b

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Materials Science Centre, Indian Institute of Technology, Kharagpur 721 302, India Applied Materials Science Division, Saha Institute of Nuclear Physics, 1/AF Bidhannagar, Sector-I, Kolkata 700 064, India

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a r t i c l e

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Article history: Received 4 November 2014 Received in revised form 24 March 2015 Accepted 31 March 2015 Available online xxx

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Keywords: Quantum dots Charge storage Charge retention Carrier transport

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1. Introduction

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InAs quantum dots (QDs) were grown by metal organic chemical vapor deposition technique to use them as charge storage nodes. Uniform QDs were formed with average diameter 5 nm and height 5–10 nm with a density of 2 × 1011 cm−2 . The QDs were grown on high-k dielectric layer (ZrO2 ), which was deposited onto ultra-thin GaP passivated p-GaAs (1 0 0) substrate. A charge storage device with the structure Metal/ZrO2 /InAs QDs/ZrO2 /(GaP)GaAs/Metal was fabricated. The devices containing InAs QDs exhibit superior memory window, low leakage current density along with reasonably good charge retention. A suitable electronic band diagram corresponding to programming and erasing operations was proposed to explain the operation. © 2015 Published by Elsevier B.V.

Low dimensional structures of semiconductor have gained tremendous research interest due to their modified electronic and optical properties [1]. Semiconductor nanostructures such as Si [2], Ge [3,4], SiGe quantum dots (QDs) [5], carbon nanotubes [6], and Si nano-needles [7] were used as charge storing elements to develop non-volatile memory cells. Reports are available where metallic nanoparticles (NPs) of Ni [8], Pt [9], cobalt silicide (CoSi2 ) [10], vanadium silicide (V3 Si) [11], and AuPd [12] and dielectric nanocrystals (Al2 O3 nanodots) [13], were used in metal-oxide-semiconductor (MOS) based non-volatile flash memory devices. A review article is also available on the materials for future quantum dot based memories by Nowozin et al. [14]. While using the metallic NPs, problems such as reaction between the metal particle and oxide, diffusion of metal and activation of dopants in the gate, source or drain regions when high temperature processing are encountered [15]. Moreover, a lot of challenges are involved in terms of NPs synthesis, its stability, and repeatability. Furthermore, it is not in conformity with the present process lines of device manufacturing. On the other hand, incorporation of QDs as charge storage media will lead to the advantages of low leakage, low voltage operation, low power consumption, faster programming-erasing (P/E) speed, and enhanced

∗ Corresponding author. Tel.: +91 3222 283984; fax: +91 3222 255303. E-mail addresses: [email protected], pallab [email protected] (P. Banerji).

data retention or reliability promoted by the quantum confinement as well as Coulomb blockade effect [6,16]. For next generation memory applications, GaAs MOS based structures are considered to be better choice by replacing Si due to certain advantages such as high speed operation and low power consumption [17–19]. In MOS based memory structures various high-k dielectric materials such as HfO2 , ZrO2 , Al2 O3 , Y2 O3 , and TiO2 were extensively used [20–22]. Particularly, ZrO2 appears to be a promising candidate because it is the most thermodynamically stable material along with its several other advantages such as high dielectric constant of about 25, a large band gap energy (5.1–7.8 eV), and a high breakdown field (15 × 106 V/cm) [23]. Memory device based on GaAs MOS was reported by Kundu et al. [18] where InP QDs was used for charge storing in conjunction with high-k ZrO2 . But InP exhibits high band gap, high carrier effective mass, low electron affinity, and low carrier mobility compared to InAs. Another report available in the literature on GaAs MOS based memory device with ZnO QDs embedded between two dielectric layers [24] though being a wide band gap semiconductor, low electron affinity as well as its chemical instability, it is not suitable for data storage. Hence in this work, we have introduced InAs QDs. In this paper, we, thus report the catalyst-free growth and characterization of InAs QDs on high-k dielectric (ZrO2 ) layers to study its potential in storing charges which will eventually replace metal nano-particle based flash memory devices. As an application, grown InAs QDs were used in a MOS based memory structure to obtain some of the memory parameters. A suitable energy band diagram was proposed to realize the electronic transitions pertaining

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Fig. 1. (a) AFM and (b) TEM images of MOCVD grown (at 500 ◦ C for 3 min) InAs QDs on tunneling ZrO2 , (c) SAED pattern of the grown InAs QDs. It shows the single crystalline ˚ nature of the QDs. (d) HRTEM image corresponding to the lattice fringes of a single InAs QD with lattice spacing of 2.94 A.

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to the programming (writing) and erasing operations using the QDs. 2. Experimental p-type (1 0 0) GaAs substrates, having carrier concentration of 1 × 1016 cm−3 , were chemically surface treated. The samples were degreased by boiling sequentially with acetone and methanol. Then the samples were rinsed in deionized water (18.2 M). After that the samples were dipped into the etchant solution of H2 O2 –NH4 OH–H2 O in the ratio of 1:1:2 to remove the native oxide and elemental As. Again the samples were rinsed for 3 min with deionized water and dried by N2 gun. An ultra-thin interface passivation layer (IPL) of GaP of thickness ∼1.8 nm was grown on p-GaAs at 540 ◦ C by metal organic chemical vapor deposition (MOCVD) technique. Tri-methyl gallium (TMGa) and phosphine (PH3 ), with a flow rate of 6.8 sccm and 70 sccm, respectively, were used as the precursors for Ga and P, respectively, whereas high purity H2 was used as carrier gas. Then ZrO2 was grown on it as a tunneling layer. Zirconium t-butoxide [Zr-(OC4 H9 )4 ] and O2 were used as the zirconia and oxide precursors, respectively. Here the reaction was carried out at 300 ◦ C and N2 was used as the carrier gas. This was followed by annealing the grown ZrO2 film at 500 ◦ C for 5 min in N2 ambient. The ZrO2 film thickness was found to be 5 nm. InAs QDs of 5 nm were grown on tunneling ZrO2 at 500 ◦ C for 3 min by MOCVD. Tri-methyl indium (TMI) and arsine (AsH3 ) were used as the precursor source for In and As, respectively, whereas high purity H2 was taken as carrier gas. The flow rate of TMI and AsH3 were taken as 45 and 75 sccm, respectively. Likewise, ZrO2 control layer having thickness of 21 nm was grown onto it. Finally top gate electrode of Al covering an area 1.95 × 10−3 cm2 was formed by thermal evaporation. Similarly a low resistance ohmic contact was made with

Pd-Ag onto the back surface of GaAs by the same technique. It was then annealed at 300 ◦ C for 3 min in argon ambience. The thickness of individual layer was determined by an ellipsometer (Accurion Nanofilm EP3 Model). The QDs grown on tunneling layer were characterized by atomic force microscopy (AFM) (model 5100, Agilent Technologies) in order to determine their size and density. The dots were also characterized by high resolution transmission electron microscope (HRTEM, Jeol Jem-2100) and TEM (FEI-Tecnai G220STwin). The chemical analysis of the QDs was done by X-ray photoelectron spectroscopy (XPS) using PHI 5000 VersaProbeII (ULVACPHI, INC, Japan) system connected with a microfocused (100 ␮m, 25 W, 15 kV) monochromatic Al K␣ source (h = 1486.6 eV), a hemispherical analyzer, and a multichannel detector. During the analysis, the vacuum was maintained at ∼10−11 torr inside the chamber. To neutralize the charge, a combination of low energy Ar+ ions and electrons were used throughout the analysis. Charge calibration of the binding energy scale was done by C 1s peak at 284.6 eV. The electrical measurements of the memory devices were carried out using Keithley (4200-SCS) semiconductor parameter analyzer. 3. Results and discussion From the AFM image, shown in Fig. 1 (a), homogeneous distribution of the dots over the surface of the high-k are clearly visible. The dot height and density were determined to be 5–10 nm and 2 × 1011 cm−2 , respectively, with the help of WSxM software. Fig. 1(b) represents the plan-view bright field TEM micrograph of the quantum dots with approximately round in shape and the average dot diameter was found to be 5 nm. In the selected area electron diffraction (SAED) pattern for a single InAs QD, shown in Fig. 1(c), the InAs crystal planes are observed. The distinct difference between the diffraction spots and the periodicity of their

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Table 1

Q5 Memory performance in different MOS devices.

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Sample description

Charge storage elements

Memory window (V)

GaAs MOS GaAs MOS GaAs MOS GaAs MOS GaAs MOS

Pt NPs Au NPs InP QDs ZnO QDs InAs QDs

1.80 at ±2 V 7.00 at ±10 V 6.30 at ±10 V 6.10 at ±10 V 6.83 at ±10 V

arrangement in the SAED pattern represents the growth of single crystalline InAs QDs. From the lattice fringe of the QDs, as shown in Fig. 1(d), the monolayer separation of a single InAs QD ˚ High denwas calculated and the value was found to be 2.94 A. sities of isolated islands are found to form without any wetting layer which can be considered as direct islanding growth of InAs QDs on ZrO2 following Volmer-Weber mode. During the growth due to the overpressure of AsH3 , gradual As adsorption takes place, which effectively minimize the activation energy for the formation of InAs islands. Therefore it will promote the island nucleation. In fact, the existence of lattice mismatch system and low interaction energy between InAs and amorphous ZrO2 favors direct islanding. The chemical nature of the InAs QDs was analyzed by high resolution XPS measurements. As depicted in Fig. 2(a), two distinct peaks

Fig. 2. X-ray photoelectron spectra of (a) In 3d and (b) the As 3d region of InAs QDs.

Charge loss (%)

Ref. No.

16.80 after 105 s – 16.50 after 105 s 15.20 after 105 s 13.80 after 105 s

[17] [19] [18] [24] Present study

of In 3d spectrum of the InAs QDs are observed. The one located at 443.80 eV belongs to In 3d5/2 , while the other at 451.40 eV corresponds to In 3d3/2 . Thus the value of spin orbital splitting was found to be 7.60 eV. Fig. 2(b) shows the appearance of two peaks of As. The peak at 41.40 eV is related to As whereas that at 44.40 eV denotes the oxidized As. The As peak was found to be more stronger than the oxidized species. Fig. 3(a) and (b) shows the schematic view of a typical GaAs MOS based non-volatile memory device with InAs QDs embedded between the high-k control and tunneling ZrO2 dielectric layers and cross-sectional TEM image of the device, respectively. The HRTEM image of the InAs QDs on the high-k dielectric is also shown in Fig. 3(c). The proposed energy band diagram of such a device in which the InAs QDs are sandwiched between two highk dielectric layers (ZrO2 ) is shown in Fig. 4(a). The carriers have to surmount the triangular potential barrier formed at InAs/GaAs interface as shown in Fig. 4(b), due to the incorporation of high-k dielectric (ZrO2 ) following Fowler-Nordheim (F-N) tunneling. Consequently, the charges are trapped into the potential well formed between high-k (ZrO2 ) tunnel and control layers. Typical high frequency (100 kHz) capacitance–voltage (C–V) characteristics of the memory structures with embedded QDs as well as of the control devices (without any QDs) were carried out at room temperature under different gate voltages which was swept from ±3 to ±10 V. As shown in Fig. 5(a), a large hysteresis in the C–V characteristics was found over the entire sweeping voltage. Since with increasing applied sweep voltage, the flatband voltage (VFB ) also increases, so there exists a number of trap sites within the InAs QDs. Again the hysteresis is in the direction of the counter clockwise suggests that the carrier transport between the InAs QDs and p-type GaAs substrate is due to tunneling [10]. On the other hand very low memory window was found in the control structures, as shown in Fig. 5(b), compared to the devices where QDs were introduced. The width of the memory window (hysteresis) of the devices with QDs was found to be 1.84, 4.41, and 6.83 V for voltage sweep of ±3, ±6, and ±10 V, respectively. In Table 1, a comparison of the results of the present study has been made with those reported earlier having both NPs and QDs as charge storage elements. The value of the memory window is found to be not only higher than those reported for InP QDs and ZnO QDs embedded GaAs based MOS devices; it is comparable to that reported by Chiu et al. [19] who have used Au NPs as charge storing elements. InAs QDs on high-k dielectric (ZrO2 ) results considerable strain into the system. In such system (InAs/GaAs), the electron-hole exchange interaction is anisotropic which leads to the splitting of energy levels as well as the increase in confinement potential into InAs QDs due to in-plane asymmetries of the carrier wave function [25,26]. Hence the number of energy states is increased. Again high conduction band offset (∼3.26 eV) at InAs/ZrO2 in the bulk leads to deeper potential well formed between two oxide layers, and thus accommodate more energy levels for carriers. It may be mentioned here that the injected electrons will first fill up the empty states, where the trap level is deeper and then fill the shallower levels [27]. This eventually results better storage of carriers due to an increment in available energy states for InAs QDs. Thus a large hysteresis in the C–V characteristics is found for the devices

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Fig. 3. (a) A schematic of the device structure, (b) cross-sectional TEM image of InAs QDs embedded in a matrix of ZrO2 , and (c) HRTEM image of InAs QDs.

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containing InAs QDs. However, the hysteresis in C–V characteristics can be obtained either due to the injection of charges into the InAs QDs or due to the presence of surface states at ZrO2 /GaAs interface [28]. To ensure that the origin of charge storage is the QDs, we

Fig. 4. (a) Schematic energy band diagram of Al/ZrO2 /InAs QDs/ZrO2 /(GaP)p-GaAs memory structure at flatband condition. (b) Fowler-Nordheim tunneling through triangular potential barrier formed in the high-k dielectric.

have characterized our memory devices by frequency dependent C–V measurements. Now from Fig. 6, it is seen that no frequency dispersion in accumulation capacitance, with nearly constant hysteresis width, was observed in the measured frequency ranges from 10 kHz to 1 MHz for ±10 V sweep voltage. Thus interface traps have negligible contribution for the origin of hysteresis; and hence the charge storage phenomena are due to InAs QDs and not due to surface states in ZrO2 or ZrO2 /GaAs interfaces. This minimization of surface states is caused by the incorporation of ultra-thin GaP IPL on GaAs surface prior to the deposition of ZrO2 . The operation of the programming and erasing were demonstrated according to the band diagram as shown in Fig. 7(a) and (b), respectively. During programming operations, when positive voltage is applied at the gate electrode, the inversion electrons will tunnel from the GaAs conduction band to the InAs QDs by surmounting the triangular potential barrier of the tunnel oxide layer following F-N tunneling mechanism. The injected electrons are then stored into the InAs QDs leading to the writing operations. The thick control high-k will block further movement of the electrons towards the metal gate electrode, and thus minimize the gate leakage current. However during erasing operation the trapped electrons are emitted back to the GaAs leaving behind many holes into the InAs QDs or holes are injected into the QDs on applying negative voltage to the gate electrode. During erase cycle the minimization of back tunneling current i.e. hole current under programming mode and electron current under erasing mode was achieved by using high-k ZrO2 with large barrier height and large relative permittivity as a blocking layer. To estimate the leakage current in our fabricated devices, the current density–voltage (J–V) characteristics was performed and shown in Fig. 8. The value of the leakage current was measured to be 2.86 × 10−6 A/cm2 at −1 V, which is found to be lower than those reported earlier [24,29]. This low value of leakage current in the fabricated memory devices is attributed to the Coulomb blockade effect. The plausible mechanism is explained as an electron is trapped into the QDs, its potential energy is raised by the electrostatic charging energy, Q2 /C, where Q is the electronic charge

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Fig. 5. Room temperature high-frequency (100 kHz) capacitance–voltage characteristics of GaAs NVM devices (a) containing InAs QDs and (b) without InAs QDs for control devices. Large hysteresis was found in the InAs QDs embedded devices, whereas very poor memory window was obtained in the control samples without InAs QDs.

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Fig. 7. Schematic energy band diagram of Al/ZrO2 /InAs QDs/ZrO2 /(GaP)p-GaAs memory structure at (a) positive programming bias condition, and (b) negative bias for erasing modes.

and C is the quantum dot capacitance. Again C can be expressed as:



C = 4˘εR 1 +

2

(R/2d) R + 2 2d 1 − (R/2d)



(1)

where ε is the dielectric constant of ZrO2 , R is the radius of InAs QDs, d is the distance between the center of the dots and the substrate surface. In our case InAs QDs with diameter of 5 nm

Fig. 6. Room temperature frequency dependent capacitance–voltage characteristics of the InAs QDs embedded GaAs MOS based NVM devices with sweeping gate voltage ± 10 V. No frequency dispersion was found in the memory devices containing InAs QDs. This ensures the obtained memory effect is due to the charge storage in the InAs QDs.

Fig. 8. J–V characteristics corresponding to the leakage current of GaAs NVM devices.

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substrates passivated with ultra-thin GaP. From AFM and TEM images the height and diameter of InAs QDs was found to be 5–10 nm and 5 nm, respectively, whereas the SAED pattern shows ˚ We crystalline nature of the dots with a lattice spacing of 2.94 A. have systematically studied the role of InAs QDs as charge storing elements for GaAs MOS based devices. C–V measurements show a large hysteresis width of 6.83 V with negligible dispersion in frequency. The device exhibits very low leakage current and superior charge retention of 86.2% after 105 s. Thus with its simple MOS like structure and superior characteristics, the structures may have great potential for future generation nano-scale non-volatile charge storage devices. Acknowledgments

Fig. 9. Retention characteristics of the GaAs MOS based NVM devices containing InAs QDs. The characteristics exhibit 86.2% charge retention even after 105 s.

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were grown. The calculated electrostatic charging energy of the quantum dots was found to be ∼30 meV, which is higher than the room temperature thermal energy (25 meV). This will decrease the electric field across the tunnel layer. As a result the tunneling current is reduced. Since our system satisfies this fundamental condition of Coulomb blockade effect, thus the obtained low value of leakage current is due to the Coulomb blockade effect [24]. The surface passivation also minimizes the interface states and contributes positively towards decreasing the leakage current further [29]. For practical application, it is pertinent to determine the retention characteristics of the InAs QDs embedded memory devices. The device was initially charged under a drive gate voltage of ±13 V for 2 s and then C ± (t) measurements were carried out ± by changing the gate voltage to its flatband voltage value, VFB . The excess capacitance (C%) can be expressed as: (C + (t) − C − (t)) C(%) = × 100 ± − CFB − CFB

(2)

where C + (t) and C − (t) are the capacitances at the time of measurement for forward and reverse gate sweeping voltage, respectively. + − Likewise, CFB and CFB are the flatband capacitances during forward and reverse sweeping voltage, respectively [30]. Fig. 9 reveals reasonably good charge storage (86.2%) capacity of the InAs QDs embedded memory device, where only 13.8% charge were lost after 105 s. Fig. 9 consists of two capacitance decay regions, viz. initial fast decay and then slow decay region. Initial fast charge loss is caused by lateral charge spreading and coulomb repulsion, whereas charge leakage through the tunnel layer is responsible for slow decay in the device. The localization of the InAs QDs prevents lateral charge spreading and Coulomb repulsion of charges into the QDs, and thus reduces fast decay. Coulomb blockade effect also reduces the carrier leakage through the tunnel layer. However, due to large band offset (3.26 eV) at InAs/ZrO2 in the bulk compared to InP/ZrO2 (2.74 eV) [18] and ZnO/ZrO2 (2.46 eV) [24], the carriers cannot easily tunnel back from InAs QDs to the GaAs. On the other hand ultra-thin GaP passivation layer significantly lowers the density of interface states resulting reduction in reverse tunneling. 4. Conclusion We have successfully grown InAs QDs by MOCVD technique on high-k ZrO2 , which is deposited onto the p-type (1 0 0) GaAs

One of the authors (S.M. Islam) acknowledges University Grants Q4 Commission, New Delhi for awarding Maulana Azad National Fellowship for Minority Students. The authors also acknowledge partial support from Department of Science and Technology, New Delhi. The authors are thankful to Mr. Arunava Chaudhuri for technical help during MOCVD growth. References [1] D. Bimberg, Semiconductor Nanostructures, Springer, Berlin, 2008. [2] H.I. Hanafi, S. Tiwari, I. Khan, IEEE Trans. Electron Devices 43 (1996) 1553–1558. [3] S. Das, K. Das, R.K. Singha, A. Dhar, S.K. Ray, Appl. Phys. Lett. 91 (2007) 233118. [4] K. Das, M. NandaGoswami, R. Mahapatra, G.S. Kar, A. Dhar, H.N. Acharya, S. Maikap, J.H. Lee, S.K. Ray, Appl. Phys. Lett. 84 (2004) 1386–1388. [5] D.W. Kim, F.E. Prins, D.L. Kwong, S.K. Banerjee, IEEE Trans. Electron Devices 50 (2003) 510–513. [6] X.B. Lu, J.Y. Dai, Appl. Phys. Lett. 88 (2006) 113104. [7] S. Jung, J. Yoo, Y. Kim, S.K. Dhungel, J. Yi, Mater. Sci. Eng. C 26 (2006) 813–817. [8] D. Panda, S. Maikap, A. Dhar, S.K. Ray, Electrochem. Solid State Lett. 12 (2009) H7–H10. [9] H. Kim, S. Woo, H. Kim, S. Bang, Y. Kim, D. Choi, H. Jeon, Electrochem. Solid State Lett. 12 (2009) H92–H94. [10] J.H. Kim, J.Y. Yang, J.S. Lee, J.P. Hong, Appl. Phys. Lett. 92 (2008) 013512. [11] D. Kim, D.U. Lee, H.J. Lee, E.K. Kim, Thin Solid Films 521 (2012) 94–97. [12] F. Sabri, D.G. Hasko, Appl. Phys. Lett. 74 (1999) 2996–2998. [13] J.H. Chen, W.J. Yoo, D.S.H. Chan, L.J. Tang, Appl. Phys. Lett. 86 (2005) 073114. [14] T. Nowozin, D. Bimberg, K. Daqrouq, M.N. Ajour, M. Awedh, J. Nanomaterials 2013 (2013) 215613. [15] S.L. Zhang, U. Smith, J. Vac. Sci. Technol. A 22 (2004) 1361–1370. [16] T.C. Chang, S.T. Yan, C.H. Hsu, M.T. Tang, J.F. Lee, Y.H. Tai, P.T. Liu, S.M. Sze, Appl. Phys. Lett. 84 (2004) 2581–2583. [17] R.C. Jeff Jr., M. Yun, B. Ramalingam, B. Lee, V. Misra, G. Triplett, S. Gangopadhyay, Appl. Phys. Lett. 99 (2011) 072104. [18] S. Kundu, N.N. Halder, P. Biswas, D. Biswas, P. Banerji, R. Mukherjee, S. Chakraborty, Appl. Phys. Lett. 101 (2012) 212108. [19] H.C. Chiu, C.K. Lin, C.W. Lin, C.S. Lai, Microelectron. Reliab. 52 (2012) 2592–2596. [20] H.S. Kim, I. Ok, M. Zhang, F. Zhu, S. Park, J. Yum, H. Zhao, J.C. Lee, Appl. Phys. Lett. 91 (2007) 042904. [21] G.D. Wilk, R.M. Wallace, J.M. Anthony, J. Appl. Phys. 89 (2001) 5243–5275. [22] L. Kang, B.H. Lee, W.J. Qi, Y. Jeon, R. Nieh, S. Gopalan, K. Onishi, J.C. Lee, IEEE Electron Device Lett. 21 (2000) 181–183. [23] G.K. Dalapati, A. Sridhara, A.S.W. Wong, C.K. Chia, S.J. Lee, D. Chi, Appl. Phys. Lett. 91 (2007) 242101. [24] S. Kundu, S.R. Gollu, R. Sharma, N.N. Halder, P. Biswas, P. Banerji, D. Gupta, J. Appl. Phys. 114 (2013) 084509. [25] R.M. Stevenson, R.M. Thompson, A.J. Shields, I. Farrer, B.E. Kardynal, D.A. Ritchie, M. Pepper, Phys. Rev. B 66 (2002) 081302 (R). [26] O. Stier, M. Grundmann, D. Bimberg, Phys. Rev. B 59 (1999) 5688. [27] Y. Shi, K. Saito, H. Ishikuro, T. Hiramoto, J. Appl. Phys. 84 (1998) 2358. [28] C.L. Hinkle, A.M. Sonnet, M. Milojevic, F.S. Aguirre-Tostado, H.C. Kim, J. Kim, R.M. Wallace, E.M. Vogel, Appl. Phys. Lett. 93 (2008) 113506. [29] X. Ma, Nanotechnology 19 (2008) 275706. [30] R. Aluguri, S. Das, R.K. Singha, S.K. Ray, Curr. Appl. Phys. 13 (2013) 12–17.

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