Incorporation of metal silicides and refractory metals in VLSI technology

: Applied

Incorporation of metal silicides and refractory in VLSI technology

The advantages into VLSI formed

1401; accepted

over

junction-clad

for publication

a pre-existing

are illustrated junction.

devices ac generally

diffusion

While

the

drive

current

Reducing

1 to 0.2.5 pm CMOS chnracterihtics.

( < IO nA/cm’)

latch-up

of refractory

metals

resistance,

and

series

resistance

of

and thcrehy

allow

stability. The ux of silicide as a

to smaller dimensions while minimizing junctions where the junction

the scaling of the

motion heyond the silicide

nm.

The self-aligned silicide process (SALICIDE) was developed for silicon VLSI technology as a way to reduce the sheet resistance both of shallow junctions and of poly-Si gates. The silicidcs of both titanium and cobalt have been widely used, and their basic properties have been extensively reported for this application. Rcfs. [1,2] provide recent reviews of some of the literature on these materials. Only relatively recently, however, has there been extensive publication [3-221 about the issues associated with the integration of these materials into device technology. The incorporation of these silicides into VLSI device technology has presented some serious additional challenges, particularly since the evolution of the technology to even smaller feature sizes and shallower junctions makes the continued use of metal silicides even more difficult. The concept of Self-Aligned refractory METal 0

~::.‘...,I?. ,,., ,:

where the silicide or metal are

thickness to reduce silicon consumption

n c and pi

1. Introduction

0169-4332/91/$03X

technology

higher resistivity and poorer thermal

source is shown to be one possible way to scale the technology

I

:.,

such as hot electron stability, threshold voltage control. and short

the metal (silicide)

depth results in films having considerehly

to be less than

.:”

metals

of metal silicides and the selective deposition

using examples from

silicide thickness. Here we report low leakage is believed

.’

1991

improved, other characteristics.

channel effect may he adversely effected. scaling the junction

27 March

and issues associated with the incorporation

device technology

‘..

applied surface science

North-Holland

24 March

:.

:.:

Surface Science 53 (1991) 2Yl-312

Received

.:.. .:.:. .:::: .q...... .., ..,‘.: .:

1991 - Elsevier

Science Publishers

(SAMET) for junction cladding has been considered for some time 123,241, but only recently have the issues of selectivity [2S] and junction leakage [26-291 been adequately addressed such that this option now appears potentially viable. The selective deposition of refractory metal silicidcs [30,31] or other high-conductivity materials, such as TiB, [32], are other natural candidate alternatives for incorporation into device technology. Both of these selective deposition processes have the advantage of raising the source/drain regions where their thickness does not add to the electrical junction depth which is critical in controlling device short channel behavior. Using the conventional approach of siliciding the existing junctions, serious problems have been observed with achieving a reliable reaction with heavily-doped substrates to obtain the low resistivity silicide phase without: (a) depleting dopant from the junction and thereby increasing the contact resistance, (b) bridging from the gate to the

B.V. All rights reserved

diffusion, or (c) pen&rating the junction, laterally or vertically, so as to cause high junction leakage. Once the silicide is formed, it is still a problem to keep it from agglomerating during subsequent thermal cycles which are used for glass (BPSG of PSG) retlow. Several of these problems become more severe as the junction dimensions are reduced. One of the aims of this work was to provide more understanding of the trade-offs and issues associated with the scaling of silicided junctions. As part of this objective, we have tried to quantify the utility of silicides in VLSI devices and to determine the limits of their applicability. Another focus was to examine alternate approaches that might be beneficial in extending the applicability of silicide technology. Fig. 1 shows two additional techniques for shallow junction formation in addition to the more standard selective cladding with either silicide or refractory metal of preformed junctions. One of these alternatives is to implant the junction through metal

or through silicide. The other tcchniquc uses silicides as a diffusion source by implanting cntirely within the silicidc to minimize junction depth. Ultimately. the sclectivc deposition of silitides on silicon regions and their subsequent USC as solid diffusion sources, may offer the potential for continued scaling of junction depths.

2. Formation

of metal silicides

on devices

The reaction of titanium or cobalt with silicon wafers to form their respect& silicidcs has been extensively studied. Nevertheless. in actual device processing, an incomplete reaction is frequently observed. Several complicating factors associated with this device fabrication have been shown w postulated to retard the silicidation reaction. These factors include the presence of cxccssivc native oxide especially on degenerately doped substrates. contaminants such as polymer left by oxide spacer etching, knock-on of impurities OI

11111111

a

3’:‘_:-,Me’ ’ Oxide

Silicon

Implant Through Metal

Form Silicide

Implant 81 Diffuse Junction

Form Silicide/

Implant & Diffuse

Refractory Metal

Junction

Silicide

Conventional

as a Diffusion

Form Silicide & Diffuse Junction

Implant Through

Source

Metal

Implant Through Silicide

Fig. I. Comparison

c

b

a of processes for shallow junction

selective metallization

of existing junctions.

formation

with self-aligned

(h) silicide as a diffusion

Glicides or refractory

source (SADS)

through metal (ITM).

metals: (a) siiicidation

OI- implant through silicidc (ITS).

01

Cc) implant

below 10 nm thick, corresponding to silicon consumption of 20-40 nm results in films having a very high sheet resistance such that the potential advantage of lowering the diffusion sheet resistance with silicides is lost. The thermal stability of metal silicide films degrades as they become thinner and narrower [11,35-381, and the phase transformation of TiSi, to the higher conductivity C54 phase is retarded in narrower lines. This factor places additional constraints on the limits of their applicability.

damage in the substrate due to spacer RIE, or even high dopant concentrations. Scaling of silicide technology to devices having smaller features and shallower junctions requires that the metal (silicide) thickness also be reduced to scale down the silicon consumption to avoid penetration of the junction. Furthermore, the silicon consumption in fine-patterned device areas may be considerably greater than on large-area structures. This anomalous consumption requires that the metal thickness be reduced even more than simple scaling would require to avoid junction penetration. However, it has been seen here and in other work [33,34] that the metal and silicide sheet resistance do not scale proportionally to their thickness. The use of metal films

Table 1 Representative Silicide

dues

of sheet resistances

Metal thickness (nm)

TiSi, TiSi? TiSi z TiSi 7 TiSi? TiSi, TiSi z TiSi z TiSi z TiSi TiSiz TiSi I TiSiz TiSi TiSiz TiSi TiSii TiSi z TiSi2 TiSi? TiSi,

- II’

CoSi, CoSi ? CoSi L C&i? CoSi2 CoSi z CoSi z CoSi2

140 400 120 230 - 130 - 30 39 12

112 250 40? 35 32 30 230 X0? 50

I.50 35 50 100 100 85 30 30 30 18

obtained

2.1. Reaction with suhstrute In CMOS device technology, sequence includes: (1) reactive

after silicidation

Sheet resistance

(O/O

n+

P+

1.7 6.0

I .6S 2.7 3.5 3.2 4.x 3.9 3.x 2.3 1.7 4.0 6.0 4.0 3.5 0.86

I .03 4 3.x 6.4 17.4 1.5 0.6 1.1 2.5 I.‘) I.4

1.7 2.4 0.X5 2.4 3.0 2.5 3.6 3.‘) 2.4 2.0 1.o 3.5 4.0 3.0 3.5 0.76 0.9 2.4 2.0 3.3 16.2

a typical process ion etching of a

of II+, p+, and poly-Si

)

Ret’. poly-Si 2.0

3.0 2.7 10.1 2.3 1sl

2.5 1.7

0.89

1.11 2.1 2.8 3.6 17.4

1.3 0.4S 1.1 2.6 1.9

1.3 0.45 2.0

1.9 1.4

8.6 3.5

[?I [61 [61 11u1 1131 m [391 [431 Ml [561 I571 [5X1 [5X1 [5X1 [591 [ho] [601 [This [This [This [This

work] work] work] work]

PII Ml [421 [431 [431 [441 [611 [This work]

CVD oxide spacer down to silicon using a fluorine-deficient etching gas, (2) an oxygen plasma treatment to oxidize and remove the polymer formed during the first RIE step, (3) an optional HF etch to remove the oxide formed by the oxygen plasma. (4) a photolithography (resist) step to define those regions which are to rcceivc the n ’ (or p+ ) ion implantation. (5) ion implantation of the n’ (or p’) species. (6) a second lithography step to define the opposite junction type, (7) implantation of that junction, and (8) annealing of the source-drain junctions. Thus. depending on the process specifics. silicide formation may bc adversely cffectcd by the presence of polymer. oxide. substrate damage (including buried impuritics). or high dopant concentrations. Indeed. many I-eports of silicidc formation cite diffcrcnt final sheet rcsistivitics depending on whether the silicidc is formed on n+. p ’ , or poly-Si. Table I gives an cxamplc of some of previously observed diffcrcnccs. The substrate cffcct on the sheet rcaistancc, N. is most pronounced for TiSi, films where:

In this cast some of the observed differences can he attrihutcd to the cffcct of dopants on the silicide sheet r&stance [?A-411. Table 2. for instance, shows that the bulk rcsistivity of films grown on p + substrates is lower than that of films grown on n + material. Furthcrmorc. the resistivity ratio. namely the ratio of room tempcraturc to 77 K resistivitics. is greatest for the lowest rcsistivity films. In other instances the cffcct of arsenic in inhibiting the C49 to (‘54 phase transfor-

mation in TiSi, may be responsible for the observed “substrate” effect. The roughness, or partial agglomeration, of silicides on poly-Si might also account for some of the reported differences. Unfortunately, much additional work needs to be done to fully understand the effect of all of the variables. The substrate effect in cobalt disilicidc films appears to be much smaller [17,42X44]; nevcrtheless, table I dots show instances [?I] where the silicidcs have noticeably higher sheet rcsistances on poly-Si or n’ substrates.

Because of the lateral diffusion of silicon into titanium at the initial reaction temperature. the actual silicon consumption can bc much grcatcr than would be prcdictcd by the rclativc densities of metal and silicidc [ 171. This cxccss silicon consumption is believed to play a central role in defining the “buffer” needed between the junction depth and the dcsigncd silicidc depth. Fol titanium. an argon formation atmosphere promotes lateral silicon diffusion and greatly aggravates ( - 2 times) the excess silicon consumption. Even lormation of TiSi, in nitrogen is accompanied by some lateral motion of the exposed silicon into the titanium over oxide regions. FOI fcaturc sizes of the order of micromctcrs in dimcnsion. this process contributes to additional silicon loss amounting to 2Sr;-50ri of the silicidc thickness. Submicron patterns would bc cxpectcd to exhibit cvcn more cxccss silicon consumption. The use of cobalt to form silicidc offers the advantage of eliminating or reducing this anom:t-

Original

Wafer

Fig. 2. Silicon consumption

for TiSi,

and CoSi,

lous, excess silicon consumption, particularly if the initial reaction temperature is chosen to form Co,Si (- 400 o C) in which cobalt is the predominant diffuser. By minimizing the silicon diffusion, bridging between the gate and the diffusion is also minimized. Fig. 2 compares the silicon consumption of TiSi, and CoSi, films grown in different atmospheres, where CoSi, seems to be clearly superior. 2.3. Metal thickness As mentioned earlier, problems associated with the reaction of metal and silicon are greatlyexacerbated as the metal thickness is reduced. Fig. 3 illustrates the non-zero intercept of a plot of metal sheet resistance versus metal thickness for both titanium and cobalt. In both cases it would

after formation

in an argon or a nitrogen atmosphere.

0.4

. co X Ti

l/

0.3 T 0 '; 3 @ _m Q d

/ ,

,/

l./ /

0.2

5 5 0.1

0

10

20 Thickness

Fig. 3. Relationship

between

30

40

(nm)

evaporated

metal thickness and

its sheet resistance for cobalt and titanium.

appear that 5 nm of the initial metal thickness does not contribute to the film’s conductivity. The reaction of very thin metal layers with silicon presents additional problems. The data in fig. 4 shows that the relationship between the sheet resistance of the evaporated metal and that of the final silicide is not constant for starting metal films below about 10 nm thick. Variations in the starting metal thickness of only a few percent can result in silicide films having an order of magnitude higher sheet resistance. The TEM micrographs of fig. 5 show a non-uniform reaction of a 9 nm cobalt film on silicon in which both Co,Si and CoSi, were present after an 700 o C reaction 1451, a condition which produces only CoSiz in thicker films. As might be expected, this non-uniform reaction is manifested in non-uniform film resistance and a highly non-linear relationship between the metal thickness and the resistivity of the reacted film. Comparison of the silicide films formed in 10 s at 700 “C with those formed at 800° C in fig. 4 also illustrates that these thin films arc thermally unstable even at the temperatures normally used to form high-conductivity,

Approximate 2010

Cobalt Thickness

stoichiometric silicide films. Only a few percent difference in the starting metal thickness makes an enormous difference in the stability of the resultant silicide film. Thus. barring the dcvelopmcnt of new techniques for silicide formation, it would appear that CoSi, contacts may not bc practical below about 40 nm thick, so that alternative techniques will be needed to form junctions shallower than 50 nm deep. 2.4. Silicidr stuhility An additional problem associated with the use of very thin silicides is the limited thermal stability of these materials. Temperature cycles associated with BPSG formation, for example, can be sufficient to promote silicide agglomeration. In the agglomeration process, the silicidc balls up and can form isolated islands such that the rcsultant structure has a high resistance. Sheet rcsistance has proven to be a convenient mcasurc of the amount of silicide agglomeration. Work in this laboratory [38] has shown that the time constant for the silicide sheet resistance to incrcasc

Deviation of Thickness from Nominal (Approximate)

(nm)

9

8

100

Rs Metal

T

200

C

B

TOP Wafer

(ML.)

T

C

8

C.Sk?r Wafer

T

C

B

Bottom Wafer

Position in Evaporator Fig. 4. Thickness break

point

dependence

at about

of CoSi ? resistance: (left)

10 nm of metal;

(right)

metal

non-linear

relationship

between

and silicide

resistance

variation

evaporation.

silicide and metal sheet resistance with with

position

of wafers

during

cobalt

CM. Oshurn et al. / Incorporation

ofmetal

by 30%, designated rdTdegrad, can be expressed terms of a degradation diffusivity, Ddrgrad:

in

d - d,, = ~degradrdegred ’ where d is the silicide thickness, and d,, is an offset thickness. The offset thickness values agree well with the values for the infinite resistance intercept of the sheet resistance versus silicide thickness curves for TiSi, (15 nm) and CoSi, (13 nm). Penning [46] has also been able to model the resistivity degradation in terms of a fixed thickness which does not contribute to the silicide conductivity after agglomeration; his values of d,,

297

silicides and refractory metals in VLSI technology

for TiSi, ranged from 7 to 21 nm. The degradation diffusivity can be further expressed as the product of pre-exponential and thermally activated exponential terms, Capping of the silicide with plasma SIN or CVD SiO, has an influence on the silicide stability. Several studies [35,461 have reported improved stability of nitride-capped TiSi,. In this work capped CoSi, appears to be less stable than the silicide merely annealed in nitrogen as illustrated in fig. 6. A strong annealing atmosphere effect has been noted for TiSi, and CoSi, such that nitrogen annealing produces films that are considerably more stable than those

50 nm .

Fig. 5. Cross-sectional

(top) and plan view (bottom)

TEM’s of the reaction of thin (9 nm) cobalt with silicon resulting in globules of Co,% and CoSi,.

annealing of this bilayer results in a reversal in the layering, with the CoSi, appearing at the bottom of the stack. This instability provides an upper bound to the acceptable thermal budget for this material.

1.6 so $ I .!I

3. Refractory metal deposition

1.2

The incorporation of selective tungsten on dcvice gate and source/drain regions has been dclayed in the past because of problems associated with non-uniform silicon consumption or ‘Lwormholes”. which gave rise to high junction leakage, selectivity, and gate/junction bridging due to poor process control. Table 3 gives leakage current data for selective-tungsten clad diodes where the use of SiH, reduction gives considerably lowe leakage than the H, reduction of WF,. such that leakage comparable to non-clad junctions can hc obtained. Improvements in process technology, including the alternating cyclical, AC. technique [25]. have dramatically improved issues associated with spurious nucleation and high defect lcvcla. However, it remains to be seen whether adequate process control can be achieved to eliminate bridging across the narrow spacer separating the gate from the diffusion regions [ 131.

1 0

200

loo

300

400

6(10

X10

RTA Time @ 950°C (set) Fig.

h. Increase

(nominal)

in sheet rcsiatance after

cobalt silicide

samples were implanted

films

amealing

capped with various

with 5 x IO”

arsenic/cm’

00 nm

films.

All

at 50 keV

except where noted.

annealed in argon [2,35,X3]. Thus the deleterious effect of capping layers on CoSi, may be due. in part, to the impermeability of the cap to the annealing atmosphere. The silicide stability has been shown to correlate with the metal reaction with the substrate. For example, the reaction of both Ti [47] and Co [45] with amorphous silicon results in smaller silicide grains and films which are more resistant to subsequent agglomeration for short time anncaling. Thus the implantation of heavy ions such as arsenic, germanium. silicon. or BF, into a silicon substrate without a solid-phaseepitaxial regrowth step prior to silicidation. results in a more stable film. Considerable work has been done to better understand the role of a non-uniform native oxide between the silicon and the silicide. Sputter precleaning, in at least one instance [48], has been shown to result in a smoother as-formed silicide film which has an improved high-temperature stability. Growth of a uniformly thin oxide on the substrate was shown to result in very large grained TiSi, which had superior stability [49]. The stability of silicides on poly-Si may be even more of an issue than their stability to single-crystal silicon. Cobalt disilicidc, in particular. is especially unstable on top of poly-Si [SO];

4. Silicidation

on devices

of existing junctions

4.1. Dopunt redistributim Dopant redistribution from the silicon into the silicide is one of the important issues associated with siliciding junctions. Since the silicide-silicon contact resistance strongly depends on the dopant concentration at the silicon surface, any significant loss of this dopant into the growing silicide can adversely increase R,. Maintaining a high dopant concentration in the silicon at the silitide/silicon interface is particularly difficult since the silicide consumes silicon; thus the silicide/ silicon interface often occurs below the maximum doping concentration in the junction. Increased contact resistance after junction silicidation is observed as a kink in the I,, versus V,, transistor

290

CM. Osburn et al. / Incorporution of metul silicide.sund wfructory metals in VLSI technology Table 3 Leakage of pre-formed

junctions

Silicide Material

TiSi z TiSi 7 None TiSi z TiSi? TiSi? TiSi 2 TiSi L TiSi I TiSi, TiSii CoSi 2 CoSi 2 CoSi z CoSi, CoSi, CoSi z CoSi L CoSi, CoSiz cosi z CoSiz PdzSi PtSi None W-(SiH,) W-(Hz) None W-(SiH,) None W-(SiH,)

Thickness (nm) X0 130&200 - I12 - 112 60 < I’0 - 60 - 20 - 20

clad with selective Junction

Leakage

Type

, ‘1) A (nA/cm’)

AS AS AS A5 BF, BF, AS B BFZ BF2 AS

170-200 170-200 I x0-230 55 250 130 - 80 - 80

- 30

I, (PA/cm)

-4

1.05 _

130 130 130

10 100 10’ -5 -5 -5 -3

[21 Ul [31 [71 [71 [Ill

[‘tXl 1621

1.6

1.1-1.2

-5 - 10

AS As As As As B B

I 00

1.o 1.03

2.0 2.1 0.5 7

20 I.9

150 300 250 300 - 110 I.50

12

-5 - 0.6

300 110

130 55

Ref.

I .o

As BF,

BF, AS AS B As BF, As

metal

3 6

300 250 - 80 - 80

39 70 70 100 60 - 20 - 20

600

250

1.3 1.0 I.6 1.0 2.2 1000 2.0 0.18
AS B As B

600

Depth (nm)

55 55 55 55

150 150

silicide or refractory

[631 [This work] [This work] Dl [21

27 17

I .05

[Xl 181

I .0x

[611 [641

1000

[641 90

1.0 I .os

1.06 -5 - 10 - 70

1.05-1.1 1.05-1.1 1.05-1.1

[651 [‘561 [This work] [This work] [671 [611 [271 1271 [271 (261 [26l [26l Ml

“I I,,,,;,,/area

characteristics, particularly at low drain voltage and high gate voltage [121. One of the subtle effects of dopant redistribution into the silicide is seen in the short-channel behavior of silicided devices. Lu and Sung [14] found that lateral diffusion of dopants out of the channel region and into the adjacent silicided junctions caused the threshold voltage of very short channel devices to actually increase with decreasing channel length rather than decrease as is predicted and observed when the channel doping is uniform from the source to the drain.

Another manifestation of the dopant redistribution problem occurs with silicided poly-Si. Dopants can be depleted from the gate material leading to unacceptable MOS properties [15] or dopant can be transported from one dopant source region to a gate region along a poly-Si line to counter-dope the gate and thereby lead to an instability in the threshold voltage [16,17,51-531. 4.2. Junction

leakage

Junction leakage is a good measure of the quality of silicided shallow junctions. Fig. 7 com-

CZl TiSi 2 eZa CoSi 2

v) $

60

:

50

B 8

40

-L -11

-10

-9

-8

-7

-6

Fig. 7. Diode

leakage characteristics

about 80 nm. The evaporated

of silicided (TiSi,

titanium

or C‘oSi,)

-10

-11

-5

Log Diode Leakage

-9

-8

-7

or un
The n

and cobalt thicknesses were 17 and 7 nm. respectively.

pares diode leakage histograms for un-silicided n+ and p+ junctions with those for junctions silicided with CoSiz or TiSi2. Silicided wafers exhibit a wider statistical spread in leakage even though earlier work has shown that at least TiSi, reduces the amount of crystal damage in the junction region. The figure also shows high junction leakage for N+ junctions clad with TiSi, and illustrates the fact that a larger buffer is needed for TiSi, between the junction depth and the amount of silicon consumed. When the silicide thickness is properly scaled such that an adequate buffer is left, excellent leakage characteristics arc possible on ultra-shallow junctions (< 100 nm), e.g. fig. 8; however, scaling the silicide thickness results in a higher total sheet resistance. Table 3 gives representative junction leakage data from a wide variety of sources and shows that good low leakage diodes can be made with several different silicides as well as with the selective deposition of tungsten.

-6

-5

and p

j

(A)

’

junctions

90 80

-

70

-

60

-

50

-

40

-

30

-

20

-

10

-

ha

v, = 2v lo2 cm’

4.3. Del%ice characteristics

-10

Log Diode Leakage Fig.

X. Diode

ultra-\hallow

P‘

CZil N’

-11

of silicidassociated

’ cm’

with high resistance of shallow diffusions and with high contact resistance to diffusions. A reduction of this parasitic series resistance translates to a higher current drive capability and improved circuit performance, i.e. a reduction in circuit delays. The parasitic resistances of polysil-

n-

The most obvious device advantage ing junctions is to reduce the series

depths were

The diode area was IO

leakage p+

an d n

characteristics

’

junctions.

I

I

-9

-8

(A)

of titanium

ailicided

The evaporated

titanium

thickness was IO nm.

_

1 Km NMOS/PMOS 0.5 Km (NMOS/PMOS) -

4.8 mA 1.15 Frn 7.6/3.2 mA

= 3.3 V for 0.5 km technology,

0.50 mA 0.32X 1.5 firn

1.2 v (2 pm separation) _

” k’c; = k’,, = 5 V for 1.0 and 0.8 wrn technologies;

0.5 pm

_

118/367 12 (20 pm wide)

1 Frn NMOS

1 I*m

1 pm (NMOS/PMOS)

Latch-up

with and without

silicides

YO/120 12 (10 pm wide)

_

_

59/170 f2 (20 pm wide)

Series resist

and latch-up

Series resist It,\a,B’

current, Silicided

saturation

Non-silicided

of series resistance,

1 pm (NM~s/PMos)

Technology

Table 4 Comparison

5.2 mA 1.15 pm 7.4/2.6 mA 2.8/1.1 mA O.46/0.65 X Y.0 pm 0.62 mA 0.32X I.5 pm

2.1/1.8 mA 1.0X9.0 gm

h/2.3 mA 0.8~20 pm’?

IDsatd’

_

5.8 v (2 pm separation) _

Latch-up

[This work]

[lOI

(561

]681

1181

]31

[681

Ref.

icon and diffusion interconnects tend to increase as technologies scale down because short channel effects force reductions in thermal budget and junction depths. In addition, the parasitic resistance associated with metal to silicon contacts increases as the square of the scaling parameter and begins to dominate the total parasitic resistance for sub-micrometer dimensions. For illustrating the importance of the parasitic resistance, and its reduction by silicidation, the device characteristics of two 0.5 pm devices were simulated using PISCES II with and without the salicide film. The device structures used an 11 nm gate oxide, a 100 nm n+ junction depth, and a phosphorus-implanted LDD region. Doping profiles from implants and anneals were computed using PREDICT 1.5, a process simulator. The devices simulated were representative of minimum size gates and contacts for a 0.5 pm process. Minimum size devices, namely those with the shortest channel length and narrowest widths with minimum diffusion spacing between the gate edge and the metal edge and the metal contact, should show the smallest degradation because of parasitic series resistance and provide the most conservative estimate of the beneficial properties of the silicide. The device dimensions used for the simulation are illustrated in fig. 9a. The resistance of the contact and the diffusion interconnect were applied using a lumped clement in series with the source and drain electrode for the unsilicided device. For the silicided device the electrode was extended up to the edge of the gate

Table 5 Parameters

used in device simulations

and unsilicided

to compare silicided

devices Parameter Diffusion

resistivity

(12/O) Silicided Non-silicided

Contact resistivity (o,crn’)

3.0

1.0x IK”

150

I.OX IO ‘>

spacer, which defines the heavy n+ arsenic implant. The metal-to-silicide contact resistance was neglected and the silicide-to-silicon resistance was simulated using the distributed contact resistance model in PISCES. Table 5 lists the resistivities of the diffusions and contacts used in the two simulations. Fig. 9b shows the drain characteristic I-V curves for the two devices. At the maximum drive voltages the non-silicided device provides about 20% less drive current than the silicided device. Several important observations result from the simulations. First, most of this drive current loss in unsilicided devices is caused by the voltage drop across the resistance at the source end of the device, which reduces the effective applied gate potential. Since the drain bias has little effect on the current in the saturation region, a series voltage drop in the drain end of the device would not be expected to have much impact. Indeed, simulations of the structure with a silitided source and an unsilicided drain result in a drive current only 1.5% below that of the com-

POLY GATE

Active area

a Fig.

9. Comparison

of silicided

characteristics

and unsilicided

0.5 ym

showing drain current (I,,)

transistors:

(a) layout geometry

for

0.5 pm

ground

rules;

versus drain voltage (V,,) with the gate voltage (V,,) as a parameter.

(h) device

CM.

Osburn

et al. / Incorporation

of metal silicides and refractory

1.1 x 1Wvlcm 0.5 x lo5 v/cm increments

With Silicide

Without Silicide

a

SPACER

SPACER

Silicide

-

-

105Aicm2 Contours

-+lOOmm+ III,

With Silicide Fig. 10. PISCES

303

technolo&y

remains low than it is to achieve a low sheet resistance in the silicide process. Nevertheless, the sheet resistance does play an important role in devices that are connected with many squares of diffusion interconnect and in very wide devices that have a low “channel” resistance. However, process choices that optimize the silicide sheet resistivity at the expense of the contact resistivity may not lead to the optimum reduction in parasitic resistance effects. Tables 1 and 4 illustrate the reduction in parasitic series resistance that can be achieved with a salicide process. Hot electron stability is one of the key concerns for today’s scaled devices. In this regard,

pletely silicided device. The effect of the series resistance in non-silicided devices is greatest in the triode region where the resistance of both the source and the drain are important [54]. Second, for the minimum geometry device, illustrated in fig. 9, the largest contributor to the parasitic voltage drop is the metal-to-silicon contact resistance, not the high sheet resistance of the diffusion. The silicide acts to distribute this resistance over the entire drain area significantly lowering the voltage drops across the contact. Thus in the minimum device geometry case, it is more important to ensure that dopant depletion and redistribution is minimized so that contact resistivity

-

metals in VLSI

simulations

of silicided kV/cm;

and unsilicided

I,,,

b devices: (a) electric

I,,,

I,,,

I,,,

Without Silicide field contours

(b) constant current density contours in units of

in units of SO kV/cm

10' A/cm'.

starting

at 110

silicidation of the junctions has two effects. First, the reduction in external series resistance has the adverse effect of reducing the external voltage drop. The resulting higher voltage across the device increases the magnitude of the resultant hot electron instability. For example, Haken [3] reported a 10% decrease in transistor current drive in silicided transistors under conditions in which no degradation was observed in conventional devices (Vd = 6.5 V, V, = 2.75 V, Z,,r, = 0.8 pm). The second effect of silicidation is that the presence of the high-conductivity silicide on the junction causes a subtle shift in the current flow path and in the electric field patterns near the drain as shown in fig. 10. The impact of silicidation on hot carrier reliability is difficult to gauge from simulation results alone. As expected the removal of the 300 mV drop across the source and drain resistances increases the peak drain electric field and the current density passing through the high field region. It is reasonable to expect that the larger current and higher field caused by the silicidation would lead to slightly faster hot electron degradation. The peak drain field of the silicided device was 3.7 kV/cm compared to 3.6 kV/cm for the unsilicided device. Fig. 10 shows that although the intensity of the electric field and current density arc larger with the silicide, the positions of the maximum values are not greatly affected by the presence of the silicide. These results may depend on the design and implementation of the lightly doped drain (LDD) implant and sidewall spacer structure. Another important consideration would be silicidation induced modifications of the lateral diffusion profiles of the LDD implant. Fig. 11 compares hot electron characteristics of silicided and unsilicided devices as characterized by shifts in threshold voltage and saturated current drive. Even though PISCES calculations indicate that the series voltage drop associated with diffusion and contacts is only 0.2 V, equivalent changes in transistor threshold occur at about 0.7 V lower voltage in silicided devices compared to unsilicided ones. Equivalent changes in current drive occurred at 0.2-0.5 V lower voltages in silicided devices. Interestingly, silicided devices

. -

F g ?

.

.

Non-Sllicided

0 A 0 Slllclded

100

Len = 0.95&m

2

3

4

5

4

5

log t (set) a) ml A Non-Silicided 0 0 0 Silicided

2

3 log t (set) b)

Fig. tided

I I.

Comparison

of

and unsilicided

hot

electron

1 pm transistors:

(h) A I, /I,

characteristics

for

sili-

(a) Al/, versus time,

versus time.

deviated from the behavior shown in fig. 11 at high applied voltages. For instance at V,, = 7 V, the threshold shifts of the silicided devices were actually less than those seen at 6.5 V. Likewise, plots of the current drive degradation of silicided devices showed a change of slope at higher volt-

C.M. Osbwn etul./ Incorporation ofmetal silrcides and wfructo~ mrrals itI VLSI technology

ages and times, as evidenced in the 6.5 and 7 V curves of fig. 11b. The unsilicided devices in this study did not exhibit this anomalous behavior. The hot-electron-limited lifetimes of silicided devices are shown in fig. 12, where the time for a fixed shift in either threshold voltage or current

.

L.”

= 0.95pm

a -

6 Non-Silictded

-V,

.12

.I4

.16

.18

.2

.22

= 1OOmV

.24

.26

.28

lN, 01") a)

_

L.”

= 0.95p.m

8 3000 Hours -3% Duty _______-__

drive are plotted as a function of the drain voltage. Here the anomalous high voltage behavior of the silicided devices can be seen in the slope discontinuity in fig. 12b. Extrapolation of the data to 10 years operation at 3% duty cycle, shows that the unsilicided devices can safely operate up to 4.6 V. Depending on which end-of-life criterion is used, the silicided devices can only withstand 3.9-4.5 V. Thus, by reducing the parasitic series resistance, silicidation increases the active voltage across the channel and thereby enhances the hot-electron-induced degradation. The data shown here indicate that the difference between silicided and unsilicided devices is more complex than would be expected merely by the difference in voltage. The silicide process has a beneficial impact on device layout ground rules and packing density, particularly on the rules related to butting n-well and substrate contacts. Butting contacts occur when an n f and p f diffusion implant share the same active area without a field oxide barrier between them. Because the ni to p+ diffusion contact may not be ohmic, a metal contact connecting the two regions is normally required. The placement of the extra metal contact increases the size of the active area and the nt select mask because of the alignment of the contact to the n+ region. If the silicide is used to strap the nf and p+ regions, the high area cost of placing a metal contact may be saved. These two design layouts are illustrated in fig. 13. Another benefit of silitiding CMOS devices is an improvement in the latch-up voltage obtained by better strapping device junctions to the well contact [18]. This benefit is also shown in table 4.

5. Silicide

_ .12

.14

.16

.18 lNd

.2

.22

.24

.26

.28

(V-l) b)

Fig. 12. Hot electron lifetimes for silicided and unsilicided 1 g m devices: (a) based on AV, = 100 mV. (b) based on -1 I, /Id = 10%.

305

as a diffusion

source

Formation of silicide or depositing selective metal prior to junction formation as illustrated in figs. lb and lc provides an alternative to the conventional process. Since the implantation depths are reduced by the stopping power of the higher-atomic-weight surface metal or silicide film, these techniques offer the potential for forming shallower junctions. Furthermore, if the

306

CM. Oshurn c’f al. / Incorporation

of metal silicidrs and refractor)? metals in VISI technolo~

N-WELL BU7TING CONTACT WITH SILICIDE

N-WELL BUTTING CONTACT

Fig. 13. N-well butted contacts between n+ and p

implant depth is less than the film thickness, the end-of-range ion implantation damage is confined within the film. This allows the use of a lower thermal budget since there is no need to either remove implant damage or to diffuse the junction beyond a damage region. Three variations of this process have been extensively studied: silicide as a diffusion source (SADS), where the implant is contained entirely within the silitide; implant through the silicide (ITS), where the as-implanted junction is beyond the silicide/ silicon interface; and implant through metal OTM), where the dopants are implanted through a metal layer into the silicon. In the latter technique, ion beam mixing of the metal helps from the silicide; thus, implantation and silicide formation often occur simultaneously. At the temperatures normally associated with dopant activation after ITM. complete silicidation usually occurs. The SADS process has been studied extensively in our laboratory in an attempt to minimize the total junction depth by minimizing outdiffusion from the silicide. 5.1. Dopant

diffusion from silicides

Control of dopant diffusion from the silicide into the silicon is one of the key issues associated with the SADS process. For the silicides of most interest, the diffusion of at least one of the common dopants is relatively slow within the silicide.

*

diffusions made with versus without cilicide.

For instance the bulk diffusion of B in TiSi, or As in CoSi, are relatively slow at realistic processing temperatures. Thus grain boundary diffusion is responsible for the transport of most dopant atoms from within the silicide to the silitide/silicon interface; however. to maintain a high interfacial doping concentration and thereby low contact resistance, it is necessary to employ high implantation doses of dopant. Most of the SADS and ITS junctions reported in table 6, for instance, use between 5 x 10” and 10’” dopant atoms/cm’ which is a factor of 2-10 higher than would be used for a conventionally formed junction of a comparable depth. Enhanced diffusion of dopant within the silicon has been observed [38] when a silicide source is employed. Because of this enhanced dopant diffusion, only a limited thermal budget is alowed to restrict the junction motion to a few tens of nanometers. Fortunately, the activation energy for this enhanced dopant diffusion is actually higher that for conventional diffusion. Thus controlling junction depth by reducing the drive-in temperature appears to be a viable strategy. Fig. 14 shows the expected dopant motion for boron and arsenic for 10 s rapid thermal annealing using the data of ref. [38]. These data show the potential of controlling the junction motion to only a few nanometers beneath the silicide surfact, thereby allowing the junction depth to be only slightly larger than the silicide thickness.

307

Silicide Material

TiS2 TiSi, TiSi TiSiz TiSi, TiSil TiSii TiSi z TiSi 1 TiSi; TiSi 5 TiSi TiSiz TiSi, TiSi? TiSi? TiSi z TiSi? TiSi 7 TiSi, TiSii TiSi 2 CoSi 1 CoSi 1 CoSi 5 CoSiz CoSi 2 CoSi? CoSi? CoSi 2 C‘oSi CoSi z CoSi z cosi z CoSi L CoSi L CoSi? CoSi?

Thickness (nm) 1 IO I IO 35 45 h5 50 IO0 IO0 150 150 250 550 46 46 XI Xl 46-80 46-80 250 250 - xx - xx 45 45 I30 I30 SO I20 I20 70- 105 550 550 550 5.50 550 550 230 230

PtSi Nisi Pd,Si

4s 47 4s

Dopant species

B AS BF, BF, BF, As AS B B As B BP/As As B AS B B AS B B AS B As BF, As B RF, As B As B B P P AS As B As

X, ,I) (nm)

Ion implantation Energy (keV)

210 170

20

so 40 40

40 I5 I 60 230 300 200 so0

SO

200 - 300 - 160 - 180

II5 2X 1 IS 2X 2X 115 SO SO 100 I0

IS

< so < SO ‘X0 330 160 230 110-175

- 300 - 300

BFZ As BF,

2X 16 50 20 8 SO 20 60

30 100

5ElS SE15 7El5 7El5 7El5 l.SElS SE15 lE16 SE15 5ElS lEl6 < IElh h.7ElS 3ElS 6.7El5 3El.5

SE15 SE15 SE15 SE15 iE1S SE15 SE15 SE15 < 1Elh i IElh < lE16 < IElh < IEl6 < IElh SE15 S-IOEIS

3.5 6.7 2.0 3.X

2.0 2.0 1.52 0.9 0.9 0.45 I .24 0.49 0.49 I .34 0.7- 1.o
_

4.0 2.1 2.7 2.1 2.7

25

5ElS IEl6 6El5

MoSi I MoSiz MoSi? MoSi 1 MoSi,

- 63 100 100 100 100

As AS B As B

- 280 - 300 130 170

200 160 30 160 30

SE15 7ElS 7ElS 7ElS 7El5

GeSi

200

B

- 300

10

Si surface

-2
SE15 l.SEl5 SE15

150 250 150

assuming

IElh

Annealing

Ref.

950” C, 30’ 1050”c‘, IO’

[21 [21

II

1, 23 I.5 2.0 3.2 4000 5
2. I 0.Y -1.0 3.1 2. I 0.x7 I .2x 0.Sh

X IS X

As B B

Leakage

(nA/cm’)

IElh lE16 4ElS 4ElS

100 100 I20

on the original

tl \IIICl‘,C

>I -I+

WSi L WSi L WSiz

I’) X, is based

R, + SAR,,

Dose (cm-‘)

000” c’, IO” YSO” c, 30’ 950” C, 30’ 1000” C. 10’ IOOO” C, IO” 900” C‘. 20” 7-l I00”C x50 o (I‘. 30” X50” (‘, 30” 850” C. 30” X50” C. 30”


900 o c. 30 ’ 900 o c. 30 ’

[7X1 [7X1

1.0’)

I .03 1.OY

I .09

< I.1 1.3 I .s 2.3 < I.1 I .7

I .Oh IO’

2 0.5


[711 I711 (721 [73] (551 [%I [SSI [SSI

1.02 YOO”c, 20”

1.96

4.4 1.2 0.0 2.4 3.h 0.9 3.3 - I.0 Good Very good OK Good OK Good -I -I

[Ill [l II [I 11 [3X] [5Yl 1591

[751 [7Sl [7hl [77]

Ii.5 fxto lOi

I.7

the silicon consumption

1.0’)

3 1

1.15 1.14

- 0.3

1.11

the silicide thickness.

900 o c, 30”

800” C, X00” c. Y50° c, YSO” c, 1000” c, 800” c, 8000”, XOO”C, 700” C, I 100” c, 700” C. 1100” c. 700” c, 1100” c. 900” C, YOO”C.

IO” 10” 30’ 30’ 30” 120’ 120’ 120’ 30” 30” 30” 30” 30” 30” IO” IO”

[This work] [This work] [21 [2] [3X1 [‘I21 [421 [64] [731 1731 [731 [731 1731 (731 [74] [741

X00” C, 2’ 750” C. 30” X00” C. IO”

[3X1 [38] [3X]

450” c, 30’ 950” c. 30’ 1000” c, IO”

b91 WI [701

1000” c, IO” 1ooo”c. IO” 1000” c. 10”

[7Y] [X01 [801 1871 [871

1OOo”c.

10”

[XII

Temperature (C") 1100" 1000

0.7

900"

800"

0.9

0.8

large variation in leakage is seen in devices where the junction is formed after the metal or silicide is deposited. Tables 5 and 6 compare diode data for structures formed by the SADS, ITS (implant through silicide) and ITM (implant through metal) processes. Only a few of the ITM diodes in table 7 exhibit good leakage ( < 10 nA/cm’I. The SADS and ITS diodes generally exhibit low leakage, but the data in table 7 also indicate that careful optimization of the process conditions is necessary to minimize junction leakage. Otherwise unacceptable devices can result from this process also. In table 5 the distinction between the SADS and the ITS processes is simply based on the implanted junction depth, taken at S3K, beyond the range. compared to the silicide thickness: (R,, + 5_1K,/d,,,,,,,,,). Ratios less than one indicate a SADS process; ratios over one signify ITS. Interestingly, from this data there seems to be no clear correlation of the resultant diode leakage to the depth of the initial implantation. Diode leakage data for n’ and pf SADS diodes are given in fig. IS as a function of 10 s RTA annealing temperature. Immediately after ion implantation (5 x 10’5, 28 keV As or 16 keV

700

1.1

1.0

103K (“K-l) Fig. 14. Junction motion born SADS junctions as a function ot 10 s annealing temperature. 5.2.

L%l ice characterktics

In contrast to the widely reported, low leakage data on silicided shallow junctions in table 3, a Table 7 Leakage of implanted-through-metal Metal Material

Thickness (nm)

Dopant species

junctions x, ai (run)

Ion implantation EnCXgy CkeV)

R,, + UR,,

“)

li \,llClLlC

Dose (cm-‘)

Annealing

Leakage

Kel.

II

1, (nA/cm’)

30 18.5

As B

120

60

210

30

SE15 IEl5

O.h3 1.3

Ti

30

As

150

140

5E15

7.5

_ .?.>

I000” c‘. 5’

IS’1

Ti Ti

I IO

AI

200

I30

0.h

77

B

IX3

30

5EIY 5El4

I .x Ih

IOOO” (‘. IO’ IOOO” (‘. IO

[X3] [X31

Mo Mo Mo

50 30 10

A\ As B

IEIO 7El5 7ElS

1.x 2.1 7.7

IOz: 10

1000” c‘. IO” 1000” (‘. IO” I000” (‘. IO”

1791 [X0] [X0]

Mo Mo Mo Mo

50 50 20 20

I 100” <‘. 10”

IX41

30 30

30

5ElS iEl5 5EI-I IEl4 7El5 7ElS

1.3

Mo MO

BF, BF, ASB Ah B

I .8-7.2 4.5-5.3 7.1 2.7

w

35

As

150

2El.5

>I

c’o (‘0

180 - 150 - I.50

160

- 220 - 220

80 100 50-70 15~30

100 I60 35 715

30

I60

I .x

I .h

IO’ 0.3

I .O? I .os

I .o 100

IO” - 300 - 60 x 5

1.13 1.13

1641

[f,5]

I IOO”C. IO”

li+rl [SS] IX51

I .3x

UOO”C‘, 20’ WO” c‘. 20’ 1000”C‘. IO”

I .0x

1000” C‘. IO”

[871 LX71

425 Oc‘. 20’

ls~~l

- IO

I” .Y, ia based on the original Si surface assuming the silicon consumption equals the ailicide thickness. “I Based on complete reaction of metal to form silicidr.

‘)OO” C. 30’

000” <‘. IO-30”

Schottky diodes become junction diodes with good leakage characteristics. One of the more surprising aspects of the data is that only relatively modest annealing temperatures (600-800 ‘0 are needed to produce good diodes. At those temperatures, the projected dopant motion beyond the silicidc, from fig. 14, is expected to be in the 0.1 to 10 nm range. Increased leakage is observed at the higher annealing temperatures, and at least for p+ junctions, is attributed to the formation of oxide charge and interface states around the diode perimeter according to the classical Deal triangle. Subsequent annealing at 450” C in forming gas restores the low leakage condition except for the + junctions at high annealing temperatures ;>900°C) w h ere silicide agglomeration may cause higher leakage. Fig. 16 shows that at 800’ C low-leakage junctions (< 10 nA/cm’) can be formed in both n+ and pt junctions. The diffusion at this temperature, according to fig. 14, is only about 1 nm. At the dopant activity limit, - 2 x 102”/cm3, the depletion depths into the heavily doped junction region for a 5 V reverse bias on the diode amounts to approximately 0.04 and 0.02 nm for As and B junctions, respectively. Interestingly, low leakage pf diodes were obtained for annealing temperatures as low as 600 o C for which the dopant motion beneath the silicide might be expected to be less than the

- 14 As-imp1

400

600

Annealing Fig. 15. Reverse

800

1000

diode leakage of SADS

tion of 10 s annealing

1200

(“C)

Temperature

junctions

as a func-

temperature.

BF, into 45 nm of CoSi,), the leakage current is higher than in unimplanted, control Schottky barrier diodes, presumably because of the radiation damage in the perimeter oxide created during the I/I process. After a 400 a C anneal, that excess leakage is essentially eliminated. Progressively higher annealing temperatures then cause a dramatic reduction in reverse leakage currents as the

-3 I 3 E E zi 0

-5

N+-P n = 1.09

I:

-5 -

6.5 x 1OA cm2

26kev As, 10” 600°C 40 nm CoSi 2

-7

10

8

6

4

2

0 -1

s 2

_

e ; 0

-7 -

% rm z -I

-9 -

and reverse diode leakage characteristics

6.5 x 1OA cm2 16kev BF, , 10” 800°C 40 nm CoSi z

-10

Voltage (V) Fig. Ih. Forward

P+-N n = 1.03

-8

-6

/

-4

-2

0

1

Voltage (V) of n+p and p’n

junctions formed with the SADS

process at 800 o C

width of the depletion layer within the heavily doped region. This result raises the possibility that dopant diffusion into silicon from silicide sour03 may proceed fastcr at vcly low temperaturcs than might be predicted based upon hightempcraturc diffusion data.

6. Summary Self-aligned silicides and selectively deposited rcfractoly metals or silicidcs can play an important role in reducing the parasitic rcsistancc in the contacts and diffusions of submicron semiconductor devices. Reduced series resistance results in higher circuit performance due to both increased transistor current drive capability and reduced interconnect resistance. Furthermore, improvements in CMOS latch-up occur in silicidcd dcviccs. There arc: many very important materials isSLIC’Sassociated with the use of silicide materials in ULSI technology. In particular dopants 01 contamination can play a serious role in intcrfering with the silicidation reaction. The redistribution of dopants out of the silicon substrate can increase contact resistivity and negate any bcneficial effect of silicide cladding. The materials isSLIL'S 1xco111c more scvcre as device dimensions arc scaled down. Silicon consumption by the forming silicide rcquircs that the silicide thickness also be scaled down. In this regard it is observed that C&i, consumes less silicon in the junction region than TiSi,. The non-linear relationship bctwccn metal thickness and silicide sheet resistance and the decreased silicidc thermal stability for thinner films makes the scaling of silicidc thickness ;I serious issue. The LISA of proccsscs, such as SADS, which minimize the dopant motion beyond the silicide offers the best hope of cxtcnding the salicidc technology. Very good results have been reported with this tcchnique. Nevcrthcless, because of the silicon consumption issue with silicidation, the selcctivc dcposition of material on top of the junction region bccomcs a more necessary approach for deep submicron devices.

Acknowledgements The authors would like to acknowledge the contributions of H. Jiang and D.S. Wcn at MC’NC and North Carolina State University in this ongoing work. Diode fabrication and measurement were done with the technical assistance of Jari Arppe. They would also like to thank the staff ot the MCNC silicon processing facility. in particular B. Neptune for the implantation and C. Bcrly for the mctallization for this study. Portions ot this work wcrc‘ sponsored by IBM, Burlington.

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