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Industry standardization of silicon substrates
World Abstracts on Microelectronics and Reliability electronic system with a standby in the main Unit has been studied. It is assumed that failure and repair time distribution of each unit is negative exponential with parameters 2 and/~ respectively. Laplace transforms have been used in solving the difference differential equations.
Redundancy allocations in a system with many stages. K. B. MISRA and C. E. CARTER. Microelectron. & Reliab. 12, 223 (1973). For a large system, optimum allocation of redundancy becomes tedious and sometimes difficult to manage with the existing methods. Where simple formulation or solution technique is available, the solution is generally approximate. On the other hand, with exact formulation and exact solution procedure, the excessive a m o u n t of work involved is such as not to permit the handling of large systems. The present paper initially uses a simple formulation and a simple solution technique to arrive at an approximate solution, and later obtains an exact solution using a search method. This procedure keeps the effort required for an exact solution to a m i n i m u m and is therefore applicable to large problems. The approach is independent of the type of constraints. An example is provided to illustrate the various steps of the procedure. A method of redundancy allocation. K. B. MISRA. Microelectron. & Reliuh. 12, 389 (1973). A simple and new method is provided for allocating redundancies to various stages of a system, to maximize the system reliability under some given constraints. The approach suggested does not require tedious and long computations. The approach may be helpful to system designers to arrive at the solution quickly with little algebraic manipulation. The feasibility of developing standard redundancy allocation charts in the case of simple forms of the constraints is indicated. A fast method for redundancy allocation. K. B. MISRA. Microelectron. & Reliah. 12, 385 (1973). A fast method for redundancy allocation for a series system is described in this paper. The approach makes use of some of the special features of the problem and thereby reduces it to the solution of a set of inequalities. Two illustrative problems one with linear and the other with the non-linear constraints are given as examples. The type of constraints and the number of stages do not set a limitation on the choice of this approach as with the existing methods.
Failure diagnosis using quadratic programming. H. M. MERRILL. IEEE Trans. Reliab. R-22, No. 4 (Oct. 1973). p. 207. This paper discusses the problem of determining which of a large set of possible but improbable malfunctions gave rise to a given set of measurements. The classes of systems under consideration generally lead to underdetermined sets of equations. Three methods of formulating and solving this class of problems are presented: (1) the pseudoinversc method: this leads to an easily-solved computational problem but it is not physically realistic and
13
it tends to give poor results; (2) a pattern recognition approach based on a more realistic problem formulation: unfortunately, the computational problems associated with this formulation may be formidable; and (3) a quadratic programming approach: this is based on minimization of a physically realistic objective function. A modification to eliminate discontinuities in the objective function and a quasilinearization transform the original problem to an inequality-constrained quadratic minimization problem, which is readily solved by Lemke's complementary pivoting method. A sequence of successive quasilinearizations and estimations is defined which is proved to converge to a minium of the original objective function. In tests this convergence occurred very fast. Examples are given; very general classes of problems are discussed which can be handled in this way.
Complex system reliability with general repair time distributions under preemptive resume repair discipline. P. P. GUPTA Microelectron. & Reliab. 12, 351 (1973). The operational behaviour of a Complex System having " N " components in class L 1 connected in series and "m" identical Components in class Lz in parallel redundancy has been investigated. It has been assumed that a failure in LI brings about the complete break-down of the system whereas a failure of two components in class L 2 causes the system to work in a state of reduced efficiency. The repair of the failed components in class L~ and L 2 is carried out under the Preemptive Resume Repair Discipline. Laplace Transforms of various state probabilities, viz. the system is in up state, reduced efficiency state and down state, have been obtained. In the end, asymptotic behaviour of the complex system, has also been examined. Analytic study of a stand-by redundant equipment with switching and shelf life failures. S. PRAKASH. Microelectron. & Reiiab. 12, 329 (1973). An analytic study of a stand-by redundant equipment consisting of two components with imperfect switching-over device, has been carried out under the assumption that the stand-by component may fail during its shelf life. Time dependent probabilities of various states of the equipment havc been obtained. The bchaviour of the equipment under steady state has also been examined. Stand-by redundancy complex system's reliability. R. C. GARG and C. M. SHARMA. Microelectron. & Reliab. 12, 321 (1973). In this paper the behaviour of a complex system having two classes of components has been investigated. The configuration of the system is such that in one class the components are connected in series and in the other class in stand-by redundancy. Further, it has been assumed that repair of the failed components of both the classes is carried under the head of line repair discipline. The Laplace transforms of various state probabilities have been obtained. Asymptotic behaviour of such a system has also been examined. In the end a particular case has been derived.
4. M I C R O E L E C T R O N I C S - - G E N E R A L
Industry standardization of silicon substrates. J. W. CARLSON. Solid St. Technol. Sept. 1973. p. 49. The subject of substrate standardization is explained in depth. The value of standardization is developed, emphasizing the benefits of in-
creasing product availability and delivery time by improvements in shaping efficiencies and inventory maintenance. The subject is timely because of the material supply status in a period of increasing needs. The standards were developed
14
World Abstracts on Microelectronics and Reliability
by a review of the industries custom orders and concern the mechanical, structural and surface properties of the substrates. Product classifications are developed including type, orientation, diameter, thickness, slice surface alignmcnt and fiat. A system to identify the slice orientation and type visually to climinatc the problem of product mixing is provided. Visual aids are used to describe the various features.
The current trend in CMOS technology. V. YATES. EEN Dec. i973. Since the first integrated circuits were produced. we have seen one new logic family after another introduced Each new family offered some major advantage over the last but brought with it its own disadvantages, ttow important these disadvantages and advantages were depended on the precisc application. So far there has not becn a family that offercd the best of all worlds and. in all probability, there never will be. Yield optimization of integrated circuits. T. YANAGAWA. I EE E Trans. on Eh'ctron Derices. ED-20 19 (1973). A design approach is presented that optimizes the component areas of integrated circuits so as to maximize the yield. The performance index to be optimized is defined as the chip yield divided by the chip area. which corresponds to the number of good chips in a wafer. The area of each component is determined to maximize this performance index by a nonlinear programming technique. The design of integrated circuits with respect to the yield may be mostly narrowed down to the determination of component areas, since the process parameters cannot be adjusted individually for each circuit component. This design approach is described in
5. M I C R O E L E C T R O N I C S
more detail for the kinds of components whose surface areas cannot be uniquely determined by their nominal parameter values. As a demonstration, the width of a diffused resistor in bipolar integrated circuits was optimized for some example circuits. Some useful results have been obtained for the design of circuit patterns.
Liquid immersion cooling of small electronic devices. E. BAKER. Microeh,ctron. & Reliah, 12, 163 (1973). The primary purpose of this investigation was to examine liquid immersion techniques lot cooling minute heat sources. Thc study dclnonstrated that nuclcate boiling is an effective means of cooling larger heat sources. However, for heat sources with surface areas less than 0-01 cm 2, nucleate boiling was found to offer very little improvement in convective heat transfer over free convection with the same liquid. In addition, nucleate boiling may introduce mechanical stresses, contamination and physical design problems. For these reasons. two alternatives to boiling fforced convection and bubble induced mixing) were also investigated which reduced (or bypassedl some of these problems. In the forced convection study, boundary layer analysis showed the convective heat transfer coefficient would increase significantly as the heat source size decreased, This was verified experimentally with two different liquids. The experiments found the convection coefficient increased by a factor of 15 when the source size was decreased from 2-00 to 0-01 cm 2. A similar increase was notcd in the free convection and bubble induced mixing experiments. In addition, with small sources both bubble induced mixing and forced convection gave significantly larger heat transfer coefficicnts than were practical with boiling.
DESIGN
The thermal demands of electronic design. S. T. GROSSMAN. Electronics ( N o v 1973). p. 97. The dense packaging, fast switching of ICs today create so much heat that designers must bone up on old remedies, find out about new ones. Digital-lC models for computer-aided design--I. TTI, NAND gates. J. R. GREENBAUM. Eh, ctronics (Dec. 1973). p. 121. Computer models can be generated for accurate simulation of digital integrated circuits: the 1Cs are treated as simple individual devices, rather than as a complex collection of transistors and diodes. Dynamic malfunction limits in high-speed TTL and ECL integrated digital gates. M. ABDEL-LATII: and M. J. O. STRUTT. Microeh'clron. & Reliab. 12, 57 (1973). The thrcshold conditions for dynamic malfunction in high-speed TTL and ECL integrated digital gates have been investigated experimentally. The higher the switching speed of an integrated digital gate, the more sensitive it is to dynamic malfunction. The delay- and storage-times have been experimentally found to be nearly independent of the input pulse amplitude, while the fall- and rise-times arc approximately inverse functions of the amplitude of the input current pulse. Recent advances in negative and positive photoresist technology. D. J. SYKES. Solid St. Technol. (August 1973). p. 53. A new negativc resist is described for applications where
AND
CONSTRUCTION
conventional resist oxygen sensitivity is a process design limiting parameter. Contact printing over steps is less critical since discrete areas of low film thickness do not cxhibit the troublesome oxygen desensitization reaction. Reduced oxygen sensitivity, coupled with enhanced spectral sensitivity to longcr wave lengths, make this an efl'ectivc negative resist for contact, proximity and projection printing techniques. A positive resist system is described. Characteristics, processing data. and functional applications are presented. Specific process parameter and recommended processing conditions including exposure, pre-bakc, postbake, and development are discussed and illustrated.
Single-layer packaging slashes ceramin-DIP costs in half. J. BARNHY. Eh, ctronics (Oct. 1973). p. 119. By eliminating two layers of material from the traditional package, device manufacturers are reducing the costs and boosting the reliability of the resulting ceramic packages. Large IC chip impact analysis and handling protection. L. K. KARSTADT, C. M. HSIEH. W. G. BURGER and W. A. COSGROVE. Solid St. Technol. (August 1973). p. 41. With large-scale integration, more components are being packed into available real estate, making chips larger and heavier. Their greater kinetic energy in chip-to-chip impacts must be considered both in designing chips and their handling systems. An insulating overlay such as glass protects chips
Redundancy allocations in a system with many stages. K. B. MISRA and C. E. CARTER. Microelectron. & Reliab. 12, 223 (1973). For a large system, optimum allocation of redundancy becomes tedious and sometimes difficult to manage with the existing methods. Where simple formulation or solution technique is available, the solution is generally approximate. On the other hand, with exact formulation and exact solution procedure, the excessive a m o u n t of work involved is such as not to permit the handling of large systems. The present paper initially uses a simple formulation and a simple solution technique to arrive at an approximate solution, and later obtains an exact solution using a search method. This procedure keeps the effort required for an exact solution to a m i n i m u m and is therefore applicable to large problems. The approach is independent of the type of constraints. An example is provided to illustrate the various steps of the procedure. A method of redundancy allocation. K. B. MISRA. Microelectron. & Reliuh. 12, 389 (1973). A simple and new method is provided for allocating redundancies to various stages of a system, to maximize the system reliability under some given constraints. The approach suggested does not require tedious and long computations. The approach may be helpful to system designers to arrive at the solution quickly with little algebraic manipulation. The feasibility of developing standard redundancy allocation charts in the case of simple forms of the constraints is indicated. A fast method for redundancy allocation. K. B. MISRA. Microelectron. & Reliah. 12, 385 (1973). A fast method for redundancy allocation for a series system is described in this paper. The approach makes use of some of the special features of the problem and thereby reduces it to the solution of a set of inequalities. Two illustrative problems one with linear and the other with the non-linear constraints are given as examples. The type of constraints and the number of stages do not set a limitation on the choice of this approach as with the existing methods.
Failure diagnosis using quadratic programming. H. M. MERRILL. IEEE Trans. Reliab. R-22, No. 4 (Oct. 1973). p. 207. This paper discusses the problem of determining which of a large set of possible but improbable malfunctions gave rise to a given set of measurements. The classes of systems under consideration generally lead to underdetermined sets of equations. Three methods of formulating and solving this class of problems are presented: (1) the pseudoinversc method: this leads to an easily-solved computational problem but it is not physically realistic and
13
it tends to give poor results; (2) a pattern recognition approach based on a more realistic problem formulation: unfortunately, the computational problems associated with this formulation may be formidable; and (3) a quadratic programming approach: this is based on minimization of a physically realistic objective function. A modification to eliminate discontinuities in the objective function and a quasilinearization transform the original problem to an inequality-constrained quadratic minimization problem, which is readily solved by Lemke's complementary pivoting method. A sequence of successive quasilinearizations and estimations is defined which is proved to converge to a minium of the original objective function. In tests this convergence occurred very fast. Examples are given; very general classes of problems are discussed which can be handled in this way.
Complex system reliability with general repair time distributions under preemptive resume repair discipline. P. P. GUPTA Microelectron. & Reliab. 12, 351 (1973). The operational behaviour of a Complex System having " N " components in class L 1 connected in series and "m" identical Components in class Lz in parallel redundancy has been investigated. It has been assumed that a failure in LI brings about the complete break-down of the system whereas a failure of two components in class L 2 causes the system to work in a state of reduced efficiency. The repair of the failed components in class L~ and L 2 is carried out under the Preemptive Resume Repair Discipline. Laplace Transforms of various state probabilities, viz. the system is in up state, reduced efficiency state and down state, have been obtained. In the end, asymptotic behaviour of the complex system, has also been examined. Analytic study of a stand-by redundant equipment with switching and shelf life failures. S. PRAKASH. Microelectron. & Reiiab. 12, 329 (1973). An analytic study of a stand-by redundant equipment consisting of two components with imperfect switching-over device, has been carried out under the assumption that the stand-by component may fail during its shelf life. Time dependent probabilities of various states of the equipment havc been obtained. The bchaviour of the equipment under steady state has also been examined. Stand-by redundancy complex system's reliability. R. C. GARG and C. M. SHARMA. Microelectron. & Reliab. 12, 321 (1973). In this paper the behaviour of a complex system having two classes of components has been investigated. The configuration of the system is such that in one class the components are connected in series and in the other class in stand-by redundancy. Further, it has been assumed that repair of the failed components of both the classes is carried under the head of line repair discipline. The Laplace transforms of various state probabilities have been obtained. Asymptotic behaviour of such a system has also been examined. In the end a particular case has been derived.
4. M I C R O E L E C T R O N I C S - - G E N E R A L
Industry standardization of silicon substrates. J. W. CARLSON. Solid St. Technol. Sept. 1973. p. 49. The subject of substrate standardization is explained in depth. The value of standardization is developed, emphasizing the benefits of in-
creasing product availability and delivery time by improvements in shaping efficiencies and inventory maintenance. The subject is timely because of the material supply status in a period of increasing needs. The standards were developed
14
World Abstracts on Microelectronics and Reliability
by a review of the industries custom orders and concern the mechanical, structural and surface properties of the substrates. Product classifications are developed including type, orientation, diameter, thickness, slice surface alignmcnt and fiat. A system to identify the slice orientation and type visually to climinatc the problem of product mixing is provided. Visual aids are used to describe the various features.
The current trend in CMOS technology. V. YATES. EEN Dec. i973. Since the first integrated circuits were produced. we have seen one new logic family after another introduced Each new family offered some major advantage over the last but brought with it its own disadvantages, ttow important these disadvantages and advantages were depended on the precisc application. So far there has not becn a family that offercd the best of all worlds and. in all probability, there never will be. Yield optimization of integrated circuits. T. YANAGAWA. I EE E Trans. on Eh'ctron Derices. ED-20 19 (1973). A design approach is presented that optimizes the component areas of integrated circuits so as to maximize the yield. The performance index to be optimized is defined as the chip yield divided by the chip area. which corresponds to the number of good chips in a wafer. The area of each component is determined to maximize this performance index by a nonlinear programming technique. The design of integrated circuits with respect to the yield may be mostly narrowed down to the determination of component areas, since the process parameters cannot be adjusted individually for each circuit component. This design approach is described in
5. M I C R O E L E C T R O N I C S
more detail for the kinds of components whose surface areas cannot be uniquely determined by their nominal parameter values. As a demonstration, the width of a diffused resistor in bipolar integrated circuits was optimized for some example circuits. Some useful results have been obtained for the design of circuit patterns.
Liquid immersion cooling of small electronic devices. E. BAKER. Microeh,ctron. & Reliah, 12, 163 (1973). The primary purpose of this investigation was to examine liquid immersion techniques lot cooling minute heat sources. Thc study dclnonstrated that nuclcate boiling is an effective means of cooling larger heat sources. However, for heat sources with surface areas less than 0-01 cm 2, nucleate boiling was found to offer very little improvement in convective heat transfer over free convection with the same liquid. In addition, nucleate boiling may introduce mechanical stresses, contamination and physical design problems. For these reasons. two alternatives to boiling fforced convection and bubble induced mixing) were also investigated which reduced (or bypassedl some of these problems. In the forced convection study, boundary layer analysis showed the convective heat transfer coefficient would increase significantly as the heat source size decreased, This was verified experimentally with two different liquids. The experiments found the convection coefficient increased by a factor of 15 when the source size was decreased from 2-00 to 0-01 cm 2. A similar increase was notcd in the free convection and bubble induced mixing experiments. In addition, with small sources both bubble induced mixing and forced convection gave significantly larger heat transfer coefficicnts than were practical with boiling.
DESIGN
The thermal demands of electronic design. S. T. GROSSMAN. Electronics ( N o v 1973). p. 97. The dense packaging, fast switching of ICs today create so much heat that designers must bone up on old remedies, find out about new ones. Digital-lC models for computer-aided design--I. TTI, NAND gates. J. R. GREENBAUM. Eh, ctronics (Dec. 1973). p. 121. Computer models can be generated for accurate simulation of digital integrated circuits: the 1Cs are treated as simple individual devices, rather than as a complex collection of transistors and diodes. Dynamic malfunction limits in high-speed TTL and ECL integrated digital gates. M. ABDEL-LATII: and M. J. O. STRUTT. Microeh'clron. & Reliab. 12, 57 (1973). The thrcshold conditions for dynamic malfunction in high-speed TTL and ECL integrated digital gates have been investigated experimentally. The higher the switching speed of an integrated digital gate, the more sensitive it is to dynamic malfunction. The delay- and storage-times have been experimentally found to be nearly independent of the input pulse amplitude, while the fall- and rise-times arc approximately inverse functions of the amplitude of the input current pulse. Recent advances in negative and positive photoresist technology. D. J. SYKES. Solid St. Technol. (August 1973). p. 53. A new negativc resist is described for applications where
AND
CONSTRUCTION
conventional resist oxygen sensitivity is a process design limiting parameter. Contact printing over steps is less critical since discrete areas of low film thickness do not cxhibit the troublesome oxygen desensitization reaction. Reduced oxygen sensitivity, coupled with enhanced spectral sensitivity to longcr wave lengths, make this an efl'ectivc negative resist for contact, proximity and projection printing techniques. A positive resist system is described. Characteristics, processing data. and functional applications are presented. Specific process parameter and recommended processing conditions including exposure, pre-bakc, postbake, and development are discussed and illustrated.
Single-layer packaging slashes ceramin-DIP costs in half. J. BARNHY. Eh, ctronics (Oct. 1973). p. 119. By eliminating two layers of material from the traditional package, device manufacturers are reducing the costs and boosting the reliability of the resulting ceramic packages. Large IC chip impact analysis and handling protection. L. K. KARSTADT, C. M. HSIEH. W. G. BURGER and W. A. COSGROVE. Solid St. Technol. (August 1973). p. 41. With large-scale integration, more components are being packed into available real estate, making chips larger and heavier. Their greater kinetic energy in chip-to-chip impacts must be considered both in designing chips and their handling systems. An insulating overlay such as glass protects chips