Influence of multi-finger layout on the subthreshold behavior of nanometer MOS transistors

Microelectronics Reliability 52 (2012) 1606–1609

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Influence of multi-finger layout on the subthreshold behavior of nanometer MOS transistors S.-L. Siu a,⇑, W.-S. Tam a, H. Wong a, C.-W. Kok a, K. Kakusima b, H. Iwai b a b

Department of Electronic Engineering, City University of Hong Kong, Tat Chee Avenue, Kowloon, Hong Kong Frontier Collaborative Research Center, Tokyo Institute of Technology, Nagatsuta, Midori-ku, Yokohama, Kanagawa 226-8502, Japan

a r t i c l e

i n f o

Article history: Received 5 August 2011 Accepted 11 September 2011 Available online 14 October 2011

a b s t r a c t This work studies the effects of number of gate finger on the DC subthreshold characteristics of multifinger nanoscale MOS transistors. We found in not optimally-tempered nanoscale (gate length = 90 nm) MOS transistors that the significantly deteriorated subthreshold characteristics can be effectively improved by increasing the number of gate finger. This observation was explained with a modified subthreshold slope model based on voltage-doping transformation theory. Hence, the multi-finger structure does not only enhance the operation frequency, it also improves the subthreshold DC characteristics of the nanoscale MOS transistors. Ó 2011 Elsevier Ltd. All rights reserved.

1. Introduction Radio-Frequency (RF) CMOS technology has attracted tremendous research interests because of the system integration consideration and to cope with the rapid development of mobile communication technology [1–4]. Thanks to the nanoscale CMOS technology, the intrinsic cutoff frequency of CMOS device has now exceeded hundreds GHz. Another important technology for making RF CMOS to be viable is the introduction of multi-finger gate structure [5]. CMOS devices were hindered for high-frequency applications because of their large parasitic gate resistance [6]. This issue had been readily solved by using the multi-finger gate structure. However, some challenges still remain particularly on the hot-carrier reliability and accurate device models for circuit designs [7–9]. The DC and high-frequency models for the multi-finger nanometer MOS transistors are still not very precise because of some uncertainties on the charge and electric field distribution around the fingers [10]. It was found that the threshold voltage and the DC current–voltage characteristics of multi-finger transistors depart greatly from its equivalent single-finger transistor [9]. The subthreshold characteristics of RF CMOS devices are also important because the MOS transistor operated at subthreshold mode has demonstrated some unique features particularly for low-voltage and low-power operation [11–13]. On the other hand, as the charge transport mechanism in the subthreshold mode of operation is different from that in the ohmic or saturation region, studying the subthreshold characteristics will help for better understanding of the effects of some of the parasites associated ⇑ Corresponding author. E-mail address: [email protected] (S.-L. Siu). 0026-2714/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2011.09.011

with the gate fingers. This work reports the effect of multi-finger structure on the subthreshold characteristics of MOS transistor. Section 2 outlines the background theory for subthreshold swing modeling and characterization. The layout structure of the MOS transistor empolyed in this experiment was shown in Fig. 1. The experimental results are presented in Section 3 where we reported a new observation that the subthreshold slope can be reduced by using introducing a larger number of gate fingers. Section 4 concludes the findings and observation presented in this work.

2. Theoretical background For MOS transistor operated in the subthreshold region, i.e. the gate voltage, VGS, is smaller than the threshold voltage, VT, the surface region is in fact a bipolar transistor [14,15]. If the base width (channel length) is short enough and the drain voltage (VDS) is large enough [15], the bipolar transistor can be turned on and subthreshold conduction takes place between the source and drain. This subthreshold drain current is modelled by [16]:

sffiffiffiffiffiffiffiffiffiffiffiffiffiffi

IDS ¼









lW eSi qNA 2 ðV GS  V T Þ V DS V exp  1  exp L mV th 4uB th V th

 ð1Þ

where W/L is the aspect ratio of the transistor, l is the channel mobility, NA is the substrate doping concentration, eSi is the permittivity of silicon, Vth = kT/q is the thermal voltage, uB is the bulk potential and m is the body factor which is given by:

sffiffiffiffiffiffiffiffiffiffiffiffiffiffi eSi qNA 1 C D þ C it  m¼1þ ¼1þ C ox 4uB C ox

ð2Þ

S.-L. Siu et al. / Microelectronics Reliability 52 (2012) 1606–1609

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Fig. 1. Illustration of the layout structure of multi-finger MOS transistors.

where CD and Cit are the capacitance due to the channel depletion charges and the interface oxide charges, respectively. A modification was made by Skotnicki et al. [17] to include the channel length and doping effects.

m¼1þ

  C D þ C it eSi xj 3W pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi þ 1 þ 1 þ 2V DS =UD 4L C ox C ox L2

ð3Þ

where xj is the junction depth of the drain junction and UD is the potential barrier of the drain. The subthreshold slope, S, can be evaluated from experimental characteristics using the following equation:

S¼

 1 dðlog IDS Þ kT ¼ 2:3 m ðin mV=decÞ dV GS q

ð4Þ

According to Eq. (2), when the depletion capacitance is much smaller than the oxide capacitance, the surface potential is mainly governed by the gate voltage, m = 1, and S  60 mV/dec at room temperature which is the theoretical limit. A typical S value is about 100 mV/dec because of the present of depletion and interface charges. 3. Results and discussion Several multi-finger n-channel MOS transistors with gate lengths of 90, 100, and 110 nm were used in this investigation. The finger width is 2 lm and the numbers of finger are 6, 12, 24 and 48. The gate oxide was grown with N2O oxidation with an equivalent oxide thickness of 1.2 nm. On wafer measurements were conducted on a Cascade 12861 semi-automatic probe station and the device characteristics were measured with Agilent E8363B network analyzer piloted by IC-CAP device modeling software [18]. Other characteristics of these devices had been reported elsewhere [10]. It was found that RF subthreshold characteristics of multifinger nanoscale MOS transistors were governed by the number of fingers also. The subthreshold channel resistance increases and the drain inductance decreases as the number of finger increases because of the more significant electron transport along the finger boundaries. In addition, the channel resistance may be governed by the drain-induced barrier lowering in a very short gate length [10]. This work further explores the effect of finger number on the DC characteristics. Fig. 2 shows the DC subthreshold characteristics

of various transistors. The characteristics were normalized to the same channel width of 12 mm which is equivalent to six fingers. In principle, the characteristics should be identical for different numbers of finger after this treatment. As shown in Fig. 2, the ON current are essentially the same for finger number nf = 6, 12, and 24 for gate length of 90 and 110 nm. For nf = 48, the ON current is slightly smaller. However, the difference in the subthreshold characteristics for Lg = 90 nm is quite obvious. Fig. 3 plots the subthreshold slope as a function of number of finger. It indicates that the subthreshold slope decreases gradually as the finger number increases for gate length of 90 nm. However, for gate length of 100 or 110 nm, the subthreshold slope remains fairly unchanged for different numbers of finger. This observation has not been reported before and new theory needs to be developed in order to explain this phenomenon. On the other hand, the subthreshold slope decreases as the channel length increases. These results can be explained with Eq. (3). Longer channel length leads to better electrostatic integrity when the other parameters are the same and thus smaller subthreshold slopes are found. For gate length of 110 nm, the subthreshold slope reduce to about 92 mV/dec and it remains fairly unchanged as the number of finger increases provides that the total gate width is the same. Under this situation, the subthreshold slope is mainly determined by the depletion capacitance and the interface trap density which should have little variation as long as the total gate widths are the same. The results agree with the theory predicted by Skotnicki et al. [17]. However, for 90-nm long transistors, the subthreshold slope decreases as the gate number of finger increases. This trend cannot be explained with Eq. (3). To have clearer picture on this discrepancy, we further study the drain bias dependence of the subthreshold slope. As depicted in Fig. 4, significant degradation of the subthreshold swing was recorded for larger drain biases because of the drain-induced barrier lowering (DIBL). For VDS increasing from 0.05 V to 0.6 V, the subthreshold current increases by more than one order of magnitude. It indicates that the transistor should be in the punchthrough mode. Fig. 5 plots the subthreshold slope as a function of drain bias for different numbers of gate finger. This figure clearly indicates that the finger number dependence is also a function of the drain bias. For transistor with shorter gate length, the drain bias dependence is much stronger (see Fig. 5a). The subthreshold slope changes from less 110 mV/dec at VDS = 0.05 to over 350 mV/dec at

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Fig. 4. Effect of drain bias on the subthreshold characteristics of 90 nm long gate length.

Fig. 2. Subthreshold characteristics of MOS transistors with different gate lengths and numbers of finger. The finger width was 2 lm. The characteristics of transistors with channel width of 12, 24, and 48 fingers were normalized to 2 lm width, i.e. equivalent to six fingers width.

Fig. 3. Plot of subthreshold slope as a function of number of fingers.

Fig. 5. Plot of subthreshold slope as function of drain bias and number of finger. (a) Lg = 90 nm; and (b) Lg = 110 nm.

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VDS = 1.5 V. In a well-tempered transistor (see Fig. 5b), the subthreshold slope shows weaker dependencies on the drain bias and number of finger. The subthreshold slope changes from about 93 mV/dec to about 115 mV/dec as drain voltage increases from 0.05 V to 1.5 V for finger number of 6, 12, and 24. This is because the DIBL effect is smaller in a long channel or well-tempered devices. These observations also agree with the voltage-doping transformation theory proposed by Skotnicki et al. [17]. For transistor with finger number of 48, significant increases of subthreshold slope was found. The physical mechanism for this observation is still not clear. One possible mechanism is the contribution of boundary defects along the gate fingers. In addition, the subthreshold slope at different drain biases still demonstrates some strong number of finger dependencies. Increase the finger number can reduce the subthreshold slope as well as the drain bias dependence. Based on the about observation and followed the approach given by Skotnicki et al. [17], the subthreshold slope for multi-finger nanometer transistor can be revised to:

  C D þ C it m¼ 1þ C ox   pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi eSi xj 3W 1 þ 1 þ 2V DS =UD 1 þ 1 þ 8L nf C ox L2

ð5Þ

That is, in well-tempered transistor, or L  xj, the second term in Eq. (5) may be negligible and m can be approximated by the classical formula and it is weak VDS and nf dependence. For transistors that are not well-tempered, the second term of Eq. (5) cannot be neglected and the subthreshold slope is governed by the number of finger and drain bias. These dependencies agree with the results reported in Fig. 5. 4. Conclusion The subthreshold characteristics of multi-finger nanoscale MOS transistors have been studied in detail. We found that the subthreshold slope does not only depend on the gate length but also on the number of gate finger. The dependence of number of gate finger is more obvious in shorter channel length devices because of more obvious drain-induced barrier lowering effect and poorer electrostatic integrity. These dependencies can be understood with the modified subthreshold slope model based on voltage-doping transformation theory. The present study indicates that, in addition to the enhanced frequency response as reported earlier, the

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multi-finger structure also improves the subthreshold DC characteristics of nanoscale MOS transistors. Acknowledgments The authors would like to thank Prof. V. Filip for his help in proof reading this manuscript. The work described in this paper was partially supported by the Strategic Research Grant of City University (Project No. 7008103), Hong Kong and the Global COE Program ‘‘Photonics Integration-Core Electronics’’ of Tokyo Institute of Technology, Japan. References [1] Liou JJ, Schwierz F. RF MOSFET: recent advances, current status and future trends. Solid-State Electron 2003;47:1881–95. [2] Cheng Y, Deen MJ, Chen CH. MOSFET modeling for RF IC design. IEEE Trans Electron Dev 2005;52:1286–303. [3] Kim CW, Kang MS, Anh PT, Kim HT, Lee SG. An ultra-wideband CMOS low noise amplifier for 3–5-GHz UWB system. IEEE J Solid-State Circ 2005;40:544–7. [4] Lin CY, Chu LW, Ker MD. Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process. Microelectron Reliab 2011;51:1315–24. [5] Enz CC, Cheng Y. MOS transistor modeling for RF IC design. IEEE J Solid-State Circ 2000;35:186–201. [6] Jin X, Ou JJ, Chen CH, Liu W, Deen MJ, Gray PR, et al. An effective gate resistance model for CMOS RF and noise modeling. In: Technical digest of int. electron devices meeting; 1998. p. 961–4. [7] Yuan JS, Ma J, Yeh WK, Hsu CW. Impact of strain on hot electron reliability of dual-band power amplifier and integrated LNA-mixer RF performances. Microelectron Reliab 2010;50:807–12. [8] Naseh S, Deen JM, Marinov O. Effects of hot-carrier stress on the performance of the LC-tank CMOS oscillators. IEEE Trans Electron Dev 2003;50:1334–9. [9] Wong H, Fu Y, Liou JJ. Hot carrier reliability and breakdown characteristics of multi-finger RF MOS transistors. Microelectron Reliab 2009;49:13–6. [10] Siu SL, Wong H, Tam WS, Kakusima K, Iwai H. Subthreshold parameters of radio-frequency multi-finger nanometer MOS transistors. Microelectron Reliab 2009;49:387–91. [11] Yang LA, Yu CL, Hao Y. A new model of subthreshold swing for sub-100 nm MOSFETs. Microelectron Reliab 2008;48:342–7. [12] Lim KM, Ng CY, Yeo KS, Do MA. A 2.4 GHz ultra low power subthreshold CMOS low-noise amplifier. Microw Opt Technol Lett 2007;49:743–4. [13] Giustolisi G, Palumbo G. A low-voltage low-power voltage reference based on subthreshold MOSFETs. IEEE J Solid State Circ 2003;38:151–4. [14] Wong H. Nano CMOS gate dielectric engineering. CRC Press; 2011. [15] Wong H. Modeling of the parasitic transistor-induced drain breakdown in MOSFET’s. IEEE Trans Electron Dev 1996;43:2190–6. [16] Sze SM, Ng KK. Physics of semiconductor devices. 3rd ed. New York: Wiley; 2007 [chapter 6]. [17] Skotnicki T, Beranger CF, Gallon C, Boeuf F, Monfray S, Payet F, et al. Innovative materials, devices, and CMOS technologies for low-power mobile multimedia. IEEE Trans Electron Dev 2008;55:96–130. [18] Agilent IC-CAP .