- Email: [email protected]
Influence of textured c-Si surface morphology on the interfacial properties of heterojunction silicon solar cells
Journal of Non-Crystalline Solids 358 (2012) 2223–2226
Contents lists available at SciVerse ScienceDirect
Journal of Non-Crystalline Solids journal homepage: www.elsevier.com/ locate/ jnoncrysol
Influence of textured c-Si surface morphology on the interfacial properties of heterojunction silicon solar cells Guorong Li, Yuqin Zhou ⁎, Fengzhen Liu Graduate University of the Chinese Academy of Sciences, Beijing 100049, PR China
a r t i c l e
i n f o
Article history: Received 30 September 2011 Received in revised form 29 November 2011 Available online 23 January 2012 Keywords: HIT solar cells; Textured surface; Interfacial property; Passivation; HWCVD
a b s t r a c t For the HIT solar cells, the properties of interface between intrinsic thin film and c-Si are critical for the resulting device. The interfacial properties mainly depend on the surface passivation quality of c-Si, which is found to be affected by the morphology of textured surfaces. In this study, four kinds of textured c-Si substrates are fabricated: large pyramids without chemical polished (CP), large pyramids with CP, small pyramids without CP and small pyramids with CP. We investigated the effects of textured-surface morphology on the passivation of c-Si, the thin layer coverage and the interfacial properties of heterojunction prepared by HWCVD. Minority carrier lifetime measurements show that the wafer with small pyramids leads to better surface passivation than the one with large pyramids. The good coverage and contact between the thin film and the substrate can be achieved and no epitaxial growth occurs on the wafer with small pyramids through the study of TEM. Dark I-V measurements reveal that the heterojunction on wafer with small pyramids and CP has low recombination at the a-Si:H/c-Si interface. Our results indicate that the surface with small pyramids and low surface roughness is beneficial to the performance of HIT solar cells. Crown Copyright © 2012 Published by Elsevier B.V. All rights reserved.
1. Introduction The heterojunction with intrinsic thin-layer (HIT) solar cells are of great interest for the photovoltaic development due to their highefficiency and low-cost fabrication process [1,2]. Up to now, Sanyo has achieved the world's highest conversion efficiency of 23% for solar cells fabricated by plasma enhanced chemical vapor deposition (PECVD) on an n-type Cz wafer [3]. For HIT solar cells, the interfacial properties between a-Si:H and c-Si make significant influence on the cell's efficiency. Such good passivation of the wafer surfaces becomes critical in making device voltage reach higher value [4]. The quality of surface passivation is mainly determined by the microstructure of a-Si:H layer, which not only depends on the deposited parameters and the deposited technology but also is related to the surface morphology of c-Si [5,6]. Generally, the Si wafers are textured randomly by chemical anisotropic etching with a NaOH or KOH solution, which is the standard process to obtain pyramids with the average size of 8-10μm[7,8]. As an alkaline and strong oxidizing reagent, NaClO can be used to obtain small and uniformed pyramids with the average size of 1–3μmon the Si wafer and to remove organic contaminants on the surface of wafer [9]. It is assumed that the wafer with small and uniformed pyramids owns advantages in HIT cell preparation, because the surface with small roughness is beneficial to improve the coverage and contact between the thin layers and substrate, which is helpful to increase the
⁎ Corresponding author. Tel./fax: + 861088256653. E-mail address: [email protected] (Y. Zhou).
open voltage and fill factor of solar cells [10]. However, the good passivation of Si wafer is regularly more cumbersome to be realized on the textured surface, and it is likely due to the presence of localized recombinative paths situated at the pyramid valleys [11]. Thus, in order to obtain the higher-efficiency cell on textured substrate, we have to avoid the appearance of the epitaxial growth and guarantee the good contact between the thin layers and substrate, also the perfectly performed passivation on textured surface is necessary. Here, we presented that this issue may be resolved by selecting silicon substrate morphology and fabricating the heterojunction by HWCVD. In this paper, we prepared the Si heterojunction by HWCVD and studied the effects of the textured-surface morphology on the thin layer coverage, the passivation of c-Si and the interfacial properties of heterojunction. Minority carrier lifetime has been measured after the H treatment and deposition of a-Si intrinsic layer in order to study the passivation effect. The microstructure of i-layer and the contact between i-layer and the substrate were studied through TEM. Dark I-V measurements were conducted to analyze the interfacial properties of heterojunction with the structure of Al/(n)a-Si:H/(i) a-Si:H/(p)c-Si/Al. 2. Experimental details The c-Si substrates (CZ, P-type, 1-10 Ω cm) with (100) surface orientation were used. First, to eliminate the native oxide on the surface, the wafer was treated in 2% HF solution for 60 s before the saw damage removing and texturation. The saw damage was removed in a 20 wt% NaOH solution at 80 °C for 10 min. Then the samples were
0022-3093/$ – see front matter. Crown Copyright © 2012 Published by Elsevier B.V. All rights reserved. doi:10.1016/j.jnoncrysol.2011.12.106
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G. Li et al. / Journal of Non-Crystalline Solids 358 (2012) 2223–2226
Table 1 Conditions for NaOH and NaClO texturizaiton. Sample
Solution
Concentration
Additives
Temperature and Time
CP
Large Large + CP Small Small + CP
NaOH NaOH NaClO NaClO
3 wt.% 3 wt.% Available Chlorine 9% Available Chlorine 9%
1wt%Na2SiO3 + 7vol%IPA 1wt%Na2SiO3 + 7vol%IPA 15 V%C2H5OH 15 V%C2H5OH
80 °C 80 °C 80 °C 80 °C
– HNO3 + CH3COOH + HF – HNO3 + CH3COOH + HF
50 min 50 min 80 min 80 min
Table 2 Deposition conditions for the thin films.
H treatment (i)a-Si:H (n)a-Si:H
Ts(°C)
Tf(°C)
H2(sccm)
SiH4(sccm)
PH5(sccm)
Pressure(Pa)
Time(s)
25 25 25
1850 1780 1780
20 3 3
– 1 1
– – 0.01
10 1 2
30 15 42
textured with the solution of NaClO and NaOH, respectively. The texturing parameters are listed in Table 1. CP etching was carried on in the solution consisted of HNO3: CH3COOH: CH3COOH = 6:3:1 for 4 min. All the wafers were cleaned by the standard RCA process to remove organic and metallic contaminants from the c-Si surface. The oxide removal in HF is performed before amorphous layer deposition by HWCVD. The deposition parameters are listed in Table 2. Atomic hydrogen treatment for the c-Si surface was done before depositing the films. The minority carrier lifetime was measured by a WT-2000 wafer scanner. The coverage and contact between the thin film and the substrate was studied by TEM, and the dark I-V characteristics of the heterojunction were obtained at 300 K. 3. Results We fabricated various textured morphologies obtained by NaClO and NaOH solutions, as shown by the scanning electron microscopy (SEM) micrographs in Fig. 1, from (a) small ones (1–3μm) to (b) large ones
(8–10 μm). After pyramid formation, CP was adopted to reduce the sharpness of pyramids. It results in a pyramid rounding, with small surface roughness, as presented in Fig. 1(c) and (d). With the CP time (tCP) increased from 0 to 4 min, the average angle of pyramid peak (φ) increased from 73.8° to 110.6° for the sample textured by NaClO, and φ increased from 73.7° to 101.8° for that one textured by NaOH. The passivation of the c-Si surface by intrinsic a-Si:H layers with the thickness of 50 nm deposited on both sides of c-Si is studied by minority carrier lifetime (τ) measurements. We present the results in Fig. 2 with error bars obtained based on possible error in measurements. Fig. 2 shows that the value of τ is smallest for the sample with large pyramids without CP, whereas the value of τ is largest for the sample with small pyramids and CP. The values of τ for the sample with small pyramids without CP and the sample with large pyramids with CP is almost the same. The cross-sectional TEM images of the a-Si:H layer with the thickness of about 20 nm deposited on the surface of c-Si textured by NaClO are shown in Fig. 3. It is seen that the a-Si:H layer covers the
Fig. 1. SEM photographs of c-Si with different sizes and shapes of pyramids, (a) large pyramids, (b) small pyramids, (c) large-CP, (d) small-CP.
G. Li et al. / Journal of Non-Crystalline Solids 358 (2012) 2223–2226
0.01
30
1E-3
25
1E-4
20
1E-5
I (A)
35
15
1E-6
10
1E-7
5
1E-8
2225
NaOH NaOH-CP NaClO NaClO-CP
1E-9
0 Large
Small
Large-CP
-1.0
Small-CP
-0.5
0.0
Fig. 2. Values of minority carrier lifetime for the different textured wafers passivated by the intrinsic a-Si:H layer with the thickness of 50 nm on both sides.
pyramid conformally, even at the peak of pyramid, and no epitaxial growth occurs at the a-Si:H/c-Si interface. The influences of pyramid's morphology on the interfacial properties of HIT cells are studied by the dark I-V characteristics, shown in Fig. 4. Here, the dark I-V curves are fitted by the double-diode equation as following: qðV−IRs Þ qðV−IRs Þ V−IRs I ¼ I 01 exp −1 þ I 02 exp −1 þ n1 kT n2 kT Rp
0.5
1.0
V (V)
samples
Fig. 4. Dark I–V curves for heterojunctions prepared on the Si wafers with different textured surfaces. Fit-lines are drawn with the experimental plots.
Table 3 The fitted parameters from the dark I–V curves (0.15 V b V b 0.3 V). Sample
n2
I02 (A)
Large Small Large + CP Small + CP
3.49 3.14 3.33 3.04
1.20 × 10− 6 2.65 × 10− 7 1.06 × 10− 7 9.71 × 10− 7
ð1Þ
Here, I01, I02 are the diffusion saturation current and generationrecombination saturation current, respectively, and n1, n2 are the diffusion diode factor and generation-recombination diode factor, respectively. q is the electron charge, k is Boltzmann's constant, T is the temperature, Rs is the series resistance and Rp is the shunt resistance. The first two terms of Eq. (1) describe the behavior of the diodes. The parameters, n1, n2, I01 and I02 are determined by transport and recombination mechanisms of the carriers. As demonstrated in this paper, our research is mainly focused on the interfacial property of the heterojunction, that's why the generation-recombination current in the depletion region closely related to it is fully studied. Therefore, it is only the parameters n2 and I02 that are fitted in our research, as listed in Table 3. It can be seen that the values of n2 for the samples with large pyramids are higher than those for the ones with small
pyramids, and CP treaments can reduce the values of n2 obviously. The value of n2 for the sample with small pyramids and CP is smallest among all the cases.
4. Discussion The phenomenon of pyramid rounding by CP treatment noticed in Fig. 1 can be well explained by mass-transfer etching theory [12]. As M. Kulkarni referred in his research [12], the mass-transfer resistance during etching is essentially related to the thickness of mass transfer; therefore, the mass-transfer resistance is lower at the peaks than that at the valleys. In this process, the pyramids are smoothed with CP treatment, which results in the reduction of surface roughness and the increase of φ. Moreover, small pyramids are helpful to improve
Fig. 3. The cross-sectional TEM photographs of a-Si:H layer deposited on the c-Si wafer with small pyramids. (a) with 100 nm scale, (b) with 10 nm scale.
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G. Li et al. / Journal of Non-Crystalline Solids 358 (2012) 2223–2226
the coverage of the film on c-Si. As shown in Fig. 3, the thin layer can cover the pyramid conformally. Fig. 2 shows that CP treatment can improve the minority carrier lifetime effectively. It is mainly owing to two reasons: for the first one, the surface is less rough after CP treatment that leads to the better coverage of the intrinsic amorphous layer on c-Si and the better passivation of c-Si; for the second one, CP etching can effectively reduce the content of metal ions on the surface of wafers [4,13]. CP treatment is a process with non-metal ions involved; furthermore, the less rough surface is beneficial to the removal of metal ions by RCA cleaning. That the sample with small pyramids and CP has the largest value of τ can be attributed to its low surface recombination rate resulted from the small surface roughness and the low content of metal ions on the surface of wafers. Consistently, the value of n2 becomes smaller after CP treatment, which also implied that the surface recombination rate decreases when the surface is less rough. Among all the samples, the value of n2 for the heterojunction prepared by the wafer with small pyramids and CP treatment is smallest and closest to the ideal value of 2 [14], indicated that the surface with the low roughness is beneficial to the performance of HIT solar cells. All the values of n2 are much higher than the ideal value may be related to the quality of heterojunction for which the prepared parameters are not optimal. 5. Conclusions There are four different surface morphologies of c-Si fabricated: large pyramids textured by NaOH, small ones textured by NaClO, large ones with CP treatment and small ones with CP treatment. The results of TEM indicate that the c-Si with small pyramids can improve the coverage and contact between the films and substrate. Furthermore, no epitaxial growth occurs at the a-Si:H/c-Si interface. The results, from the minority carrier lifetime and the dark I-V measurement, show that the wafers with small pyramids and CP treatment may achieve good surface
passivation and interfacial properties, with which the efficiency of HIT solar cells would be improved.
Acknowledgement This work was supported by the National Key Basic Research Program of China (No. 2011CBA00705).
References [1] S. Taira, Y. Yoshimine, T. Baba, M. Taguchi, H. Kanno, T. Kinoshita, H. Sakata, E. Maruyama, M. Tanaka, Proceedings of the 22nd EU PVSEC, Milan, 2007, p. 932. [2] Q. Wang, M.R. Page, E. Iwaniczko, et al., The 33rd IEEE Photovoltaic Specialists Conference, San Diego, California, 2008, p. 11. [3] http://sanyo.com/news/2009/05/22-1.html2009(5/22/09).“Tokyo, May 22, 2009SANYO Electric Co., Ltd. (SANYO) announced today that it has broken its own record for the world's highest energy conversion efficiency in practical size (100 cm2 or more) crystalline silicon-type solar cells, achieving an efficiency of 23.0% (until now 22.3%) at a research level for its proprietary HIT solar photovoltaic cells.” [4] Matthew Edwards, Stuart Bowden, Ujjwal Das, Michael Burrows, Sol. Energy Mater. Sol. Cells 92 (2008) 1373–1377. [5] H. Angermann, E. Conrad, L. Korte, J. Rappich, T.F. Schulze, M. Schmidt, Mater. Sci. Eng., B 159–160 (2009) 219–223. [6] D. Jeong, C. Kim, J. Song, J. Lee, J. Cho, S. Park, J. Wang, K. Yoon, J. Song, Photovoltaic Specialists Conference (PVSC), 34th IEEE, 2009, pp. 642–645. [7] S.R. Chitre, Proceedings of the 13th IEEE International Photovoltaic Specialists Conference, Washington D. C., 1978, pp. 152–154. [8] D.L. King, M.E. Buck, Proceedings of the 22nd IEEE Photovoltaic Specialists Conference, Las Vegas, 1991, p. 303. [9] Linfeng Sun, Jiuyao Tang, Appl. Surf. Sci. 255 (2009) 9301–9304. [10] U. Gangopadhyay, S.K. Dhungel, A.K. Mondal, H. Saha, J. Yi, Sol. Energy Mater. Sol. Cells 91 (2007) 1147–1151. [11] L. Fesquet, S. Olibet, J. Damon-Lacoste, S. De Wolf, A. Hessler-wyser, C. Monachorr, C. Ballif, Photovoltaic Specialists Conference (PVSC), Philadelphia, 2009, p. 000754. [12] M. Kulkarni, H. Erk, J. Electrochem. Soc. 147 (2000) 176. [13] Zhang Yu, Zhou Yuqin, Jiang Zhenyu, Liu Fengzhen, Zhu Meifang, Phys. Status Solidi C 7 (3-4) (2010) 1025–1028. [14] R. Hussein, D. Borchert, G. Grabosch, et al., Sol. Energy Mater. Sol. Cells 69 (2001) 123.
Contents lists available at SciVerse ScienceDirect
Journal of Non-Crystalline Solids journal homepage: www.elsevier.com/ locate/ jnoncrysol
Influence of textured c-Si surface morphology on the interfacial properties of heterojunction silicon solar cells Guorong Li, Yuqin Zhou ⁎, Fengzhen Liu Graduate University of the Chinese Academy of Sciences, Beijing 100049, PR China
a r t i c l e
i n f o
Article history: Received 30 September 2011 Received in revised form 29 November 2011 Available online 23 January 2012 Keywords: HIT solar cells; Textured surface; Interfacial property; Passivation; HWCVD
a b s t r a c t For the HIT solar cells, the properties of interface between intrinsic thin film and c-Si are critical for the resulting device. The interfacial properties mainly depend on the surface passivation quality of c-Si, which is found to be affected by the morphology of textured surfaces. In this study, four kinds of textured c-Si substrates are fabricated: large pyramids without chemical polished (CP), large pyramids with CP, small pyramids without CP and small pyramids with CP. We investigated the effects of textured-surface morphology on the passivation of c-Si, the thin layer coverage and the interfacial properties of heterojunction prepared by HWCVD. Minority carrier lifetime measurements show that the wafer with small pyramids leads to better surface passivation than the one with large pyramids. The good coverage and contact between the thin film and the substrate can be achieved and no epitaxial growth occurs on the wafer with small pyramids through the study of TEM. Dark I-V measurements reveal that the heterojunction on wafer with small pyramids and CP has low recombination at the a-Si:H/c-Si interface. Our results indicate that the surface with small pyramids and low surface roughness is beneficial to the performance of HIT solar cells. Crown Copyright © 2012 Published by Elsevier B.V. All rights reserved.
1. Introduction The heterojunction with intrinsic thin-layer (HIT) solar cells are of great interest for the photovoltaic development due to their highefficiency and low-cost fabrication process [1,2]. Up to now, Sanyo has achieved the world's highest conversion efficiency of 23% for solar cells fabricated by plasma enhanced chemical vapor deposition (PECVD) on an n-type Cz wafer [3]. For HIT solar cells, the interfacial properties between a-Si:H and c-Si make significant influence on the cell's efficiency. Such good passivation of the wafer surfaces becomes critical in making device voltage reach higher value [4]. The quality of surface passivation is mainly determined by the microstructure of a-Si:H layer, which not only depends on the deposited parameters and the deposited technology but also is related to the surface morphology of c-Si [5,6]. Generally, the Si wafers are textured randomly by chemical anisotropic etching with a NaOH or KOH solution, which is the standard process to obtain pyramids with the average size of 8-10μm[7,8]. As an alkaline and strong oxidizing reagent, NaClO can be used to obtain small and uniformed pyramids with the average size of 1–3μmon the Si wafer and to remove organic contaminants on the surface of wafer [9]. It is assumed that the wafer with small and uniformed pyramids owns advantages in HIT cell preparation, because the surface with small roughness is beneficial to improve the coverage and contact between the thin layers and substrate, which is helpful to increase the
⁎ Corresponding author. Tel./fax: + 861088256653. E-mail address: [email protected] (Y. Zhou).
open voltage and fill factor of solar cells [10]. However, the good passivation of Si wafer is regularly more cumbersome to be realized on the textured surface, and it is likely due to the presence of localized recombinative paths situated at the pyramid valleys [11]. Thus, in order to obtain the higher-efficiency cell on textured substrate, we have to avoid the appearance of the epitaxial growth and guarantee the good contact between the thin layers and substrate, also the perfectly performed passivation on textured surface is necessary. Here, we presented that this issue may be resolved by selecting silicon substrate morphology and fabricating the heterojunction by HWCVD. In this paper, we prepared the Si heterojunction by HWCVD and studied the effects of the textured-surface morphology on the thin layer coverage, the passivation of c-Si and the interfacial properties of heterojunction. Minority carrier lifetime has been measured after the H treatment and deposition of a-Si intrinsic layer in order to study the passivation effect. The microstructure of i-layer and the contact between i-layer and the substrate were studied through TEM. Dark I-V measurements were conducted to analyze the interfacial properties of heterojunction with the structure of Al/(n)a-Si:H/(i) a-Si:H/(p)c-Si/Al. 2. Experimental details The c-Si substrates (CZ, P-type, 1-10 Ω cm) with (100) surface orientation were used. First, to eliminate the native oxide on the surface, the wafer was treated in 2% HF solution for 60 s before the saw damage removing and texturation. The saw damage was removed in a 20 wt% NaOH solution at 80 °C for 10 min. Then the samples were
0022-3093/$ – see front matter. Crown Copyright © 2012 Published by Elsevier B.V. All rights reserved. doi:10.1016/j.jnoncrysol.2011.12.106
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G. Li et al. / Journal of Non-Crystalline Solids 358 (2012) 2223–2226
Table 1 Conditions for NaOH and NaClO texturizaiton. Sample
Solution
Concentration
Additives
Temperature and Time
CP
Large Large + CP Small Small + CP
NaOH NaOH NaClO NaClO
3 wt.% 3 wt.% Available Chlorine 9% Available Chlorine 9%
1wt%Na2SiO3 + 7vol%IPA 1wt%Na2SiO3 + 7vol%IPA 15 V%C2H5OH 15 V%C2H5OH
80 °C 80 °C 80 °C 80 °C
– HNO3 + CH3COOH + HF – HNO3 + CH3COOH + HF
50 min 50 min 80 min 80 min
Table 2 Deposition conditions for the thin films.
H treatment (i)a-Si:H (n)a-Si:H
Ts(°C)
Tf(°C)
H2(sccm)
SiH4(sccm)
PH5(sccm)
Pressure(Pa)
Time(s)
25 25 25
1850 1780 1780
20 3 3
– 1 1
– – 0.01
10 1 2
30 15 42
textured with the solution of NaClO and NaOH, respectively. The texturing parameters are listed in Table 1. CP etching was carried on in the solution consisted of HNO3: CH3COOH: CH3COOH = 6:3:1 for 4 min. All the wafers were cleaned by the standard RCA process to remove organic and metallic contaminants from the c-Si surface. The oxide removal in HF is performed before amorphous layer deposition by HWCVD. The deposition parameters are listed in Table 2. Atomic hydrogen treatment for the c-Si surface was done before depositing the films. The minority carrier lifetime was measured by a WT-2000 wafer scanner. The coverage and contact between the thin film and the substrate was studied by TEM, and the dark I-V characteristics of the heterojunction were obtained at 300 K. 3. Results We fabricated various textured morphologies obtained by NaClO and NaOH solutions, as shown by the scanning electron microscopy (SEM) micrographs in Fig. 1, from (a) small ones (1–3μm) to (b) large ones
(8–10 μm). After pyramid formation, CP was adopted to reduce the sharpness of pyramids. It results in a pyramid rounding, with small surface roughness, as presented in Fig. 1(c) and (d). With the CP time (tCP) increased from 0 to 4 min, the average angle of pyramid peak (φ) increased from 73.8° to 110.6° for the sample textured by NaClO, and φ increased from 73.7° to 101.8° for that one textured by NaOH. The passivation of the c-Si surface by intrinsic a-Si:H layers with the thickness of 50 nm deposited on both sides of c-Si is studied by minority carrier lifetime (τ) measurements. We present the results in Fig. 2 with error bars obtained based on possible error in measurements. Fig. 2 shows that the value of τ is smallest for the sample with large pyramids without CP, whereas the value of τ is largest for the sample with small pyramids and CP. The values of τ for the sample with small pyramids without CP and the sample with large pyramids with CP is almost the same. The cross-sectional TEM images of the a-Si:H layer with the thickness of about 20 nm deposited on the surface of c-Si textured by NaClO are shown in Fig. 3. It is seen that the a-Si:H layer covers the
Fig. 1. SEM photographs of c-Si with different sizes and shapes of pyramids, (a) large pyramids, (b) small pyramids, (c) large-CP, (d) small-CP.
G. Li et al. / Journal of Non-Crystalline Solids 358 (2012) 2223–2226
0.01
30
1E-3
25
1E-4
20
1E-5
I (A)
35
15
1E-6
10
1E-7
5
1E-8
2225
NaOH NaOH-CP NaClO NaClO-CP
1E-9
0 Large
Small
Large-CP
-1.0
Small-CP
-0.5
0.0
Fig. 2. Values of minority carrier lifetime for the different textured wafers passivated by the intrinsic a-Si:H layer with the thickness of 50 nm on both sides.
pyramid conformally, even at the peak of pyramid, and no epitaxial growth occurs at the a-Si:H/c-Si interface. The influences of pyramid's morphology on the interfacial properties of HIT cells are studied by the dark I-V characteristics, shown in Fig. 4. Here, the dark I-V curves are fitted by the double-diode equation as following: qðV−IRs Þ qðV−IRs Þ V−IRs I ¼ I 01 exp −1 þ I 02 exp −1 þ n1 kT n2 kT Rp
0.5
1.0
V (V)
samples
Fig. 4. Dark I–V curves for heterojunctions prepared on the Si wafers with different textured surfaces. Fit-lines are drawn with the experimental plots.
Table 3 The fitted parameters from the dark I–V curves (0.15 V b V b 0.3 V). Sample
n2
I02 (A)
Large Small Large + CP Small + CP
3.49 3.14 3.33 3.04
1.20 × 10− 6 2.65 × 10− 7 1.06 × 10− 7 9.71 × 10− 7
ð1Þ
Here, I01, I02 are the diffusion saturation current and generationrecombination saturation current, respectively, and n1, n2 are the diffusion diode factor and generation-recombination diode factor, respectively. q is the electron charge, k is Boltzmann's constant, T is the temperature, Rs is the series resistance and Rp is the shunt resistance. The first two terms of Eq. (1) describe the behavior of the diodes. The parameters, n1, n2, I01 and I02 are determined by transport and recombination mechanisms of the carriers. As demonstrated in this paper, our research is mainly focused on the interfacial property of the heterojunction, that's why the generation-recombination current in the depletion region closely related to it is fully studied. Therefore, it is only the parameters n2 and I02 that are fitted in our research, as listed in Table 3. It can be seen that the values of n2 for the samples with large pyramids are higher than those for the ones with small
pyramids, and CP treaments can reduce the values of n2 obviously. The value of n2 for the sample with small pyramids and CP is smallest among all the cases.
4. Discussion The phenomenon of pyramid rounding by CP treatment noticed in Fig. 1 can be well explained by mass-transfer etching theory [12]. As M. Kulkarni referred in his research [12], the mass-transfer resistance during etching is essentially related to the thickness of mass transfer; therefore, the mass-transfer resistance is lower at the peaks than that at the valleys. In this process, the pyramids are smoothed with CP treatment, which results in the reduction of surface roughness and the increase of φ. Moreover, small pyramids are helpful to improve
Fig. 3. The cross-sectional TEM photographs of a-Si:H layer deposited on the c-Si wafer with small pyramids. (a) with 100 nm scale, (b) with 10 nm scale.
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G. Li et al. / Journal of Non-Crystalline Solids 358 (2012) 2223–2226
the coverage of the film on c-Si. As shown in Fig. 3, the thin layer can cover the pyramid conformally. Fig. 2 shows that CP treatment can improve the minority carrier lifetime effectively. It is mainly owing to two reasons: for the first one, the surface is less rough after CP treatment that leads to the better coverage of the intrinsic amorphous layer on c-Si and the better passivation of c-Si; for the second one, CP etching can effectively reduce the content of metal ions on the surface of wafers [4,13]. CP treatment is a process with non-metal ions involved; furthermore, the less rough surface is beneficial to the removal of metal ions by RCA cleaning. That the sample with small pyramids and CP has the largest value of τ can be attributed to its low surface recombination rate resulted from the small surface roughness and the low content of metal ions on the surface of wafers. Consistently, the value of n2 becomes smaller after CP treatment, which also implied that the surface recombination rate decreases when the surface is less rough. Among all the samples, the value of n2 for the heterojunction prepared by the wafer with small pyramids and CP treatment is smallest and closest to the ideal value of 2 [14], indicated that the surface with the low roughness is beneficial to the performance of HIT solar cells. All the values of n2 are much higher than the ideal value may be related to the quality of heterojunction for which the prepared parameters are not optimal. 5. Conclusions There are four different surface morphologies of c-Si fabricated: large pyramids textured by NaOH, small ones textured by NaClO, large ones with CP treatment and small ones with CP treatment. The results of TEM indicate that the c-Si with small pyramids can improve the coverage and contact between the films and substrate. Furthermore, no epitaxial growth occurs at the a-Si:H/c-Si interface. The results, from the minority carrier lifetime and the dark I-V measurement, show that the wafers with small pyramids and CP treatment may achieve good surface
passivation and interfacial properties, with which the efficiency of HIT solar cells would be improved.
Acknowledgement This work was supported by the National Key Basic Research Program of China (No. 2011CBA00705).
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