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Influence of the silicon overlayer thickness of SOI unibond substrates on β-SIC heteroepitaxy
Materials Science and Engineering B61 – 62 (1999) 567 – 570
Influence of the silicon overlayer thickness of SOI unibond substrates on b-SIC heteroepitaxy H. Mo¨ller a,*, M. Eickhoff a, L. Vogelmeier a, M. Rapp a, G. Kro¨tz a, V. Papaioannou b, J. Stoemenos b a
Department FT2 /M, Daimler Benz AG, Postfach 800465, 81663 Mu¨nchen, Germany b Department of Physics, Aristotle Uni6ersity of Thessaloniki, Thessaloniki, Greece
Abstract The present paper describes the epitaxial growth of high quality 3C – SiC on the top of silicon on insulator (SOI) UNIBOND substrates, to achieve an electrical insulation. The process was performed at 1200°C using methylsilane as the precursor gas. The crystal quality was proved using X-ray analysis. The FWHM of the [200] rocking curve reflex was determined to 0.31° using a 200 nm thick SOL. A serial resistance of the SiO2 layer of 2.5·1012 V mm2 was obtained at RT which proofs the insulation to the substrate. A technique based on sacrificial oxidation was applied to thin the silicon overlayer (SOL). SOLs between 15 and 200 nm could be prepared. The influence on the structural properties of the SiC film was studied using X-ray, AFM and TEM measurements. It was found that structural properties are dependent on the deposition process and on the SOL thickness. High quality SiC can be grown on SOLs thicker than 50 nm. Possibilities for the growth of highest quality SiC even on much thinner SOLs are discussed. © 1999 Elsevier Science S.A. All rights reserved. Keywords: SiC on insulator; Unibond; Ultrathin silicon; Methylsilane; Cavity
1. Introduction
2. Preparation of SOI substrates
Cubic silicon carbide (3C-SiC) films exhibit extraordinary electronic and chemical properties [1]. In combination with micromachined silicon (Si) structures they yield the realisation of robust sensors operating at high temperatures and in chemically harsh environments [2]. For the application of SiC as piezoresistors, e.g. in high temperature pressure microsensors dielectric insulation to the substrate is necessary to eliminate the influence of the silicon and to avoid short circuits. To achieve this SiC was deposited on thin crystalline silicon overlayers (SOLs) on silicon dioxide (SiO2). The present paper describes a material preparation process for SOI for the variation of the SOL thickness between 15 and 200 nm and a low temperature growth process based on the precursor gas methylsilane. Structural and electrical properties of SiC grown on different thick SOLs were compared.
Commercial available standard UNIBOND silicon on insulator (SOI) substrates from SOITEC (S.O.I TEC, 1, Place Firmin Gautier, 38000 Grenoble cedex 9, France) were used for the experiments. The original SOLs of the SOI material system were 200 nm thick, [100] orientated and had a boron doped p-type resistivity of 15–22 V cm. The buried oxide layer (BOX) was 400 nm and the bulk silicon 500 mm thick. Different series of thinning experiments were performed to investigate the influence of silicon overlayer thicknesses on the quality of the subsequent deposited SiC films. The original 200 nm thick SOL was oxidised in a wet oxidation process at 1050°C in an Eurotherm tube furnace at atmospheric pressure. The thickness ratio of the SiO2 layer to the consumed Si is known to be 2.273:1 [3]. The oxide was removed by a subsequent wet etching process in a HF etchant mixture (Merck; silicon dioxide etchant, No. 1.07944) at room temperature. The thinned crystalline SOLs were very homogeneous, showed a mirror like surface and were smooth over the whole substrate. No defects could be observed using
* Corresponding author. Tel.: +49-89-60720657; fax: + 49-8960725157. E-mail address: [email protected] (H. Mo¨ller)
0921-5107/99/$ - see front matter © 1999 Elsevier Science S.A. All rights reserved. PII: S 0 9 2 1 - 5 1 0 7 ( 9 8 ) 0 0 4 7 5 - 9
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H. Mo¨ller et al. / Materials Science and Engineering B61–62 (1999) 567–570
Fig. 1. Polfigure of a SiC on SOI film in [111] and X-ray rocking curve of the [200] reflex.
cross-section TEM (XTEM) analysis. Ultrathin SOLs with minimal thickness down to 15 nm could be prepared using this sacrificial oxidation technique.
3. Growth process A low temperature growth process with methysilane (Epichem, Power Road, Bromborough, Wirral, Merseyside L62 3QF, UK) [4] was applied. The details are described elsewhere [5]. The native oxide was removed by a HF dip followed by a water rinsing step. No further cleaning step was applied and the substrate was inserted directly into the cold reactor chamber. To achieve high quality SiC on SOI layers the conventionally used hydrogen cleaning-step was left out whereas
fast heating and cooling ramps within the process were found to be substantial. The deposition process starts with a 30 s carbonisation step in an ethylene/argon gas mixture at 1220°C and 0.2 mbar. This results in a 7 nm thick crystalline buffer layer. The subsequent deposition took place at 1200°C and 0.5 mbar with a resulting growth rate of 4.6 mm h − 1. A dilution ratio of methysilane/hydrogen of 1/100 was applied.
4. Results Fig. 1a shows the 3D texture of a 2.3 mm thick SiC-film in the [111] direction, grown as described above. Four peaks in the [111] direction, which are evident for a cubic material were obtained. The absence
Fig. 2. Leakage current at 293 K.
H. Mo¨ller et al. / Materials Science and Engineering B61–62 (1999) 567–570
569
Fig. 3. Influence of the SOL thickness on structural properties of SiC.
of any further reflexes shows that there are no disorientations. The SiC films are single crystalline. The films appear mirror like and exhibit a RMS roughness of 50 nm, obtained by AFM. The quality of a crystalline film was derived by analysing the rocking curve, shown in Fig. 1b. The full widths half maximum (FWHM) of the [200] reflex is 0.31°, which is comparable to a standard material with similar thickness. Deposition series on thinned SOLs were performed. A good electrical insulation of the SiC to the bulk substrate was found at room temperature as shown in Fig. 2. The insulation is not significantly dependent on the SOL thickness and the average serial resistance from the SiC film to the bulk substrate is determined to be 2.5·1012 V mm2. At low electrical fields this value is comparable to SOI substrates without SiC deposition. Only at high voltages can deviations be measured.
Fig. 3 shows the FWHM of the [200] reflex and its dependence on the SOL thickness. Using a 200 nm thick SOL, a FWHM of 0.31° was obtained. This value is slightly higher than 0.28°, measured on SiC, grown on bulk Si [5]. Using a 100 nm thick SOL, a FWHM of 0.263° was obtained. This value is smaller than the FWHM of SiC on bulk Si. Decreasing the SOL thickness to 15 nm, the FWHM increases drastically to 0.51°. These results can be explained by two opposite effects. On the one hand the influence of the lattice mismatch decreases with decreasing SOL thickness. Therefore the FWHM decreases. On the other hand the stability of the SOL decreases with decreasing thickness. Fig. 4a shows the XTEM picture of SiC grown on SOI. The interface exhibits a large cavity, formed during the early stage of growth by out-diffusion of Si [6].
Fig. 4. XTEM (a) and PVTEM pictures of the SiC/Si interface grown on 200 nm (b) and 50 nm (c) SOL.
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H. Mo¨ller et al. / Materials Science and Engineering B61–62 (1999) 567–570
It does not penetrate the SiO2 and disturb the insulation. The density of the cavities can be estimated using lower magnification and plane-view TEM (PVTEM) at the interface (Fig. 4b and c). Due to thermal instabilities [7, this volume] the density of cavities at the interface increases from 6% using a 200 nm thick SOL (Fig. 4b) to 50% at the interface applying a 50 nm SOL (Fig. 4c). These opposite effects explain the existence of optimal conditions of the SOL thickness for SiC growth, which were found at a 100 nm thick SOL. The FWHM of this film was smaller than the one measured on SiC deposited on bulk Si under the same process conditions. By applying a process with a faster carbonisation step the quality of the SiC gown on thin SOL increases. The FWHM decreases from 0.49 to 0.41, as shown in Fig. 2. This proves the explanation described above and gives strong hints that with better adapted process conditions the optimum of the SOL thickness can be shifted to smaller values combined with decreasing FWHM and increasing crystal quality.
5. Conclusions High quality 3C-SiC was grown electrically insulated from the substrate using a low temperature process. A thinning procedure of the SOL was applied and subsequent deposition of SiC took place. An optimum of the SOL thickness was found and the possibility of further improvements was shown. Further improvement in the stability of the SOL will also help to deposit high quality SiC. Promising results on this topic are in progress by implanting nitrogen into the Si/SiO2 inter-
.
face [8, this volume]. Also, the development of a smarter deposition process, not affecting even ultrathin SOLs of SOI substrates, is in good progress at DaimlerBenz AG. The results of this paper combined with the other improvements mentioned appears to be a promising technique to produce a b-SiC grown on SOI exhibiting a quality capable not only for harsh environment sensors, but even for electronic devices.
Acknowledgements This work was supported by the Brite Euram Programme EU project SiCOIN (Contract No. BRPRCT96-0261). The authors gratefully acknowledge Dr H.W. Grueninger for the X-ray analysis.
References [1] J.A. Powell, L.G. Matus, Springer Proc. Phys. 34 (1989) 2–11. [2] G. Kro¨tz, C. Wagner, W. Legner, H. Sonntag, H. Mo¨ller, G. Mu¨ller, Inst. Phys. Conf. Ser. 142 (1996) 829 – 832. [3] S. Bu¨ttgenbach, Mikromechanik, Teubner, Stuttgard, 1994, p. 96. [4] I. Golecki, et al., Appl. Phys. Lett. 60 (1992) 1703. [5] H. Mo¨ller, M. Eickhoff, M. Rapp, G. Kro¨tz, Applied Physics A Springer, A68, (1999) 1 – 5. [6] G. Ferro, Y. Monteil, H. Vincent, et al., Thin solid Films 278 (1996) 33. [7] V. Papaioannou, H. Mo¨ller, M. Rapp et al., The evolution of cavities in Si at the 3C-SiC/Si interface during 3C SiC deposition by LPCVD, ESCRM ‘98, Montpellier, France, Mat. Sci. Eng. B61 – 62 (1999) 539 – 543. [8] S. Zappe, E. Obermeier, H. Mo¨ller, G. Kro¨tz, H. Wirth, W. Skorupa, Stabilization of the 3C-SiC/SOI system by an intermediate Si3N4 layer, ESCRM ‘98, Montpellier, France, Mat. Sci. Eng. B61 – 62 (1999) 522 – 525.
Influence of the silicon overlayer thickness of SOI unibond substrates on b-SIC heteroepitaxy H. Mo¨ller a,*, M. Eickhoff a, L. Vogelmeier a, M. Rapp a, G. Kro¨tz a, V. Papaioannou b, J. Stoemenos b a
Department FT2 /M, Daimler Benz AG, Postfach 800465, 81663 Mu¨nchen, Germany b Department of Physics, Aristotle Uni6ersity of Thessaloniki, Thessaloniki, Greece
Abstract The present paper describes the epitaxial growth of high quality 3C – SiC on the top of silicon on insulator (SOI) UNIBOND substrates, to achieve an electrical insulation. The process was performed at 1200°C using methylsilane as the precursor gas. The crystal quality was proved using X-ray analysis. The FWHM of the [200] rocking curve reflex was determined to 0.31° using a 200 nm thick SOL. A serial resistance of the SiO2 layer of 2.5·1012 V mm2 was obtained at RT which proofs the insulation to the substrate. A technique based on sacrificial oxidation was applied to thin the silicon overlayer (SOL). SOLs between 15 and 200 nm could be prepared. The influence on the structural properties of the SiC film was studied using X-ray, AFM and TEM measurements. It was found that structural properties are dependent on the deposition process and on the SOL thickness. High quality SiC can be grown on SOLs thicker than 50 nm. Possibilities for the growth of highest quality SiC even on much thinner SOLs are discussed. © 1999 Elsevier Science S.A. All rights reserved. Keywords: SiC on insulator; Unibond; Ultrathin silicon; Methylsilane; Cavity
1. Introduction
2. Preparation of SOI substrates
Cubic silicon carbide (3C-SiC) films exhibit extraordinary electronic and chemical properties [1]. In combination with micromachined silicon (Si) structures they yield the realisation of robust sensors operating at high temperatures and in chemically harsh environments [2]. For the application of SiC as piezoresistors, e.g. in high temperature pressure microsensors dielectric insulation to the substrate is necessary to eliminate the influence of the silicon and to avoid short circuits. To achieve this SiC was deposited on thin crystalline silicon overlayers (SOLs) on silicon dioxide (SiO2). The present paper describes a material preparation process for SOI for the variation of the SOL thickness between 15 and 200 nm and a low temperature growth process based on the precursor gas methylsilane. Structural and electrical properties of SiC grown on different thick SOLs were compared.
Commercial available standard UNIBOND silicon on insulator (SOI) substrates from SOITEC (S.O.I TEC, 1, Place Firmin Gautier, 38000 Grenoble cedex 9, France) were used for the experiments. The original SOLs of the SOI material system were 200 nm thick, [100] orientated and had a boron doped p-type resistivity of 15–22 V cm. The buried oxide layer (BOX) was 400 nm and the bulk silicon 500 mm thick. Different series of thinning experiments were performed to investigate the influence of silicon overlayer thicknesses on the quality of the subsequent deposited SiC films. The original 200 nm thick SOL was oxidised in a wet oxidation process at 1050°C in an Eurotherm tube furnace at atmospheric pressure. The thickness ratio of the SiO2 layer to the consumed Si is known to be 2.273:1 [3]. The oxide was removed by a subsequent wet etching process in a HF etchant mixture (Merck; silicon dioxide etchant, No. 1.07944) at room temperature. The thinned crystalline SOLs were very homogeneous, showed a mirror like surface and were smooth over the whole substrate. No defects could be observed using
* Corresponding author. Tel.: +49-89-60720657; fax: + 49-8960725157. E-mail address: [email protected] (H. Mo¨ller)
0921-5107/99/$ - see front matter © 1999 Elsevier Science S.A. All rights reserved. PII: S 0 9 2 1 - 5 1 0 7 ( 9 8 ) 0 0 4 7 5 - 9
568
H. Mo¨ller et al. / Materials Science and Engineering B61–62 (1999) 567–570
Fig. 1. Polfigure of a SiC on SOI film in [111] and X-ray rocking curve of the [200] reflex.
cross-section TEM (XTEM) analysis. Ultrathin SOLs with minimal thickness down to 15 nm could be prepared using this sacrificial oxidation technique.
3. Growth process A low temperature growth process with methysilane (Epichem, Power Road, Bromborough, Wirral, Merseyside L62 3QF, UK) [4] was applied. The details are described elsewhere [5]. The native oxide was removed by a HF dip followed by a water rinsing step. No further cleaning step was applied and the substrate was inserted directly into the cold reactor chamber. To achieve high quality SiC on SOI layers the conventionally used hydrogen cleaning-step was left out whereas
fast heating and cooling ramps within the process were found to be substantial. The deposition process starts with a 30 s carbonisation step in an ethylene/argon gas mixture at 1220°C and 0.2 mbar. This results in a 7 nm thick crystalline buffer layer. The subsequent deposition took place at 1200°C and 0.5 mbar with a resulting growth rate of 4.6 mm h − 1. A dilution ratio of methysilane/hydrogen of 1/100 was applied.
4. Results Fig. 1a shows the 3D texture of a 2.3 mm thick SiC-film in the [111] direction, grown as described above. Four peaks in the [111] direction, which are evident for a cubic material were obtained. The absence
Fig. 2. Leakage current at 293 K.
H. Mo¨ller et al. / Materials Science and Engineering B61–62 (1999) 567–570
569
Fig. 3. Influence of the SOL thickness on structural properties of SiC.
of any further reflexes shows that there are no disorientations. The SiC films are single crystalline. The films appear mirror like and exhibit a RMS roughness of 50 nm, obtained by AFM. The quality of a crystalline film was derived by analysing the rocking curve, shown in Fig. 1b. The full widths half maximum (FWHM) of the [200] reflex is 0.31°, which is comparable to a standard material with similar thickness. Deposition series on thinned SOLs were performed. A good electrical insulation of the SiC to the bulk substrate was found at room temperature as shown in Fig. 2. The insulation is not significantly dependent on the SOL thickness and the average serial resistance from the SiC film to the bulk substrate is determined to be 2.5·1012 V mm2. At low electrical fields this value is comparable to SOI substrates without SiC deposition. Only at high voltages can deviations be measured.
Fig. 3 shows the FWHM of the [200] reflex and its dependence on the SOL thickness. Using a 200 nm thick SOL, a FWHM of 0.31° was obtained. This value is slightly higher than 0.28°, measured on SiC, grown on bulk Si [5]. Using a 100 nm thick SOL, a FWHM of 0.263° was obtained. This value is smaller than the FWHM of SiC on bulk Si. Decreasing the SOL thickness to 15 nm, the FWHM increases drastically to 0.51°. These results can be explained by two opposite effects. On the one hand the influence of the lattice mismatch decreases with decreasing SOL thickness. Therefore the FWHM decreases. On the other hand the stability of the SOL decreases with decreasing thickness. Fig. 4a shows the XTEM picture of SiC grown on SOI. The interface exhibits a large cavity, formed during the early stage of growth by out-diffusion of Si [6].
Fig. 4. XTEM (a) and PVTEM pictures of the SiC/Si interface grown on 200 nm (b) and 50 nm (c) SOL.
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H. Mo¨ller et al. / Materials Science and Engineering B61–62 (1999) 567–570
It does not penetrate the SiO2 and disturb the insulation. The density of the cavities can be estimated using lower magnification and plane-view TEM (PVTEM) at the interface (Fig. 4b and c). Due to thermal instabilities [7, this volume] the density of cavities at the interface increases from 6% using a 200 nm thick SOL (Fig. 4b) to 50% at the interface applying a 50 nm SOL (Fig. 4c). These opposite effects explain the existence of optimal conditions of the SOL thickness for SiC growth, which were found at a 100 nm thick SOL. The FWHM of this film was smaller than the one measured on SiC deposited on bulk Si under the same process conditions. By applying a process with a faster carbonisation step the quality of the SiC gown on thin SOL increases. The FWHM decreases from 0.49 to 0.41, as shown in Fig. 2. This proves the explanation described above and gives strong hints that with better adapted process conditions the optimum of the SOL thickness can be shifted to smaller values combined with decreasing FWHM and increasing crystal quality.
5. Conclusions High quality 3C-SiC was grown electrically insulated from the substrate using a low temperature process. A thinning procedure of the SOL was applied and subsequent deposition of SiC took place. An optimum of the SOL thickness was found and the possibility of further improvements was shown. Further improvement in the stability of the SOL will also help to deposit high quality SiC. Promising results on this topic are in progress by implanting nitrogen into the Si/SiO2 inter-
.
face [8, this volume]. Also, the development of a smarter deposition process, not affecting even ultrathin SOLs of SOI substrates, is in good progress at DaimlerBenz AG. The results of this paper combined with the other improvements mentioned appears to be a promising technique to produce a b-SiC grown on SOI exhibiting a quality capable not only for harsh environment sensors, but even for electronic devices.
Acknowledgements This work was supported by the Brite Euram Programme EU project SiCOIN (Contract No. BRPRCT96-0261). The authors gratefully acknowledge Dr H.W. Grueninger for the X-ray analysis.
References [1] J.A. Powell, L.G. Matus, Springer Proc. Phys. 34 (1989) 2–11. [2] G. Kro¨tz, C. Wagner, W. Legner, H. Sonntag, H. Mo¨ller, G. Mu¨ller, Inst. Phys. Conf. Ser. 142 (1996) 829 – 832. [3] S. Bu¨ttgenbach, Mikromechanik, Teubner, Stuttgard, 1994, p. 96. [4] I. Golecki, et al., Appl. Phys. Lett. 60 (1992) 1703. [5] H. Mo¨ller, M. Eickhoff, M. Rapp, G. Kro¨tz, Applied Physics A Springer, A68, (1999) 1 – 5. [6] G. Ferro, Y. Monteil, H. Vincent, et al., Thin solid Films 278 (1996) 33. [7] V. Papaioannou, H. Mo¨ller, M. Rapp et al., The evolution of cavities in Si at the 3C-SiC/Si interface during 3C SiC deposition by LPCVD, ESCRM ‘98, Montpellier, France, Mat. Sci. Eng. B61 – 62 (1999) 539 – 543. [8] S. Zappe, E. Obermeier, H. Mo¨ller, G. Kro¨tz, H. Wirth, W. Skorupa, Stabilization of the 3C-SiC/SOI system by an intermediate Si3N4 layer, ESCRM ‘98, Montpellier, France, Mat. Sci. Eng. B61 – 62 (1999) 522 – 525.