Instability phenomena in thin insulating films on silicon

Microelectronics and Reliability, Vol. 15, pp. 385 to 398. Pergamon Press, 1976. Printed in Great Britain

REVIEW PAPER INSTABILITY PHENOMENA IN THIN INSULATING FILMS ON SILICON B. R. SINGH* Advanced Centre for Electronic Systems, Indian Institute of Technology, Kanpur, (U.P.) India and KESHAW SINGH Physics Department, Banaras Hindu University, Varanasi, (U.P.) India Abstract--This paper reviews the various charge instability mechanisms associated with different insulating films on silicon which are of great importance in semiconductor device technology. The mechanisms discussed are ionic drift, dipolar polarization, slow electronic trapping and double dielectric layer effects. The parameters affecting these phenomena and the current state-of-the-art in controlling them is also discussed. 1. I N T R O D U C T I O N

Thin insulating films are of great importance in semiconductor device technology. These films are used as an integral part of MOS devices, as diffusion masks and also to passivate the semiconductor surfaces. Over the past 15 years, extensive studies have been performed to characterize and control the various instability mechanisms using single and double layer dielectrics over silicon. This has resulted in the commercial reality of the MOS devices. Metal-oxidesemiconductor voltage-dependent capacitor structures have been mostly employed for the study and are thus directly related to the reliability of the insulated gate and indirectly to the reliability of other types of semiconductor devices. In early days, two major problems, high surface state density and instability due to alkali ions, frustrated the fabrication of successful MOS devices [1]. A high density of interface states will result in a low effective mobility of carriers in the channel, a high turn-on voltage, large flicker noise, and instability of these parameters under operational stresses such as high electric fields and elevated temperatures. Alkali ion contamination of the oxide will result in high turn-on voltages and instability of device parameters under operational stresses due to mobile ion transport through the oxide. These phenomena are more pronounced in thermally grown SiO 2 films. Other than these two, a few more phenomena e.g. electronic trapping, dipolar polarization, etc., are responsible for instabilities in deposited insulating films like silicon nitride, phosphosilicate glass, lead silicate glass and tantalum oxide. These films are equally important and are also used as an integral part of IGFET and for passivation of semiconductor devices. * Present Address; Humoldt Fellow, Institut for Halbleitertechnik der RWTH Aachen, 51 Aachen, West Germany. 385

The main aim of this paper is to review the extensive work reported in the literature on different types of polarization phenomena associated with thin insulating films on silicon. This also includes the current state-of-the-art involved in control of these phenomena.

2. MIS CHARACTERISTICS

AS mentioned previously, in most of the studies the C-V characteristics of the MOS capacitor have been

employed because of its greater sensitivity and ease of fabrication. The discussion will be limited to instabilities which can occur when an electric field is applied to the passivation dielectric at room temperature or moderately elevated temperature. In practice the measured C-V characteristics always show a shift along the voltage axis compared with that of the ideal one. The ideal C- V characteristics can be calculated taking all the parameters of the device. The observed shift originates as a result of two potentials, viz. (1) the work function difference between metal and the semiconductor and (2) a fixed oxide charge [2]. The fiat band voltage shift AVvB is required to balance the already existing field in the semiconductor. The build up and the decay of the charge causes the change in built-in field and hence the shift in the C-V characteristics. The C- V characteristics yields the information regarding the different nature of polarization phenomena via magnitude of its shift, shape and direction. The magnitude of the shift AVFB can be determined by the relation AVr~ = A [ - ~ /1f f ° x , ( x )

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3. POLARIZATION PHENOMENON AND ITS EFFECT ON MIS CHARACTERISTICS

The major instability mechanisms observed in dif, ferent insulating films are illustrated in Fig. 1. The shift in the C-V characteristics with the positive polarizing voltage is also shown. In the case of ionic migration the mobile cations migrate through the insulating layer and accumulate at the insulator-semiconductor interface resulting in a negative shift in C-V characteristic, (Fig. l(a)). Figure l(b) represents the case of dipolar polarization. The dipoles are spatially distributed in the insulator and preferentially orient themselves with the field resulting in the shift along voltage axis. Analogous to the ion migration, the direction of the C V shift and the polarity of polarizing bias have the opposite signs. Figure l(c) represents the trapping of charges in the insulator injected from the semiconductor. In this case, the C V shift has the same sign as the polarizing bias. In the case of double layer dielectrics, the charge accumulates at the interface of these insulators due to the difference in current density. The sign of the charge and the shift in C-V characteristics can be either one of the two depending on the relative conductivities and is shown in Fig. l(d). Each of these mechanisms associated with different insulating films will be discussed in some detail. The reader is also referred to published reviews of instability mechanisms [3-8].

4. IONIC DRIFT

The results obtained on ionic drift can be divided into two groups: the distributed and the surface contaminants. In the former, the cations are distributed throughout the insulator and are initially compensated by the immobile anions. With the heat-biasing stress the ions become accumulated on one of the interfaces, resulting in a positive or negative space

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Fig. 2. Insulator space-charge distributions after biastemperature stressing of MIS structures with distributed and surface contaminant cations. Distributions are shown after either positive or negative bias is applied to the metal electrode.

charge depending upon the polarity of the applied field. The image charge induced in silicon will be opposite in nature. In the latter case, i.e. in the surface contaminants, the ions are generally located in the ion traps at the metal insulator interface. This is observed in thermally grown silicon dioxide layer. With positive bias the cations will move through the insulating film and accumulate at the Si-SiO2 interface resulting in a negative image charge induced in the silicon. This will give rise to a large shift in the G-V characteristic along the positive axis. The charge distribution for both the above cases is illustrated in Fig. 2. 4.1 Thermally grown silicon dioxide films A thermally grown silicondioxide layer is always found to have a positive charge associated with it. Positive charge is supposed to be caused by at least four types of centres. These are: fast surface states, fixed oxide charge, traps and mobile charges in the SiO/layer. Here, the review is limited to the instability phenomenon due to mobile charges. The instability phenomenon in SiO 2 film was first observed by Kerr et al. [9] using an MIS capacitor. The results are illustrated in Fig. 3. They observed quite stable devices with negative bias stress, but a large shift in the negative direction was observed with I

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387

ported by several workers employing radiotracer and neutron activation techniques. Yon et a/.[15] reported the Na ions profile on a clean oxide before and after heat-biasing stress. This is illustrated in Fig. 5. It is apparent from this figure that the Na ions are initially located at the metal-oxide interface and they pile up at the oxide-silicon interface after heatbiasing stress. This observation is strikingly similar to the results of C-V analysis. This also indicated the presence of immobile sodium in the SiO2 film, To verify whether the inactive Na exists in the bulk of the oxide or not, Logan and Kerr 1-16] deposited a controlled amount of sodium, lithium and potassium onto a clean SiO2 surface. It was observed that all the evaporated ions were mobile and that the Na and Li have almost the same migration rate while K ions are about 103 times less mobile than the other two at all temperatures. This was attributed to larger ionic radius of K (1.33 •) as compared to Na (1.00 ~,) and Li (0.70/~), The instability phenomena have also been studied by treating thermally grown oxides with different solvents. Gregor [17] reported the different degree of instabilities in various solvents. The general effect observed was that the more basic the solvent, the more adverse effect it has on MOS instability. Yurash and Deal [18] employed the flame-spectroscopic technique and suggested that the more active solvent might contain more sodium and thus would lead to increased contamination of the oxides. A detailed study of ionic instability in thermally grown silicon dioxide layers was made by Hof-

positive bias even at low temperature (100°C). This indicates that the observed instability is due to migration of positive charges from the metal-oxide side to the Si-SiO 2 interface. In a model proposed by Thomas and Young [10] this observed instability was attributed to the oxygen vacancies created by the reaction of gate metal (aluminium) with the SiO2 layer. Grove et al. [2] fabricated stable devices using aluminium as a gate metal without PSG as the stabilizing layer and questioned the validity of this model. The observed instability by Kerr et al. [91 using the unreactive metal (platinum), also contradicts the above model. Snow et al. [11] suggested that the observed instability arises not because of oxygen vacancies but is I I I I i due to some external contamination which they correlated with the Na ion migration. To verify, one oxidized wafer was intentionally contaminated in dilute solution of NaC1 before metallization, whereas the control wafer was without any contamination. iO~ The first one showed an enhancement of instability, f UNDRIFTED i.e. large shift in C-V characteristic with the positive bias applied at elevated temperature, whereas the second one showed only a diminished instability. The excess charge induced in the silicon by the redistribution of ionic charge was found to be dependent on i\ E=5"'°5 v'cm \ / I temperature, applied bias and time. For a particular \ ~ T ~ i'0.0: O 0 / , 7 l bias and temperature the induced surface charge, Qs __ 017 increases initially with time and finally saturates. The higher the temperature, the more rapidly Qs saturates. But the saturated value always remains the same \k ~ / I / because saturation occurs when all the available ionic charges have drifted to the Si-SiO2 interface. A drifted device could be depolarized with negative bias or by short circuiting the electrodes at elevated temperatures. Snow et al. [11] observed the symI I I I I i016 metric type of recovery in their devices. Contrary to I 2 3 4 5 this, Kerr[12], Hofstein[13] and Singh et al. [14] DISTANCE FROM AIR INTERFACE CIO00A% observed fast recovery i.e. recovery the time was too Fig. 5. Sodium profiles as determined by neutron actishort in comparison to initial drift time. vation analysis of unintentionally contaminated MOS The observations of Snow et al. [11] about Na ions devices undrifted and after drifting under positive bias at responsible for observed instability were later on sup200°C (Ref. [15]).

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discharge at the surface are shown in Fig. 8. The charge induced at the Si-SiO2 interface can also be completely removed by charging the surface with negative corona followed by washing in water. Recently, there has been considerable interest in studying whether the contamination level, i.e. the ion population, affects the ion migration kinetics or not. Kuhn and Silversmith [24] simply suspected that the ion population may affect the ion migration kinetics. No explanation has been given for this dependence. Recently, Kriegler and Bartnikas [25], while studying dielectric relaxation phenomenon in Cr SiO2 Si structures at different contamination levels, could not observe any change with sodium contamination. Very recently, Singh et al. [26, 27] observed this effect by intentionally contaminating the oxidised devices in a humidity chamber at different temperatures. A distinct spread in initial drift waveform and hence in activation energy has been observed and is shown in Fig. 9. No significant change in recovery waveform has been observed. 4.1.1. Technology f o r producing sodium-Jkee SiO~ film. Before describing the methods employed to grow uncontaminated oxides, it is desirable to discuss the sources of contamination. The sources of alkali ion contamination (sodium) are the gate metallization, the oxidation furnace, the chemical reagents, gases and general handling of the samples. The major source of contamination is aluminium evaporation with the tungsten filament. At evaporation temperature, the tungsten and aluminium alloy form a liquid phase and the sodium in the tungsten diffuses rapidly through the liquid alloy and is deposited on the oxide along with aluminium. Initially, this problem was solved by evaporating aluminium with electron-beam heating. An additional problem of increased oxide charge was observed due to exposure with X-rays coming out from the target during evaporation. The

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wafer had to be annealed to remove this oxide charge. Both these problems have been successfully solved by using sodium-free tungsten filaments which are now commercially available. The various chemicals used for cleaning and etching purposes are also a source of sodium contamination. Of all the chemicals used, only the last one should be sodium-free. Therefore, a final rinse in high resistivity deionized water is recommended. The next source for sodium contamination is the oxidation furnace. The insulating materials used for manufacture of the furnaces have a high degree of sodium contamination. A practical solution to the problem is use of SiC liner as a sodium barrier [28],

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and high purity optical grade quartz or the commercial grade transparent quartz. The use of R.F. furnaces will also reduce the sodium content. A well established technique to overcome this problem is to grow a thin layer of phosphosilicate glass over the oxidised surface of silicon. The PSG layer acts as a getter and a barrier to the movement of sodium [9]. Another instability mechanism e.g. dipolar polarization has been reported in the litera. ture [29] ; however, by choosing proper growth conditions, thickness and P2Os content, the improved stability against sodium ion migration can be achieved [30]. A very recent technique to grow sodium-free SiO2 film is the addition of (1-5%) C12 or HC1 in 02 during high temperature thermal oxidation of silicon [31, 32]. This HCl-oxide has shown better electrical stability even after intentional contamination with sodium ions. This improved stability is attributed to the mechanism of trapping and neutralisation of positively charged ions as a result of their interaction with chlorine near the Si-SiO2 interface and subsequent transfer of positive charge to the silicon electrode. Moreover, the use of HC1 as gettering agent has resulted in improved minority carrier lifetime and interface state density [31, 34, 35]. 4.2

ReactivelysputteredSi02films

Vacuum techniques, such as EB evaporation and reactive sputtering, are now well established for depositing insulator films. The ionic instability phenomena in two types of d.c. reactively sputtered films are reviewed here [36]. Films of type I were sputtered directly over Si at sputtering voltage greater than

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1200 V and low pressure and type II with voltages below 1200 V and at high pressure. The film of type I was found to have a high positive insulator charge density while that of type II showed large density of negative charges. This behaviour has been attributed to the influence of ionic species present in the plasma above the work piece during deposition [36]. The ionic behaviour is also different in these films. The type I film had the ionic behaviour similar to thermally grown SiO2 film, i.e. a large negative fiatband voltage was observed under positive bias as shown in Fig. 10 for isochronal stress. In contrast, type II films had the behaviour similar to clean, thermally grown SiO2. In this case the positive bias produced little effect (Fig. 11) while negative stress caused injection trapping at the oxide-silicon interface. This difference in the behaviour of the two films has not been well understood. It is suggested that this is probably due to the structural differences.

Under negative bias, however, they drifted towards the metal-glass interface, leaving behind a negative space charge thus making VvR positive. Kerr [37] attributed the observed polarization to the migration of Na ions. The shift in the flat band voltage vs temperature with an applied bias of 10V is shown in Fig. 12, for various glass compositions. Similar studies in silicate glasses have also been made by Snow and Dumesnil [39] employing double layered structure. In this structure a thin SiO2 layer over silicon was grown to avoid the direct interaction

4.3 Deposited glass The high temperature glasses are being extensively employed in semiconductor technology. They are used for multilayer connections in integrated circuits, in the passivation of transistors and diodes, as a major parts of thick-film pastes and in protection, mainly because of their relative effectiveness against device degradation due to ionizing radiation. The other interesting point which merits their review here is their peculiar instability behaviour. Kerr [37] studied a wide composition of different glasses e.g. lead aluminoborosilicate and zincborosilicate glasses. He employed the sedimentation technique for the fabrication of glass film over the silicon substrates [38]. Large shifts in Vva with both the bias polarities were observed at an elevated temperature. It is believed that the ions are uniformly distributed throughout the glass film. Under positive bias, cations drifted towards the glass-silicon interface resulting in a positive space charge which gave rise to a negative value of VFB.

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5.1 Phosphosilicate glass The instability observed due to ion migration in thermally grown SiO2 layers was improved by a second insulating layer known as a phosphosilicate glass (PSG) film. This layer is frequently formed during the processing of transistors and integrated circuits at the time of phosphorous diffusion. As pointed out earlier, such layers act as barriers to Na ions and thus tend to stabilize bipolar and MOS devices against gross instabilities due to sodium migration. Kerr [9] studied the stability behaviour of n - p - n transistors and MOS capacitors with and without PSG layer. He observed the improved performance of bipolar and MOS devices having a PSG layer next to the heat-biasing stress. The gettering action of PSG layer for Na migration was also reported by Yon et al. 1-15]. A comparison of Na ion concentration with and without the PSG layer is shown in Fig. 16. It is apparent from this figure that the concentration of Na ions is considerably lowered with PSG over SiO2 layer. Buck et al. [41] and Carlson et al. [42] have also determined sodium distributions from neutron activation analysis and radiotracer studies and their results generally agree with those of Yon et al. [15]. Snow and Deal [29] have also concluded the improved performance of devices with PSG layer but io2c ~_ \

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Fig. 16. The effect of a phosphosilicate glass layer deposited at 950°C in gettering the sodium from a heavily contaminated silicon dioxide film (Ref. [15]).

- Z a Vp K o [ l + ( K . + 7.a)xo/Koxo]'

(4)

where K o, Ko, xo and Xo are the dielectric constants and thicknesses of glass and oxide layers, respectively. Their observed results with the film containing about 16 mole per cent P/O5 fits very well with the theoretical prediction if Xd = 0.75. It is clear from eq. (4) that the dipolar polarization could be reduced to a tolerable limit using a small value for xg/x o. An alternative for the same is to reduce the polarizability Zd. Eldridge et al. [30] examined the PSG films of wide composition range and studied the dependence of Zd on mole fraction of P205. They reported that the polarizability ~ was proportional to the square of PzO5 content as shown in Fig. 19. They attributed the observed instability

Thin Insulating Films on Silicon 0.18 I

393 V EPias [Volts)

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Fig. 18. Dependence of the saturation shift of the C-V curve per unit applied voltage V~a,/Vpon the phosphosilicate glass to silicon dioxide thickness ratio x~/xo. Each point corresponds to a different sample (Ref. [29]). to the migration of nonbridging oxygen ion between adjacent phosphorous atoms. It was suggested that the reduction of xg/xo and use of low mole percentage P205 glass could reduce dipolar polarization to tolerable limits. The possible nature of field-induced drifting in the intentionally contaminated PSG film with sodium ions was also reported by Eldridge and Kerr [43]. PSG films of different compositions were used. The results indicate that a relatively thin ( ~ 4 mole per cent P205) film of PSG will effectively stabilize the device under typical operating conditions of temperature and field against the significant Na concentration. Raising the P205 concentration to 6 or 8 mole per cent gives additional increase in both z and the activation energy. With reference to the effect of N P 2 0 s on the polarization phenomenon Yeow et al. [44] and Singh and Srivastava [45] studied the effect of PSG deposition condition on surface state charge at Si-SiO2 interface and polarization phenomena. It is concluded that these phenomena are mainly related to growth conditions and can be controlled by choosing the ambient gas and temperature. Yeow et al. [44] suggested that the better stability could be observed by growing the 12 I I

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I

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15

20

25

30

35

40

45

50

N2P205xlO3 Fig. 19. Linear dependence of low-temperature PSG polarizability on the square of the mole fraction of P205 in the glass (Ref. [30]).

1

T =3OOO c

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Fig. 20. Dependence of negative-bias instability in thermal SiO2 on field, oxidation process, and silicon orientation (Ref. [48]). PSG layer over the SiO2 layer in pure nitrogen ambient. 6. ELECTRONIC TRAPPING

6.1 Silicon dioxide Another source of instability observed in some of the insulating layers was due to trapping of charge carriers. The process involves the charge exchange between the silicon surface and the trapping sites located in the insulating layer. This exchange can produce an algebraic decrease in the insulator charge near the Si-SiO2 interface with positive bias to metal electrode and a charge increase with negative bias. Heiman and Warfield[46] considered the various aspects of charge exchange on C - V characteristics in MIS devices. Saminadayer et al.[47] have also observed the effect at room temperature in dry oxides on Si substrates which were previously annealed in vacuum at 850°C. These authors proposed that charge trapping occurs by tunneling between the silicon and spatially shallow oxide traps directly. Instability of a different nature has been observed by several workers [48-51] in which the C - V characteristics shift in the same direction as the polarity of the bias at elevated temperature stress. The characteristics showed a greater shift with negative applied voltage than that with positive voltage and required a fairly high temperature (300°C-400°C) for rapid shift. Some additional features of this instability in steam-grown, low temperature hydrogen annealed on (111) silicon has been observed by Hofstein [48] and is shown in Fig. 20. It is clear from this figure that the C - V shift is proportional to the field applied at 300°C and is strongly dependent on the orientation of the silicon. Based on his observations Hofstein [48] discussed all likely possibilities and proposed a semiqualitative model as shown in Fig. 21. He attributed

394

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the drift to the trapping of holes by a level of donorlike states. These states lie in close proximity to the Si-SiO2 interface and can communicate with the silicon by a mechanism similar to trap hopping, i.e. the potential well of the trap extends into the silicon so that a hole need not be excited into the oxide valence band to be captured. Under applied negative bias, holes are thermally excited over the trap barrier and are trapped. The activation energy for this trapping is approximately 1.0 eV. Since these trapping levels are very close to the Fermi level, the number of holes trapped, and hence the flat band shift, will depend upon surface concentration and therefore on the applied bias. To control this trapping instability, Hofstein suggested that high temperature dry hydrogen annealing should effectively eliminate the instability both for (100) and (11 l) orientation of the silicon. Deal et al. [-49] attributed this instability to the excess ionic silicon centres injected from the substrate. 6.2. Silicon nitride As an alternative to SiO2, silicon nitride received much attention as a passivation layer in which ionic instability is almost absent at elevated temperature [52, 53]. But other electrical instability mechanisms Original

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Fig. 23. Hystersis effect on the flat-band voltage shift of metal nitride-silicon capacitors subjected to symmetric cycles of metal to silicon polarizing voltage (Ref. [52]). are more evident. A room temperature charge exchange i.e. trapping of carriers in silicon nitride film injected from silicon has been observed in MetalNitride-Silicon (M-N-S) structures [54-56]. If the trapping is associated with the semiconductor-insulator interface the nature of the shift in C - V characteristics will be as shown in F.ig. 22. Trapping begins at +40 or - 3 0 V for a nitride thickness of 2000A. It has been concluded that a minimum field (1.5 × 106 V/cm in the present case) is necessary before the onset of charge trapping occurs. The amount of trapped charge increases linearly with the applied field above the threshhold, as is evident from the displacement of the C - V characteristics. Because of the shift in flat band voltage towards positive direction with the applied positive bias and its weak temperature dependence, this instability is indeed due to the tunneling of carriers in and out of traps near the insulator-semiconductor interface and is not caused by any other polarization phenomena e.g. ionic or dipolar. Some experimental results were also interpreted in terms of injection of carriers from the metal electrode [57]. The behaviour of flat band voltage shift with the applied field in M - N - S structures is shown in Fig. 23. It is apparent from the figure that with the change in polarity of applied field from negative to positive and back, a hysterisis loop is observed. The size of the loop depends upon the maximum bias voltage applied [-52]. 6.3 Silicon nitride over silicon dioxide

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Fig. 22. C-V plots showing examples for room-temperature trapping in silicon nitride layer on silicon. (100) oriented 1.4 x 1016cm -3 p-type silicon; 0.21/~m nitride thickness) (Ref. [54]).

The observed instability in metal-nitride-silicon can be greatly reduced by separating the silicon nitride layer and silicon with a thin SiO2 layer. This double layer structure has shown no trapping even up to destructive breakdown. This result is only valid if the SiO2 layer is thick. In the case of a thin layer of SiOz (50-500 A) the trapping can still occur, but higher threshold fields are required. The increase in threshold field is proportional to the oxide thickness and is considerably larger for negative bias. This is evident from Fig. 24. It is apparent from this figure

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Fig. 24. Voltage shift AV (due to room-temperature trapping) vs applied voltage for metal-nitride-oxide-silicon capacitors with various thicknesses of thermal oxide under 0.25 #m of silicon nitride (111) oriented 1.4 x 1016cm -3 p-type silicon (Ref. [54]). that as the oxide thickness increases from 0-500/~ the positive threshold voltage for a 0.25 #m silicon nitride film moves from 40 to 130 volts. The main feature of trapping mechanism observed in MNOS structure is mentioned here as given by Szedon and Chu [58]. It is proposed that with the applied positive bias the trapping occurs due to tunnelling of electrons from the silicon conduction band to the oxide conduction band, where they move through the oxide and are trapped in the silicon nitride layer. This is illustrated in Fig. 25, The threshold voltage represents the field large enough to allow tunnelling into the oxide conduction band. When the applied voltage is raised above threshold voltage, a large amount of charge flows through the oxide and is trapped in the silicon nitride layer. This trapped charge will reduce the oxide field back to the threshold value. This can be readily shown to produce a shift in the flat band voltage given by

395

VFB = V G - - Vcrit , a s is o b s e r v e d experimentally. T h e larger threshold voltages observed under negative bias are believed to be due to a lower tunnelling probability for holes into the valence band of SiO2 than for electrons into the conduction band. This phenomenon is very useful as a memory effect. The literature mainly describes two structures of MNOS memory transistors: one with an oxide thickness of 50-2130 A and the other with an oxide thickness of 15-75A. Both these transistors have the thickness of nitride layer in the range of 200-10130 A. The charge injection behaviour has been described by different possible mechanisms depending upon the thickness of underlying SiO2 [-59-65].

7. ION MIGRATION AND ELECTRONIC TRAPPING 7.1 Tantalum oxide Recently the reactively sputtered tantalum oxide films have received considerable attention as an insulating layer in MIS system due to their improved charge storage and ion stability behaviour. The amorphous and crystalline films were employed for the study. These films can be obtained by annealing the reactively sputtered Ta2Os films at temperatures of 600°C and 800°C, respectively. The room temperature instability behaviour on purely amorphous film is shown in Fig. 26, with the stress voltage applied from - I0 to I0 V. It is apparent from the figure that the curves of fiat band voltage have nearly identical negative slopes irrespective of the annealing conditions. The negative slope is characteristic of processes involving charge rearrangement within the oxide, e.g. ionic migration. However, with ion migration involving only one species, the fiat band voltage shifts usually are not symmetric with stress voltage. In the case of crystalline films asymmetric behaviour has been obtained which indicates the ion migration of a single species. I0

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Fig. 27. Upper panel: charge instability at 77 K showing injection trapping at the tantalum oxide-silicon interface for an unannealed film of tantalum oxide on silicon. The room temperature behaviour is shown as well. Lower panel: inferred room temperature charge behaviour after correction for the injection-trapping effects (Ref. [4]). Another instability behaviour was observed in the amorphous Ta205 films as shown in Fig. 27. For this, stress greater than 10V resulted in the shift of the flat band voltage in the opposite direction to ion migration. This indicates carrier injection from the silicon with subsequent trapping in the oxide. To separate out these two behaviours, i.e. ionic and charge injection, an unannealed amorphous Ta205 film was cooled to - 1 9 6 ° C to freeze out any ionic effects. The lower curve of Fig. 27 was obtained when the room temperature stress results are corrected by the amount attributed to the tunneling. This representation suggests that the charge rearrangement within the insulator proceeds over a wide range of bias stress at room temperature. Owing to a lot of complication with the injection and ionic behaviour, and also to the interaction with the silicon directly, this structure has not been used to study the ionic drift in more detail.

from Fig. 28 that no saturated charge, i.e. saturation shift in flat band voltage, has been observed for any of the stress applied. On the other hand, from experiments involving direct measurement of the ionic transient, a saturation charge density of 2 x l0 ~3 cm 2 was observed. This is about three to four times greater than the maximum charge indicated in Fig. 28. The mobile ionic species in Ta205 were not identified in these experiments. Clearly the large quantities of charge migrating under stress at elevated temperature indicate reasons for concern if this or similar material is to be used in high realiability applications. As mentioned previously, both the injection trapping and ionic charge instabilities are present in the sputtered Ta205 film on silicon. The latter persists even in the presence of thin layer of SiO2. In this case it can be argued that ion migration in SiO2 layer may have the dominant effect. Contrary to this no ionic migration in the composite system of SiO2 and Si3N~ has been observed. If there is no ionic migration in TazO5 films also, the double layer structure should be stable, which is not the case. It appears that the mobile species can migrate in both the films. Complete understanding of the phenomenon is still lacking and requires more investigations. Recent results indicate the absence of ionic instability in Ta205 films. These experiments however consisted of heating unbiased capacitors at 200=C for 2 hr and no significant flat band voltage shift was observed. With the results reported without biasing stress, it is not justified to conclude that the alkali ion concentrations in the oxide were low. A more rigorous study on these lines is required to understand the exact electrical nature of the films.

CONCLUSION

In recent years, extensive studies have been made which have resulted in clear understanding of charge instability mechanism in a variety of insulating films on silicon. In fact, as a result of these studies and ,,1 17 8 4

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7.2 Tantalum oxide over silicon dioxide The improved room temperature instability was observed using double insulating films, i.e. sputtered Ta205 film over an SiO/ layer. The attempts were also made to study the phenomena at an elevated temperature with stress bias applied for different time intervals. Figure 28 shows the shift in the flat band voltage. Initially the bias was applied at 100°C and the last four minutes were at 150°C. It is apparent

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Thin Insulating Films on Silicon with the recent advancements in semiconductor device technology, the surface devices such as I G F E T have become practical. But the knowledge of exact mechanisms involved in these instability p h e n o m e n a and their control is still empirical. Future studies can be expected to yield information on new insulators mainly to be used in double dielectric systems. The studies have already been started on new insulating materials, e.g. HFO2, SrTiO2, Y203 which have advantages over Si3N 4 a n d A1203 of high dielectric constants a n d are expected to yield low threshold voltage double dielectric systems. Acknowledgements--We are thankful to Dr. M. S. Tyagi and Dr. S. S. Kushwaha for critical reading of the manuscript. Thanks are also due to Mr. Ravi Chandra Dube, Scientists, CEERI, Pilani (Rajasthan) for sending the pertinent literature. Thanks are also extended to Dr. R. S. Srivastava and Dr. B. R. Marathe for their constructive suggestions and all the authors of the papers from which much of this material has been reproduced. REFERENCES 1. W. Shockley and G. L. Pearson, Phys. Rev. 74, 232 (1948). 2. A. S. Grove, B. E. Deal, E. H. Snow and C. T. Sah, Solid State Electronics 8, 145 (1964). 3. E. H. Snow and B. E. Deal, Trans. metal Soc. of AIME 242, 512 (1968). 4. J. R. Szedon and R. M. Handy, J. Vac. Sci. and Tech. 6, 1 (1969). 5. D. R. Kerr, Proc. 8th Reliab. Phys. Syrup. 1, (1970). 6. W. A. Pliskin, D. R. Kerr and J. A. Perri, Physics of Thin Films. Vol. 4, p. 257. Academic Press, Inc. New York (1967). 7. P. Balk, Solid State Devices: 1973. Conference series No. 19 The Inst. of Physics, London (1974). 8. D. Kahng and E. H. Nicollian, Appl. Solid State Sci. 3, 2 (1973). 9. D. R. Kerr, J. S. Logan, P. J. Burkhardt and W. A. Pliskin, IBM J. Res. Dev. 8, 376 (1964). 10. J. E. Thomas, Jr. and D. R. Young, IBM J. Res. Dev. 8, 368 (1964). 11. E. H. Snow, A. S. Grove, B. E. Deal and C. T. Sah, oJ. appl. Phys. 36, 1664 (1965). 12. D. R. Kerr, IEEE Solid State Device, Res. Conf. Santa Barbara (Calif.) (June 1967). 13. S. R. Hofstein, IEEE Trans. Electron. Devices ED°I3, 222 (1966). 14. B. R. Singh, S. S. Rai and R. S. Srivastava, Phys. Star. Solid, (a). 13, 51 (1972). 15. E. Yon, W. H. Ko and A. B. Kuper, IEEE Trans. Electron Devices ED-13, 276 (1966). 16. J. S. Logan and D. R. Kerr, IEEE Solid State Devices Research Conf. Princeton N.J. (June 1965). 17. L. V. Gregor, Sprin9 Meetin 9 of the Electrochem. Soc. Cleveland, Ohio, (May 1966). 18. B. Yurashi and B. E. Deal, J. electrochem. Soc. 115, 1191 (1968). 19. S. R. Hofstein, IEEE Trans. Electron Devices ED-14, 749 (1967). 20. S. R. Hofstein, Appl. Phys. Lett. 10, 291 (1967). 21. T. E. Burgess and F. M. Fowkos, Spring Meeting of the Electrochem. Soc. Cleveland, Ohio (May 1966). 22. P. J. Burkharat, J. electrochem. Soc. 114, 196 (1967). 23. M. H. Woods and R. Williams, J. appl. Phys. 44, 5506 (1973). 24. M. Kuhn and D. J. Silversmith, d. electrochem. Soc. 118, 966 (1971).

397

25. R. J. Kriegler and R. Bartnikas, IEEE Trans. Electron Devices ED-20, 722 (1973). 26. B. R. Singh, B. D. Tyagi and B. R. Marathe, Phys. Star. Solid, (a) 19, K 143 (1973). 27. B. R. Singh, B. D. Tyagi and B. R. Marathe, The Electrochem. Soc. Meeting, San Francisco, Calif. (May 1974). 28. R. Schmidt, J. electrochem. Soc. 115, 193C (1968). 29. E. H. Snow and B. E. Deal, J. electrochem. Soc. 113, 263 (1966). 30. J. M. Eldridge, R. B. Laibowitz and P. Balk, J. appl. Phys. 40, 1922 (1969). 31. P. H. Robinson and F. P. Heiman, J. electrochem. Soc. 118, 141 (1971). 32. R. J. Kriegler, Y. C. Cheng and D. R. Colton, J. electrochem. Soc. 119, 388 (1972). 33. R. J. Kriegler, A. Aitken and J. D. Morris, Proc. 5th Conf. on Solid Star Devices, Tokyo (1973). 34. M. Severi and G. Soncini, Electronics Lett. 8, 480 (1972). 35. B. R. Singh, B. D. Tyagi, A. N. Chandorkar and B. R. Marathe, The Electrochem Soc. Meeting, San Francisco, Calif. (May 1974). 36. S. Y. Wo and N. P. Formigoni, J. appl. Phys. 39, 5613 (1968). 37. D. R. Kerr, I B M J. Res. Dev. 8, 385 (1964). 38. W. A. Pliskin, J. electrochem. Soc. 114, 620 (1967). 39. E. H. Snow and M. E. Dumesnil, J. appl. Phys. 37, 2123 (1966). 40. B. R. Singh, J. phys. D. Appl. Phys. 7, 443 (1974). 41. T. M. Buck, F. G. Allen, J. V. Dalton and J. D. Strutters, J. electrochem. Soc. 114, 862 (1967). 42. H. G. Carlson, G. A. Brown, C. R. Fuller and J. Osborme, Phys. Failure Electron. 4, 390 (1966). 43. J. M. Eldridge and D. R. Kerr, J. electrochem. Soc. 118, 986 (1971). 44. Y. T. Yeow, J. W. Clancy and D. R. Lamb, Int. J. Electronics 34, 115 (1973). 45. B. R. Singh and R. S. Srivastava, J. Int. Telecom. Engrs. 19, 471 (1973). 46. F. P. Heiman and G. Warfield, IEEE Trans. Electron Devices ED-12, 167 (1965). 47. K. Saminadayer, J. Pautrat and J. Pfister, Compt. Rend., 264, 254 (1967). 48. S. R. Hofstein, Solid State Electronics 10, 657 (1967). 49. B. E. Deal, M. Sklar, A. S. Grove and E. H. Snow, J. electrochem. Soc. 114, 266 (1967). 50. A. Goetzberger and H. E. Nigh, Proc. IEEE 54, 1454 (1966). 51. Y. Miura and Y. Matuhura, Japan J. appl. Phys. 5, 180 (1966). 52. T. L. Chu, J. R. Szedon and C. H. Lee, Solid State Electronics 18, 867 (1967). 53. J. V. Dalton and J. Drobek, J. eIectrochem. Soc. ll5, 865 (1968). 54. B. E. Deal, P. J. Fleming and P. L. Castro, J. electrochem. Soc. 115, 300 (1968). 55. H. C. Pao and M. O. Connel, Appl. Phys. Lett. 12, 260 (1968). 56. S. M. Hu, J. electrochem. Soc. 113, 693 (1966). 57. S. M. Hu, D. R. Kerr and L. V. Gregor, Appl. Phys. Lett. 10, 97 (1967). 58. J. R. Szedon and T. L. Chu, IEEE Solid State Device Res. Conf. Santa Barbara, Calif. (June 1967). 59. E. C. Ross and J. T. Wallmark, RCA Rev. 30, 367 (1969). 60. F. A. Sewell Jr., H. A. R. Wegener and E. T. Lewis, Appl. Phys. Lett. 14, 45 (1969). 61. Dr. Frohman-Betchkowsky and M. Lenzlinger, J. appl. Phys. 40, 3307 (1969). 62. G. Dorda and M. Pulver, Phys. Star. Solid, (a) 1, 71 (1970).

398

B.R. SINGH and KESHAW SINGH

63. K. I. Lundstrom and C. M. Svensson, IEEE Trans. Electron Devices ED-19, 826 (1972). 64. E. H. Nicollian, A. Goetzberger and C. N. Berglund, Appl. Phys. Lett. 15, 774 (1969).

65. C. Svensson and I. Lundstrom, J. appl. Phys. 44, 4657 (1973). 66. T. Takemoto, T. Ishihara and K. Akiyama, Japan J. appl. Phys. 5, 844 (1966).