- Email: [email protected]
Integrated circuit production yield assurance based on yield analysis
Microelectronics Journal, 24 (1993) 819-822
i:¸¸ i~il
Integrated circuit production yield assurance based on yield analysis* Z. StamenkoviG S. Dimitrijev t and N. Stojadinovi( Faculty qf Electronic En,cineering, University qflNE, 18000 NE, Yugoslavia
The production of modern integrated circuits must be accompanied by control of the critical process steps, modern integrated circuit production control being based on yield analysis. It is shown in this paper that yield analysis can also be used to ensure efficient investments and predict investments which are required in order to ensure a competitive yield of future products. 1. Introduction here are three different but consecutive facts related to integrated circuit p r o d u c tion yield. T h e first is process disturbance, w h i c h can be defined as any r a n d o m p h e n o m e n o n manifesting itself in a permanent r a n d o m m o d i fication o f the physical characteristics o f a fabricated integrated circuit structure. Fluctuations in the temperature during oxide growth and diffusion o f impurities or the cleanliness o f a cleanr o o m are typical examples o f disturbanccs. Process disturbances cause defects and faults in
T
*This paper was presented at the P,electronic '91 Conference, Budapest, Hungary, 26-30 August 1991. tPresent address: School of Microelectronics Engineering, Griffith University, Brisbane, Australia.
integrated circuit structures [•]. Examples o f defects include pinholes in insulator layers, dislocations and photolithographic defects. Finally, an electrically active defect which causes a failure o f the integrated circuit chip (short circuit, open circuit, excessive leakage current, etc.) is referred to as a fault. T h e disturbances themselves are impossible to measure. T h e only evidence o f their existence is the appearance o f defects and faults. However, these are not easy to characterize, either. Simplified characterizations o f defects are difficult to extract from the available manufacturing data. T h e problem is that in the m o d e r n integrated circuit fabrication line, the majority o f defects are very small (smaller than 3/in1). As the defect density is small too, the observability o f the defects w h i c h can be achieved by making use o f standard measurement techniques is very low. Therefore, in industrial practices the disturbances are characterized mainly in terms o f fault densities (a n u m b e r o f faults per unit area or per chip [2]). Nevertheless, for proper and efficient control o f the integrated circuit production
0026-2692/93/$6.00 ~ 1993, Elsevier Science Publishers Ltd.
819
Z. Stamenkovid et al./Integrated circuit production
process, the process disturbances should bc characterized by the test chip yield measurcments. A yield model which does not require any defect or fault density detcrmination but is completely based on the test structure yield measurement and is suitcd to the integrated circuit production control has recently been proposed [31. It will be shown in this papcr that the above-mentioned yield model can not only be used for a successful integrated circuit production control but offi:rs a sophisticated characterization of the integrated circuit production process. In particular, aftcr a brief description of the model itself, it will bc shown h o w the yield-analysis-bascd characterization of an integrated circuit production process can bc used to propcrly design investments in thc integrated circuit production process.
2. Yield model
A suitablc way to control in-line production is the use of monitor wafers with test chips containing specially designed test structures. Thcsc monitor wafers are proccssed togethcr with the production wafers, and should rcflcct the disturbances which influence the yield of production wafers [3, 4]. Using corresponding in-linc measurements of the test chip yield, which will be denoted by Y,i and defined as the ratio between the numbcr of good test chips and the total number of test chips in a given wafer area, the integrated circuit chip yicld, associated with the ith critical process step, can bc directly predicted. The intcgrated circuit chip yield will diffcr from the tcst chip yicld owing to the difference in so-called active or critical area. So, if the ratio between the integrated circuit chip and the test chip critical area is given by A,-i/A~,, the integrated circuit chip yield can be determined by [31
820
y,.,= y~:L,/.],,
(1)
Chip yield is a quantity defined as the probability that a given chip contains no faults. Therefore the chip yield should, in principle, be determined for each chip from the wafer after each critical process. However, there is no need to calculate the chip yield for each chip separately, since the probability of fault-free chips (i.e. chip yield) is the same for each chip which belongs to an area with approximately a uniform distribution of faults. It is typical that the faults will bc clustcrcd, but the wafer area can be divided into m subareas with approximately uniform distribution of faults [3,5]. Consequently, the expression (1) can bc rcwrittcn in the form =
(2)
where {' denotes tile corresponding subarea. However, the chip yicld is not enough for complete yield characterization, and the wafer yield, Yi, dcfincd as the ratio bctwecn the number of good chips n and total number of chips in a wafer N, should bc predicted as well. It is important to note that thc number of good chips in a wafer and thc wafer yield are stochastic variables, and appear through their distribution functions. The parametcrs of the wafer yield distribution fimction, mean Yi and variance 0-{.i, are given by
[3] Y, =
(3)
C.Y.. t=l
(1/N)
c,., Y..,
(1
(4)
[=1
whcrc C , is equal to the gth subarea divided by the total wafer area.
Microelectronics Journal, Vol. 24
At the end, the final wafer yield should be modeled as well. It has been shown that the parameters o f the final wafer yield distribution (mean Y and variance rrp) can be approximated by [3, 6] - -
9
(s)
Y = H Y, i=l
9 O'y
H (O'2Yiq- y 2 ) __ i=1
gi
(6)
i=1
3. Yield analysis By making use o f the above-described yield model, yields associated with each critical process step can be determined. An example of such a characterization o f an integrated circuit production process is given in Table 1. The data pertain to well-known and rather simple C D 4 0 0 0 series C M O S integrated circuit production. Six critical processes, which are listed in Table 1, were assumed to be responsible for the yield loss and were accompanied by inline yield measurements made on the corresponding test structures, and the consequent yield analysis.
The gate oxide formation (step 4 in Table 1) is commonly considered as the most critical process step in M O S technologies, and consequently much attention is normally paid to this process step. However, it can be seen from Table 1 that in this particular example the yield associated with p+-diffusion was much smaller than the yields o f the other process steps and, therefore, was the main cause o f the wafer yield loss. It was obvious that in this example a further investment in the process o f gate oxide formation could not improve the final wafer yield, while an investment in the process of p+-diffusion would be extremely beneficial. It can be seen from Table 1 that an investment made to improve the process o f p+-diffusion (enhancement o f the process cleanliness, etc.) resulted in a final wafer yield increase o f over 10%. Such a yield improvement could not be achieved by an investment in any other critical process step. As has been mentioned in the introductory section, the usual approach to integrated circuit production control is based on dcfcct or fault density measurements. However, this approach does not take into account the dependence on the complexity o f a given integrated circuit type and, therefore, many wafers may be stopped regardless of the integrated circuit type. That is to say, a given defect density level can enable an
TABLE 1 Yield modeling results Critical process
Mean qf wqfi'r yield, Yi CD4011B
1. 2. 3. 4. 5. 6.
p -diffusion pe -diffusion n+-diffusion Gate oxide formation Photo for contacts Photo for metal
0.952 0.845/0.928a 0.966 0.993 0-984 0.958
Mean of final wafer yield, Y
0.727/0.799"
CD4 520B
0.884 0.671/0.792" 0.897 0.978 0-949 0.867 0.428/0-505"
"After investment in the p+-diffusion process.
821
Z. Stamenkovi6 et al./Integrated circuit production
acceptable yield (and, consequcntly, price) of" simpler integratcd circuit chips, but it may not be sufficient to achieve the desircd yicld and pricc o f more complex integrated circuit chips. The approach considered in this paper docs not suffer from thc described disadvantagc. M o r e ovcr, it can bc used to forecast and characterize yields o f futurc products to decidc about investments which cnablc thc desircd final intcgratcd circuit production yield. In the considered example o f production o f C114011B integrated circuits, it is estimatcd that the mcan o f thc wafer yicld associatcd with p+diffusion and its variance should be higher than 0-92 and lower than 3-5 x 10 5, respectivcly, to cnsurc the acceptablc value o f thc final wafer yield. It can bc sccn from Fig. 1 that the currently cstablishcd p+-diffusion process fiflfills the imposcd requirements. H o w c v c r , in thc case o f production o f C114520B integrated circuits, thc same defect dcnsity associatcd with thc p - diffusion process gavc a mean o f the wafer yield o f 0-792 and a variancc o f 2.23 × 10 -4, both being far from the estimated limits prcscnted in Fig. 1. Thcrefore, to achicvc the compctitive pricc with thc possiblc production o f morc complex C114520B intcgrated circuits, a fi]rthcr invcstmcnt in p+-diffusion process should bc nlade. CD4OIIB Ac2=O. IT9mm a
+?
m~$2(I0 -4 )
+Y
First, the most critical proccss stcp is discovered bccause o f invcstment effects. This is thc first control level. The ntean o f wafer yicld is enough to discover the most critical process step. Then, an cfficient invcstmcnt for the achievemcnt o f a higher yield can bc made. W h e n an improvcmcnt in the most critical process is carricd out and the desircd stability of this proccss is rcached, wc can m o v e on to the second control level. At this control level we must dccide about thc integrated circuit typcs which should bc produced. Thc usual approach to intcgratcd circuit production control is to cstimatc the dcfect density and docs not allow the opportunity to selcct integratcd circuit typcs. H o w c v c r , our app_jroach uses both yic!d parameters, thc mcan Y, and the variancc 0-~,i o f the wafer yield distribution fimction, and enables thc sophisticatcd selection ofintcgrated circuit typcs.
Acknowledgment This work was supportcd by the Sciencc Council o f thc Republic o f Serbia.
References Ill [2]
CD4520B Ac2=O. S66mm a
~¢$a(10-4)
2
4. S um m ary
[3] [4]
O. 9 2 1
.
.
.
.
.
.
.
.
.
d- 0 . 3 5 0
0.85 1
..........
=-t2.15
Fig. 1. Example ofintcgratcd circuit typc sclcction (Y"I 0.998 and a~., = 0.99 × 10 1 for the (;114(111B intc~atcd circuit; YeI = 0.792 and av2D = 2.23× 10 * fbr the C1)4520B integrated circuit).
822
[5]
0
[6]
W. Maly, Computer-aided design for VLSI circuit manuf~lcturability, lhoca,ditlqs ( f the l,tiE.~i, 78 (1990) 356-3~)2. C. It. Stappcr, F. M. Arlnstrong and K. Saji, Intcgratcd circuit yield statistics, Proa,ediHy,s ~ftlu' IEEIL 71 (1983) 453-470. S. l)imitrijcv, N. Stojadmovi(- and Z. Stamcnkovi& Yield model fi~r in-linc intcgratcd circuit production control, Solid-State FJectromcs, 31 (1988) 975-979. Z. Stamcnkovi( and S. l)imitrijcv, Chip yield estimation by tcst structurc nlcasurcmcnts, Proa'edittk, s of the XXI" Yt(eosla~, Symt~osim.~ o~s Eh,ctrou 1)ella's amt Materials, Maribor 1989, pp. 33-39. R.M. Warner, Applying a compositc model to the IC yicld problem, IEF.EJolmml olSolid-Statc Cinuits, 9 (1974) 86-95. z. Stamcnkovi(- and S. l)imitrijcv, ()n thc expressions for final wafer yield modeling, Proa'editlqs ( f the XI~7 Yt{~,oslm, Co~tfi, rctta' o~l Micmelcctnmics, Zagreb, 1988, pp. 407-413.
i:¸¸ i~il
Integrated circuit production yield assurance based on yield analysis* Z. StamenkoviG S. Dimitrijev t and N. Stojadinovi( Faculty qf Electronic En,cineering, University qflNE, 18000 NE, Yugoslavia
The production of modern integrated circuits must be accompanied by control of the critical process steps, modern integrated circuit production control being based on yield analysis. It is shown in this paper that yield analysis can also be used to ensure efficient investments and predict investments which are required in order to ensure a competitive yield of future products. 1. Introduction here are three different but consecutive facts related to integrated circuit p r o d u c tion yield. T h e first is process disturbance, w h i c h can be defined as any r a n d o m p h e n o m e n o n manifesting itself in a permanent r a n d o m m o d i fication o f the physical characteristics o f a fabricated integrated circuit structure. Fluctuations in the temperature during oxide growth and diffusion o f impurities or the cleanliness o f a cleanr o o m are typical examples o f disturbanccs. Process disturbances cause defects and faults in
T
*This paper was presented at the P,electronic '91 Conference, Budapest, Hungary, 26-30 August 1991. tPresent address: School of Microelectronics Engineering, Griffith University, Brisbane, Australia.
integrated circuit structures [•]. Examples o f defects include pinholes in insulator layers, dislocations and photolithographic defects. Finally, an electrically active defect which causes a failure o f the integrated circuit chip (short circuit, open circuit, excessive leakage current, etc.) is referred to as a fault. T h e disturbances themselves are impossible to measure. T h e only evidence o f their existence is the appearance o f defects and faults. However, these are not easy to characterize, either. Simplified characterizations o f defects are difficult to extract from the available manufacturing data. T h e problem is that in the m o d e r n integrated circuit fabrication line, the majority o f defects are very small (smaller than 3/in1). As the defect density is small too, the observability o f the defects w h i c h can be achieved by making use o f standard measurement techniques is very low. Therefore, in industrial practices the disturbances are characterized mainly in terms o f fault densities (a n u m b e r o f faults per unit area or per chip [2]). Nevertheless, for proper and efficient control o f the integrated circuit production
0026-2692/93/$6.00 ~ 1993, Elsevier Science Publishers Ltd.
819
Z. Stamenkovid et al./Integrated circuit production
process, the process disturbances should bc characterized by the test chip yield measurcments. A yield model which does not require any defect or fault density detcrmination but is completely based on the test structure yield measurement and is suitcd to the integrated circuit production control has recently been proposed [31. It will be shown in this papcr that the above-mentioned yield model can not only be used for a successful integrated circuit production control but offi:rs a sophisticated characterization of the integrated circuit production process. In particular, aftcr a brief description of the model itself, it will bc shown h o w the yield-analysis-bascd characterization of an integrated circuit production process can bc used to propcrly design investments in thc integrated circuit production process.
2. Yield model
A suitablc way to control in-line production is the use of monitor wafers with test chips containing specially designed test structures. Thcsc monitor wafers are proccssed togethcr with the production wafers, and should rcflcct the disturbances which influence the yield of production wafers [3, 4]. Using corresponding in-linc measurements of the test chip yield, which will be denoted by Y,i and defined as the ratio between the numbcr of good test chips and the total number of test chips in a given wafer area, the integrated circuit chip yicld, associated with the ith critical process step, can bc directly predicted. The intcgrated circuit chip yield will diffcr from the tcst chip yicld owing to the difference in so-called active or critical area. So, if the ratio between the integrated circuit chip and the test chip critical area is given by A,-i/A~,, the integrated circuit chip yield can be determined by [31
820
y,.,= y~:L,/.],,
(1)
Chip yield is a quantity defined as the probability that a given chip contains no faults. Therefore the chip yield should, in principle, be determined for each chip from the wafer after each critical process. However, there is no need to calculate the chip yield for each chip separately, since the probability of fault-free chips (i.e. chip yield) is the same for each chip which belongs to an area with approximately a uniform distribution of faults. It is typical that the faults will bc clustcrcd, but the wafer area can be divided into m subareas with approximately uniform distribution of faults [3,5]. Consequently, the expression (1) can bc rcwrittcn in the form =
(2)
where {' denotes tile corresponding subarea. However, the chip yicld is not enough for complete yield characterization, and the wafer yield, Yi, dcfincd as the ratio bctwecn the number of good chips n and total number of chips in a wafer N, should bc predicted as well. It is important to note that thc number of good chips in a wafer and thc wafer yield are stochastic variables, and appear through their distribution functions. The parametcrs of the wafer yield distribution fimction, mean Yi and variance 0-{.i, are given by
[3] Y, =
(3)
C.Y.. t=l
(1/N)
c,., Y..,
(1
(4)
[=1
whcrc C , is equal to the gth subarea divided by the total wafer area.
Microelectronics Journal, Vol. 24
At the end, the final wafer yield should be modeled as well. It has been shown that the parameters o f the final wafer yield distribution (mean Y and variance rrp) can be approximated by [3, 6] - -
9
(s)
Y = H Y, i=l
9 O'y
H (O'2Yiq- y 2 ) __ i=1
gi
(6)
i=1
3. Yield analysis By making use o f the above-described yield model, yields associated with each critical process step can be determined. An example of such a characterization o f an integrated circuit production process is given in Table 1. The data pertain to well-known and rather simple C D 4 0 0 0 series C M O S integrated circuit production. Six critical processes, which are listed in Table 1, were assumed to be responsible for the yield loss and were accompanied by inline yield measurements made on the corresponding test structures, and the consequent yield analysis.
The gate oxide formation (step 4 in Table 1) is commonly considered as the most critical process step in M O S technologies, and consequently much attention is normally paid to this process step. However, it can be seen from Table 1 that in this particular example the yield associated with p+-diffusion was much smaller than the yields o f the other process steps and, therefore, was the main cause o f the wafer yield loss. It was obvious that in this example a further investment in the process o f gate oxide formation could not improve the final wafer yield, while an investment in the process of p+-diffusion would be extremely beneficial. It can be seen from Table 1 that an investment made to improve the process o f p+-diffusion (enhancement o f the process cleanliness, etc.) resulted in a final wafer yield increase o f over 10%. Such a yield improvement could not be achieved by an investment in any other critical process step. As has been mentioned in the introductory section, the usual approach to integrated circuit production control is based on dcfcct or fault density measurements. However, this approach does not take into account the dependence on the complexity o f a given integrated circuit type and, therefore, many wafers may be stopped regardless of the integrated circuit type. That is to say, a given defect density level can enable an
TABLE 1 Yield modeling results Critical process
Mean qf wqfi'r yield, Yi CD4011B
1. 2. 3. 4. 5. 6.
p -diffusion pe -diffusion n+-diffusion Gate oxide formation Photo for contacts Photo for metal
0.952 0.845/0.928a 0.966 0.993 0-984 0.958
Mean of final wafer yield, Y
0.727/0.799"
CD4 520B
0.884 0.671/0.792" 0.897 0.978 0-949 0.867 0.428/0-505"
"After investment in the p+-diffusion process.
821
Z. Stamenkovi6 et al./Integrated circuit production
acceptable yield (and, consequcntly, price) of" simpler integratcd circuit chips, but it may not be sufficient to achieve the desircd yicld and pricc o f more complex integrated circuit chips. The approach considered in this paper docs not suffer from thc described disadvantagc. M o r e ovcr, it can bc used to forecast and characterize yields o f futurc products to decidc about investments which cnablc thc desircd final intcgratcd circuit production yield. In the considered example o f production o f C114011B integrated circuits, it is estimatcd that the mcan o f thc wafer yicld associatcd with p+diffusion and its variance should be higher than 0-92 and lower than 3-5 x 10 5, respectivcly, to cnsurc the acceptablc value o f thc final wafer yield. It can bc sccn from Fig. 1 that the currently cstablishcd p+-diffusion process fiflfills the imposcd requirements. H o w c v c r , in thc case o f production o f C114520B integrated circuits, thc same defect dcnsity associatcd with thc p - diffusion process gavc a mean o f the wafer yield o f 0-792 and a variancc o f 2.23 × 10 -4, both being far from the estimated limits prcscnted in Fig. 1. Thcrefore, to achicvc the compctitive pricc with thc possiblc production o f morc complex C114520B intcgrated circuits, a fi]rthcr invcstmcnt in p+-diffusion process should bc nlade. CD4OIIB Ac2=O. IT9mm a
+?
m~$2(I0 -4 )
+Y
First, the most critical proccss stcp is discovered bccause o f invcstment effects. This is thc first control level. The ntean o f wafer yicld is enough to discover the most critical process step. Then, an cfficient invcstmcnt for the achievemcnt o f a higher yield can bc made. W h e n an improvcmcnt in the most critical process is carricd out and the desircd stability of this proccss is rcached, wc can m o v e on to the second control level. At this control level we must dccide about thc integrated circuit typcs which should bc produced. Thc usual approach to intcgratcd circuit production control is to cstimatc the dcfect density and docs not allow the opportunity to selcct integratcd circuit typcs. H o w c v c r , our app_jroach uses both yic!d parameters, thc mcan Y, and the variancc 0-~,i o f the wafer yield distribution fimction, and enables thc sophisticatcd selection ofintcgrated circuit typcs.
Acknowledgment This work was supportcd by the Sciencc Council o f thc Republic o f Serbia.
References Ill [2]
CD4520B Ac2=O. S66mm a
~¢$a(10-4)
2
4. S um m ary
[3] [4]
O. 9 2 1
.
.
.
.
.
.
.
.
.
d- 0 . 3 5 0
0.85 1
..........
=-t2.15
Fig. 1. Example ofintcgratcd circuit typc sclcction (Y"I 0.998 and a~., = 0.99 × 10 1 for the (;114(111B intc~atcd circuit; YeI = 0.792 and av2D = 2.23× 10 * fbr the C1)4520B integrated circuit).
822
[5]
0
[6]
W. Maly, Computer-aided design for VLSI circuit manuf~lcturability, lhoca,ditlqs ( f the l,tiE.~i, 78 (1990) 356-3~)2. C. It. Stappcr, F. M. Arlnstrong and K. Saji, Intcgratcd circuit yield statistics, Proa,ediHy,s ~ftlu' IEEIL 71 (1983) 453-470. S. l)imitrijcv, N. Stojadmovi(- and Z. Stamcnkovi& Yield model fi~r in-linc intcgratcd circuit production control, Solid-State FJectromcs, 31 (1988) 975-979. Z. Stamcnkovi( and S. l)imitrijcv, Chip yield estimation by tcst structurc nlcasurcmcnts, Proa'edittk, s of the XXI" Yt(eosla~, Symt~osim.~ o~s Eh,ctrou 1)ella's amt Materials, Maribor 1989, pp. 33-39. R.M. Warner, Applying a compositc model to the IC yicld problem, IEF.EJolmml olSolid-Statc Cinuits, 9 (1974) 86-95. z. Stamcnkovi(- and S. l)imitrijcv, ()n thc expressions for final wafer yield modeling, Proa'editlqs ( f the XI~7 Yt{~,oslm, Co~tfi, rctta' o~l Micmelcctnmics, Zagreb, 1988, pp. 407-413.