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Integrated on-chip energy storage using passivated nanoporous-silicon electrochemical capacitors
Author’s Accepted Manuscript Integrated On-Chip Energy Storage Using Passivated Nanoporous-Silicon Electrochemical Capacitors D.S. Gardner, C.W. Holzwarth, Y. Liu, S.B. Clendenning, W. Jin, B.K. Moon, C. Pint, Z. Chen, E. Hannah, C. Chen, C.P. Wang, E. Mäkilä, R. Chen, T. Aldridge, J.L. Gustafson
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S2211-2855(16)30074-X http://dx.doi.org/10.1016/j.nanoen.2016.04.016 NANOEN1221
To appear in: Nano Energy Received date: 13 September 2015 Revised date: 26 February 2016 Accepted date: 13 April 2016 Cite this article as: D.S. Gardner, C.W. Holzwarth, Y. Liu, S.B. Clendenning, W. Jin, B.K. Moon, C. Pint, Z. Chen, E. Hannah, C. Chen, C.P. Wang, E. Mäkilä, R. Chen, T. Aldridge and J.L. Gustafson, Integrated On-Chip Energy Storage Using Passivated Nanoporous-Silicon Electrochemical Capacitors, Nano Energy, http://dx.doi.org/10.1016/j.nanoen.2016.04.016 This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting galley proof before it is published in its final citable form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
Integrated On-Chip Energy Storage Using Passivated Nanoporous-Silicon Electrochemical Capacitors D. S. Gardnera, C. W. Holzwarth IIIa, Y. Liua, S. B. Clendenninga, W. Jina, B. K. Moona, C. Pinta, Z. Chena, E. Hannaha, C. Chenb, C. P. Wangb, E. Mäkiläc, R. Chena, T. Aldridgea, and J. L. Gustafsona a
Intel Corp., 3065 Bowers Ave., Santa Clara, CA 95052 USA Florida Intl. University, Dept. of Mech. and Materials Engr., 10555 W Flagler St., Miami, FL 33174 USA c University of Turku, Dept. of Physics and Astronomy, FI-20500, Finland Email: [email protected]
b
Fig. 1. Stack of P-Si substrates with electronic circuitry on the top substrate. Abstract
Integrated on-chip energy storage is increasingly important in the fields of internet of things, energy harvesting, sensing, and wearables; capacitors being ideal for devices requiring higher powers or many thousands of cycles. This work demonstrates electrochemical capacitors fabricated using an electrolyte and porous silicon nanostructures with very high surface-to-volume ratios. Nanopore morphologies and passivation coatings for maximizing energy and power densities of porous-silicon based electrochemical capacitors are studied. Stability is achieved through atomic layer deposition (ALD) titanium nitride or chemical vapor deposition (CVD) carbon coatings. The use of silicon processing methods creates the potential for on-chip energy storage. Keywords Porous silicon, atomic layer deposition, carbonization, electrochemical capacitors
Introduction With the emergence of the Internet of Things (IoT), over 50 billion connected devices are expected by 2020 [1, 2]. New types of devices are being invented continuously, each with their own unique power requirements. Many of these devices are not connected to the power grid: wireless sensors, health monitors, wearables, etc., and require integrated energy storage and/or energy harvesting capability. The typical power profile for these types of devices is very low power during standby and data collection with a significantly higher peak power needed for data transmission. The low power modes can be supported by an energy-harvesting device; however, for the high power modes, an electrochemical (EC) capacitor is an ideal candidate. EC capacitors outperform batteries for these types of devices since they can capture energy at high rates and at lower voltages than batteries as well as provide higher peak power. Although the energy density for EC capacitors is significantly less (~20×) than batteries, when paired with an energy harvester, the important figure of merit is lifetime energy density (energy density × cycle lifetime). Unlike batteries, EC capacitors are electrostatic devices and do not rely on chemical reactions to store energy. This enables them to achieve higher cycle lifetimes of many thousands of times, easily compensating for their lower energy density. This is especially true for the billions of off-power-grid IoT devices where it is not possible to regularly replace the batteries. Silicon is already the material of choice for the integrated circuits found in every IoT device. Fig. 1. Charge-discharge measurement While there are numerous research efforts to integrate energy harvesting devices on-chip, the of a stack of P-Si such as in Fig. 1.
Fig. 2. Tapered porous silicon nanostructure created by changing the current density during etching. The tapered profile (in blue) can be optimized for desired device performance (e.g. faster speed or higher capacitance).
effort to integrate EC capacitors on a silicon die has to date been limited. Typically EC electrodes are comprised of high surface area carbon micro-particles, but due to possible contamination and electrical shorting when processing with conductive particles, a particle based electrode is not a good candidate for an integrated solution. A potentially better choice is high-surface area porous silicon nanostructures as the electrode material (see Figs. 1 and 2). Silicon nanostructures have already been used extensively as battery anodes in the form of nanowires [3], nanotubes [4], nanoporous particles [5, 6], and (macro-, meso-, nano-) porous silicon (P-Si) films [7-9]. Also, hybrid EC capacitors using carbon-coated Si/SiO2 particles as an anode have been demonstrated [10]. However, the few publications regarding porous silicon as an electrode material for EC capacitors have either required high temperature processes incompatible with on-chip integration or macroporous silicon (pores diameters larger than 50 nm) which limits the surface area and therefore the overall achievable performance. This paper presents EC capacitors based on P-Si nanostructures with highly branched pores coated with atomic layer deposited (ALD) films (see Fig. 3). The main pore diameter is tapered from 100 to 20 nm; the majority of the surface area comes from the branching structure along the pore walls consisting of nanopores in the 5 to 15 nm range. P-Si has poor conductivity as well as poor chemical and mechanical stability because the silicon surface can easily oxidize. Consequently, the energy density of P-Si coated with a conductive passivation film is significantly higher. Measurements of coated P-Si capacitors reveal that an areal capacitance of 3 to 6 mF/cm2 can be achieved using 2 m deep pores and the capacitance scaled approximately linearly with depth with 28 mF/cm2 measured for 12 m deep pores [11-14]. These results are one to two orders of magnitude higher than the other studies utilizing P-Si [15-18]. These devices were fabricated using silicon process methods with the potential for on-chip integration. The pores can be formed in localized regions on the front side or on the backside, utilizing the bulk Si, of a silicon die containing integrated circuits and a kinetic or solar energy harvesting device such as a silicon solar cell [19]. The EC capacitors can be integrated into silicon chips and used as a micro-supercapacitor for energy storage in several different ways. Pores can be patterned into localized regions of silicon and then a coating can be applied to form the second electrode or pores can be formed in a side-by-side planar design. In addition, pores can be formed on the backsides of two silicon die and stacked to form an EC, optionally pores can be formed on both sides of silicon die creating a double-sided substrate and then inserted into the stack creating the configuration shown in Fig. 1. The porous volume and space between P-Si electrodes is filled with a liquid or preferably solid electrolyte [20]. Solid-state electrolyte alternatives include gel-polymer electrolytes [21, 22] and ionic-liquid based gelled electrolytes called ionogels [22, 23]. The series resistance can be minimized by using thin highly-doped silicon substrates. The stacked P-Si structure has the advantage of being a thin form factor with minimal impact on the area available for circuits. Additionally, it is relatively easy to manufacture, building off of die stacking technologies already developed for 3D integrated circuits. The measurements from a stack of silicon dies in Fig. 2 shows a charge-discharge cycle to 5 volts. In this configuration, there are two EC capacitors in series resulting in a doubling of the operating voltage and areal energy (volumetric energy remains the same). This can provide localized low-energy storage such as that needed for integrated sensors. Experimental
Fig. 5. Cross sectional images of carbonized P-Si created at 500 °C through reaction with acetylene followed by a second ramp up to 720 °C (see [8, 10] for details).
Fig. 4. SEM images of top of porous region (left) before and (right) after stop-flow ALD TiN deposition. The pore walls become thicker but the overall pore structure does not change.
To maximize the performance of P-Si electrochemical capacitors, it is important to optimize the pore structure and surface properties. The pore structure can be characterized with five interdependent parameters: pore size, surface area, porosity, depth, and morphology; likewise, the surface properties can be characterized by chemical stability, conductivity and wettability. A. Porous-Silicon Nanostructure The following properties control the performance of the electrochemical capacitor: capacitance, operating voltage, cycle lifetime, and operating frequency. The total surface area needs to be high to obtain large capacitance which requires small pore diameters and deep etch depths that create high-aspect-ratio features. The high-aspect ratios can lead to high effective series resistance (ESR) because of the long path that ionic charge carriers have to traverse. Contrariwise for high operating frequency, large pore diameters are preferred for fast ion transport. For optimal performance, a pore structure with an open central channel (fast transport) and many smaller pores branching out along the sidewall (high surface area) is desired. The need for the central open channel diminishes the closer one gets to the bottom of the porous layer favoring smaller highly-branched pores. In an effort to create this optimal structure, a tapered-pore nanostructure with main channel sizes tapering from 100 nm to 20 nm and with the degree of branching increasing with depth (see Fig. 3) was developed to deliver extremely high surface-to-volume ratios. Electrochemical etching using hydrofluoric acid and isopropyl alcohol (2:1 HF:IPA) was employed [24] to etch the P-Si nanostructures with depths of up to 250 m and a porosity of ~75%. IPA was added to reduce the hydrogen gas generation and improve the homogeneity of P-Si [25, 26]. The etching apparatus is a double tank electrochemical cell for 4 inch Si wafers developed by AMMT [27]. The electrical symmetry of this cell with front side and backside contact via the HF:IPA etchant, allows for double sided P-Si fabrication by simply reversing the current direction. Highly doped (100) p-type silicon (0.01 to 0.001 -cm) was chosen because it provides good electrode conductivity. Depending on the current density used, wide smoother-walled pores or narrow highly-branched pores can be achieved. Silicon with less dopant can be used, but process parameters (current density, HF concentration, temperature, etc.) need to be adjusted appropriately to obtain similar structures [25, 26]. As part of the etching procedure, a sacrificial layer process is used to ensure fully open pores; it consists of a high current density etch followed by a KOH strip before the P-Si etch process. This proved to be essential for ALD coating penetration and for device operation at higher power densities. After etching, native silicon oxide 0.1 nm to 0.2 nm thick can form in air within 1 hour on the freshly etched silicon surfaces [28, 29]. This would result in a significant capacitance drop, so samples were stored in a nitrogen ambient soon after etching. It should be noted that although the anodization process is a simple method for synthesizing P-Si, dry etching processes (such as: deep reactive-ion etching) could
Fig. 3. Pore size distribution from BET adsorption analysis of three different etching current densities demonstrating the inverse relationship between pore diameter and surface-area density.
Fig. 6. SEM cross sectional image with an EDS depth profile of Ti and N concentrations superimposed on Si pores showing Ti and N concentration as a function of depth.
also be used. The unetched portions of the silicon substrate served as the current collectors for the two-electrode symmetric cells. Some of the dopants become deactivated in the P-Si due to defect states such as surface dangling bonds, so the P-Si has a lower conductivity compared to the unetched Si. Redoping of P-Si is a potential method to further improve its conductivity, but in this paper, conductive surface coatings were explored. Surface-area measurements using Brunauer–Emmett–Teller (BET) adsorption analysis shows an inverse relationship between pore diameter and surface-area density (see Fig. 4). A non-local density functional theory (NLDFT) model applicable for nitrogen adsorption at 77 °K in porous silica with a cylindrical-branched pore geometry [30, 31] was used. This model is valid for the pore sizes (0.35 to 100 nm) and type H1 sorption hysteresis observed. B. Surface Coatings This P-Si nanostructure was combined with an ionic liquid to create an electrochemical capacitor. Wafers etched with pores were diced into square electrodes with an area of 1 cm2. A conventional cell with a two- or three-electrode configuration was used for electrochemical characterization. Bare silicon is not stable over a long period of time due to unwanted reactions with the electrolyte [32], resulting in decreasing capacitance with cycling [13, 33]. Conductive, passivating and/or electrochemically active surface coatings such as ALD titanium nitride (TiN) (see Fig. 5) [12, 13, 34], pseudo-capacitive materials (e.g. VN, RuO2), SiC [35, 36], or carbon (see Fig. 6) [12, 37-39] were found necessary for long-term stability. Recent work by one of our coauthors [17] has since confirmed that coating P-Si with a graphene-like carbon deposited at high temperatures (over 650 °C) can reduce these unwanted reactions. The present study demonstrates that stability is also achievable at reduced deposition temperatures with ALD TiN enabling on-chip integration. Carbon and TiN coated samples were prepared using the same P-Si nanostructure enabling direct comparison of the coating materials. Double layer charge storage occurs at the surface of the TiN or carbon with the accessible surface area for the electrolyte still largely dependent on the P-Si acting as scaffolding. Carbonization of the P-Si was achieved using a two-step deposition process with a mixture of nitrogen and acetylene gas (1:1 N2 to C2H2) in a CVD furnace [37, 38]. The first step is based on the adsorption of acetylene into the hydrogen-terminated, oxide-free P-Si crystal matrix and uses a continuous acetylene flow while ramping to 500 °C. The hydrogen termination desorbs and is replaced by acetylene fragments forming a highly-stable thermally hydrocarbonized P-Si (THCPSi) that is hydrophobic. It effectively locks the structure and prevents the pores from rearranging. Graphitization of the acetylene occurs at temperatures above 650 °C, so after the material is brought back to room temperature, acetylene gas is discontinued and then the sample is ramped up to 720 °C in pure nitrogen gas (see [37-39] for details). Finally, the sample is allowed to cool back to room temperature under N2 gas flow and the surface becomes hydrophilic because the hydrocarbon termination gradually converts into silicon carbide [40]. Thermally carbonized P-Si (TCPSi) (see Fig. 6) with a high chemical stability even in basic solutions is obtained [37]. The hydrophilic nature of TCPSi is due to a thin oxide crust covering the outer surface on top of a nonstoichiometric SiC layer because carbon in SiC cannot itself terminate the surface. The pores are expected to be uniformly coated because acetylene is initially inserted at room temperature instead of at high temperature, so graphitization cannot block the pores and prevent uniform carbonization of the surfaces.
Fig. 8. XPS depth profile of ALD TiN deposited on a planar surface.
Fig. 7. TEM and TEM-EDS images of porous Si coated with ALD TiN. (a) TiN coatings can be seen on P-Si. Box shows region where EDS was taken. (b) HRTEM of TiN and Si. (c) TEM-EDS of Ti-K show TiN coatings.
The second technique for coating P-Si was stop-flow ALD of TiN. ALD of films in ultrahigh aspect ratio features (AR over 100:1) presents unique challenges. To obtain uniform coatings, efficient surface reactions are needed between high volatility, low molecular weight, small molecular diameter precursors without chemical vapor deposition side reactions [41, 42]. TiCl4 is among the best candidates because in addition to its high vapor pressure and moderately small molecular weight, it can be used to form conductive TiN without side reactions that might oxidize the silicon surface. In recent work on ALD TiN/Al 2O3/TiN metal-insulator-metal (MIM) capacitors in 30:1 AR trenches [43], a plasma-enhanced ALD TiN process was used. In the case of our higher aspect ratio P-Si substrates with torturous channels, the penetration of plasma-based coreactants would be very challenging dictating the use of purely thermal processing. In this work, the TiCl4 + NH3 ALD TiN process met these criteria and resulted in passivating conductive films. The SEM images in Fig. 5 show the top of the porous silicon before and after coating with ALD TiN. Unlike some ALD processes, this coating process did not seal closed the porous silicon. ALD reactor design also plays a critical role. Whereas the majority of ALD is in a continuous viscous flow reactor, a pseudo stop-flow ALD reactor was used to obtain uniform coatings to a 12 μm pore depth (see Fig. 7). To minimize native silicon oxide formation, samples were stored in a N2 atmosphere and then loaded directly into the vacuum system of the ALD reactor. The substrate was allowed higher-pressure extended precursor soak times with intervening pump-purge cycles to remove excess precursor along with reaction byproducts. The large open central regions needed in the pore structure for ion transport also aids in the coating process by enhancing precursor diffusion down the pores. A typical process consisted of TiCl 4 precursor soak for 5 seconds followed by N2 purge for 10 seconds and then NH3 soak for 5 seconds and a second purge for 10 seconds. Table I. Porous Si surface area reduction from TiN coating.
Coating Before ALD 2.5nm TiN 5 nm TiN 10 nm TiN
Surface area m2/cm3 241 210 168 113
Percent reduction — –13% –30% –53%
Fig. 9. Cyclic voltammetry using a three-terminal cell at 50 mV/s of uncoated porous silicon. The uncoated silicon is not stable after 100 cycles. Fig. 10. Three-terminal CV measurements at 10 mV/s of 5 m deep by ~50 nm wide pores (100:1 aspect ratio). The positive voltage is starting to show a slight degradation at +1.2 V whereas the negative voltage is stable. The electrochemical window is limited by the cathode to approximately 2.4 volts for a symmetrical device, but can be extended in the negative direction by creating an asymmetric device.
Materials Characterization Key characteristics of the bare and coated P-Si nanostructures (surface area, pore volume, and pore size distribution) and the effectiveness of the surface coatings were studied. SEM images were used to ensure fully open pores and to measure the tapered pore structures. ALD TiN films were first characterized on planar surfaces for conductivity, wettability, purity, and electrochemical stability. Penetration depth and chemical composition of the coatings were measured with energy-dispersive Xray spectroscopy (EDS). EDS depth profiling superimposed onto the SEM image shows that the Ti and N penetrate equally to the bottom of the 12 m deep pores (see Fig. 7). Surface area measurements of the optimized P-Si nanostructure using BET analysis showed that smaller pores etched at lower current densities resulted in larger surface areas (see Fig. 4). Larger pores with a smaller total surface area were obtained at higher current densities. Tapered pores fabricated by varying the current density during etching show higher surface areas than devices with large pores and lower surface area than devices with only small pores. Measurements of TiN coated samples showed that the surface area is reduced with increasing TiN thickness (see Table I). The reduction of surface area is due to the reduction of the pore diameter and the blockage/filling of pores with initial diameters less than twice the coating thickness. The thickness of the TiN after 300 ALD cycles in the pores is difficult to determine, but can be estimated using TiN mass and pore volume measurements. Calculations show it to be as low as an average of 2 nm for a 5 nm thickness on a planar surface. This lower deposition rate is likely due to limited precursor access of the high aspect ratio structures. Transmission electron microscopy (TEM) cross-sectional images of the porous silicon after ALD TiN shows evidence that the pore walls are coated with TiN (see Fig. 8). High-resolution TEM analysis within the pores (see Fig. 8b) show both crystalline TiN (200) with a lattice spacing of 2.25 Å and Si (311) with a larger lattice spacing of 3.15 Å. TEM-EDS measurements show the location of the Ti-K emission (see Fig. 8c) confirming that TiN is coating the pore walls.
Fig. 12. Comparison of CV measurements of two different TiN-coating thicknesses on porous silicon after electrically cycling 50 times at a rate of 10 mV/s. When only 200 ALD cycles are used, the structure is unstable.
X-ray photoelectron spectroscopy (XPS) was used to study the chemical composition of the TiN (see Fig. 9) on planar surfaces. The XPS depth profiling shows that the thick TiN films are nitrogen rich which is less reactive than titanium-rich TiN. Also the oxygen level was below 2 atomic percent and carbon was below 1 atomic percent in the bulk of this 30 nm film. The chlorine content was below the 0.5 atomic percent XPS detection limit. The surface energy of ionic liquid was also examined using liquid droplets to enhance electrolyte penetration and it was found that the best wettability was obtained on TiN [13]. Coating quality was characterized by measuring the electrochemical window of fabricated EC capacitors. Performance P-Si electrodes with and without TiN or carbon coatings were tested using cyclic voltammetry and impedance spectroscopy in a three-terminal measurement setup. The working electrode was one of the aforementioned P-Si electrodes, the reference electrode was platinum wire, and the counter electrode was either a platinum mesh or active carbon, which served as a current sink. Different ionic liquids were studied to determine the ionic liquid best suited to TiN coated porous Si including TEABF4/AN, EMI-BF4, EMI-Tf, and a 3 M EMI-BF4/propylene carbonate (PC) mixture. The highest capacitance density and energy density was obtained using EMI-BF4 and EMI-Tf [44]. In this study, all electrodes were immersed in EMI-BF4 electrolyte in a N2-filled glove box. To improve electrolyte penetration into the porous electrodes, the electrodes immersed in electrolyte were treated using a vacuum to remove air trapped in the pores.
a)
b)
Fig. 13. SEM images of ALD TiN coated porous silicon: a) 300 ALD cycles ALD that results in 5 nm of TiN on a flat silicon surface and b) 200 ALD cycles of TiN.
Fig. 11. Energy-dispersive X-ray spectroscopy of titanium K-line normalized to silicon K-line versus depth for 7 m deep pores with ~50 nm pore diameters (140:1 aspect ratios). Two different ALD TiN thicknesses were used to coat the P-Si. 300 ALD cycles result in 5 nm TiN on a flat silicon surface.
Fig. 14. CV measurements at 1 mV/s (slower than typically done) shows that (a) the larger 5 m deep by approximately 50 nm wide pores (100:1 aspect ratio) are stable after 50 cycles. b) An average 30 nm wide pores (166:1 aspect ratio) using the same ALD TiN process shows some degradation at 1 mV/s at the positive potential which is not seen at higher 10 mV/s rates.
As shown in Fig. 10, the cyclic voltammetry of an uncoated P-Si electrode in three different voltage ranges indicates irreversible redox reactions, in which case charges cannot be effectively stored on the electrode. The capacitance is quite low at lower voltages because of the formation of silicon dioxide. In contrast, the device coated with TiN or carbon can be stably cycled (with repeated overlapping curves), as can be seen for 50 cycles in Fig. 11. TiN coated P-Si electrode with 5 µm deep pores were cycled at 10 mV/s at increasing voltage windows to determine the electrochemical window. The TiN coated device curves are relatively rectangular with the measurement not changing from cycle to cycle. This indicates capacitive behavior with minimal faradic reactions in the range of −1.2 V to +1.2 V. The electrochemical response of the ALD TiN coatings on P-Si was further studied by changing the TiN coating thickness.
Fig. 15. Charge-discharge curve at a constant current using two-electrode devices for an ALD TiN coated 12 m deep P-Si and an uncoated 254 m deep P-Si electrochemical capacitor.
a)
b)
Fig. 17. Nyquist plot of the impedance spectroscopy of TiN coated 10 m deep P-Si. Insert shows that large pores result in the lowest effective series resistance and vice versa with the tapered structure having an ESR just below the largest pores.
c)
Fig. 16. Charge-Discharge of porous silicon (a) without and (b) with TiN coating on the porous silicon surface. (c) The capacitance is stable after long term cycling at 50 mV/s to 0.8 V which is within the electrochemical window for all the devices.
EDS depth profile measurements in Fig. 12 show that the ALD TiN effectively penetrated to the bottom of the 7 m deep pores (140:1 aspect ratio). The EDS depth profile also shows that with fewer cycles, less TiN material is deposited into the pores. Cyclic voltammetry measurements of these samples in Fig. 13 shows that thinning the TiN coating by reducing the number of ALD cycles from 300 to 200 results in the onset of irreversible redox reactions. The thicker TiN can be seen in SEM crosssection images with 300 ALD cycles versus 200 ALD cycles in Fig. 14. Smaller pores can be formed to further increase the surface area. Samples were prepared with an average pore size of 30 nm (166:1 aspect ratio) and coated with ALD TiN and then characterized (see Fig. 15). Three-terminal cyclic voltammetry at 1 mV/s (slower than typically done) showed that the larger ~50 nm pores continue to be stable in the range of −1.0 V to +1.0 V, but that the smaller 30 nm pores with TiN are starting to degrade at a potential of +1.0 V because of increased difficulties of obtaining a conformal TiN coating. The capacitance hence is actually reduced as seen in Fig. 15. Furthermore, due to a less conformal TiN coating, the ESR for electrodes with smaller pores increases and the CV curves start to deviate from a rectangular shape. TiN coated P-Si electrodes were also made into two terminal symmetric cells and tested using galvanostatic charging and discharging (see Fig. 16). A deep 254 m uncoated P-Si sample was prepared to examine the limits of pore depth and it exhibited poor charging characteristics because of irreversible chemical reactions resulting in only 3.4 mF/cm2 of capacitance.
Fig. 18. Bode plot comparing 2 m P-Si with and without ALD TiN coatings. The impedance was tested at open circuit potential.
Fig. 19. Capacitance vs. frequency of 2 m deep P-Si. Real capacitance C' shows the storage capability whereas the imaginary capacitance C" corresponds to energy dissipation by an irreversible process.
An ALD coated 12 m deep sample (21× shallower) exhibited nearly linear charging and discharging versus time using a constant current and exhibited an areal capacitance density of 28 mF/cm2. Additional two-terminal devices were assembled using uncoated, carbon-coated, and TiN-coated P-Si. The devices were then cycled 1,000 times. The capacitance is C = Q/V, where Q is obtained by integrating the discharge current of the cyclic voltammetry curves and normalizing to the volume of the P-Si. Capacitance dropped quickly after the first few cycles of bare P-Si from reactions (see Fig. 17) while that of TiN coated PSi increases during the first hundreds of cycles, a phenomenon known as conditioning. The conditioning process could be from a combination of two factors. First, pseudo-redox reactions from the existence of functional groups on the TiN surface may have a positive effect on the electrochemical performance. The fixed amount of functional groups and the limited reversibility of such reactions may limit the increase in capacitance to only the initial cycles [45, 46]. Second, electrochemical activation processes from the intercalation of ions and solvent into the small pores during polarization may also cause a capacitance gain [47]. After stabilization, the TiN coated P-Si has an areal capacitance of 3.1 mF/cm2 for 2 m deep pores after 1,000 cycles, 10× higher than bare P-Si and 3× more than the carbonized P-Si (see Fig. 17). The increased capacitance could arise in part from the TiN being involved in faradaic redox reactions [46], but aqueous electrolytes are not being used and this was not evident in the measurements. The volumetric capacitance for the TiN coated samples presented in this paper range from 30~60 F cm˗ 3 for a half cell, which is inside the range of 12~160 F cm˗ 3 that has been reported for carbon in non-aqueous electrolytes [48]. We conclude that despite the surface area of the coated P-Si being 5-10 times less than carbon, the volumetric capacitance is within the range because a higher fraction of the P-Si surface area is active in the EC capacitor. Impedance spectroscopy was also used to characterize the TiN coated 10 m deep P-Si with different pore morphologies. The effective series resistance (ESR) was found to correlate with the pore size with lower ESR corresponding to larger pores and vice
versa (see insert in Fig. 18). The ESR of tapered pores was found to be between that of the larger pores and mid-size pores. The knee in the impedance spectrum occurs at 0.6 Hz for these 10 m deep pores. The improvement from coatings can also be seen in the Bode plot showing impedance versus frequency (see Fig. 19). The impedance is lower for TiN-coated P-Si because of the conductive TiN layer. The time constant of the TiN coated 2 m deep PSi EC capacitor is 17.6 ms. Uncoated P-Si initially is faster, but it soon becomes too lossy after cycling to be measured. This time constant is shorter than the 1.3 second time constant associated with the impedance spectroscopy measurements for the deeper 10 m deep pores in Fig. 18 because the conductive path is longer and therefore more resistive in the deeper pores. The | | and the imaginary capacitance C"=Z' real capacitance C' | | are calculated and plotted in Fig. 20 where Z' and Z" represent the real and imaginary part of the electrochemical impedance respectively and represents the frequency. At lower frequencies, the capacitance of TiN/P-Si is 3~6 mF/cm2 for the 2 m deep pores, similar to that from CV measurements, whereas bare P-Si before cycling is only 0.4 mF/cm2 and degrades after cycling. A Ragone chart depicting the performance characteristics of the P-Si EC capacitors by plotting energy density (storage capacity) vs. power density (speed of charge and discharge) is shown in Fig. 21. The values are calculated by integrating the galvanostatic discharge curves for each device at various current densities and normalizing to the volume of the P-Si. Also included are the energy versus power densities of electrolytic capacitors and Li-ion batteries including thin film Li-batteries [49] although Li-ion batteries can only be recharged a few hundred times before having to be replaced. Using TiN coatings, volumetric energy densities of up to 9×10−3 Wh/cm3 were obtained which is over 800× higher than bare P-Si at 1 V and comparable to commercial carbon-based EC capacitors. This converts to a specific energy of 6 Wh/kg using the P-Si and electrolyte masses (not accounting for surface coatings and packaging). The energy density of TiN coated P-Si is less than bulk Li-ion batteries and is comparable to thin-film Li batteries, but with much higher power densities. Also, the energy density of TiN-coated P-Si is better than electrolytic capacitors. At power densities between 1 and 10 W/cm3, the TiN-coated P-Si electrochemical capacitors in Fig. 21 have two to three orders of magnitude more energy density than 3 V electrolytic capacitors making them suitable for applications such as solar or vibrational energy harvesting. In addition, they do not have the disadvantage of requiring frequent replacement as would be the case with Li-ion batteries. Conclusion Tapered P-Si nanostructures were characterized, optimized, passivated with TiN or carbon, and used with an ionic liquid electrolyte to form an electrochemical capacitor. Pseudo stop-flow ALD TiN was successfully used to coat the high aspect ratio structures. The energy density is increased by coating the P-Si with ALD TiN or carbon with ALD TiN producing the larger increase in energy density. The P-Si EC capacitors with carbon or TiN coatings both exhibited stable capacitance for over 1,000 cycles. Impedance testing showed that devices exhibited capacitive behavior (C' C") up to 60 Hz. The energy density of TiNcoated P-Si is one to three orders of magnitude higher than electrolytic capacitors and comparable to carbon-based EC capacitors. P-Si based EC capacitors are thus shown to have the potential to provide integrated on-chip energy storage.
Fig. 21. Ragone plot for performance comparison of volumetric power density versus energy density of TiN coated P-Si, carbonized P-Si (C P-Si), and bare P-Si as compared to Li-ion batteries and electrolytic capacitors. The values for P-Si are after 100 cycles at the indicated test voltage.
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Stengl, and A. Luigart, "On the morphology and the electrochemical formation mechanism of mesoporous silicon," Mat. Sci. & Engr. B, vol. B69-70, pp. 11-22, 2000. [25] M. J. Sailor, Porous Silicon In Practice: Preparation, Characterization And Applications: John Wiley & Sons, 2012. [26] L. Canham, Handbook of Porous Silicon: Springer, 2014. [27] Adv. Micromachining Tools, GmbH. Available: www.ammt.com [28] W. Henrion, M. Rebien, H. Angermann, and A. Röseler, "Spectroscopic investigations of hydrogen termination, oxide coverage, roughness, and surface state density of silicon during native oxidation in air," Applied Surface Science, vol. 202, pp. 199-205, 12/30/ 2002. [29] H. Angermann, W. Henrion, M. Rebien, and A. Röseler, "Wet-chemical preparation and spectroscopic characterization of Si interfaces," Applied Surface Science, vol. 235, pp. 322-339, 8/15/ 2004. [30] P. I. Ravikovitch and A. V. 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Highlights
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Porous silicon provides high surface areas suitable for electrochemical capacitors.
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Stacked Si die with coated porous Si layers enable integrated energy storage.
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The nanopore morphology and coatings are optimized for maximizing energy density.
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Coating the silicon improves conductivity, stability, and capacitance.
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Stop-flow ALD TiN is effective at coating high-aspect-ratio nanostructures (>100:1).
Graphical abstract
PII: DOI: Reference:
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S2211-2855(16)30074-X http://dx.doi.org/10.1016/j.nanoen.2016.04.016 NANOEN1221
To appear in: Nano Energy Received date: 13 September 2015 Revised date: 26 February 2016 Accepted date: 13 April 2016 Cite this article as: D.S. Gardner, C.W. Holzwarth, Y. Liu, S.B. Clendenning, W. Jin, B.K. Moon, C. Pint, Z. Chen, E. Hannah, C. Chen, C.P. Wang, E. Mäkilä, R. Chen, T. Aldridge and J.L. Gustafson, Integrated On-Chip Energy Storage Using Passivated Nanoporous-Silicon Electrochemical Capacitors, Nano Energy, http://dx.doi.org/10.1016/j.nanoen.2016.04.016 This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting galley proof before it is published in its final citable form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
Integrated On-Chip Energy Storage Using Passivated Nanoporous-Silicon Electrochemical Capacitors D. S. Gardnera, C. W. Holzwarth IIIa, Y. Liua, S. B. Clendenninga, W. Jina, B. K. Moona, C. Pinta, Z. Chena, E. Hannaha, C. Chenb, C. P. Wangb, E. Mäkiläc, R. Chena, T. Aldridgea, and J. L. Gustafsona a
Intel Corp., 3065 Bowers Ave., Santa Clara, CA 95052 USA Florida Intl. University, Dept. of Mech. and Materials Engr., 10555 W Flagler St., Miami, FL 33174 USA c University of Turku, Dept. of Physics and Astronomy, FI-20500, Finland Email: [email protected]
b
Fig. 1. Stack of P-Si substrates with electronic circuitry on the top substrate. Abstract
Integrated on-chip energy storage is increasingly important in the fields of internet of things, energy harvesting, sensing, and wearables; capacitors being ideal for devices requiring higher powers or many thousands of cycles. This work demonstrates electrochemical capacitors fabricated using an electrolyte and porous silicon nanostructures with very high surface-to-volume ratios. Nanopore morphologies and passivation coatings for maximizing energy and power densities of porous-silicon based electrochemical capacitors are studied. Stability is achieved through atomic layer deposition (ALD) titanium nitride or chemical vapor deposition (CVD) carbon coatings. The use of silicon processing methods creates the potential for on-chip energy storage. Keywords Porous silicon, atomic layer deposition, carbonization, electrochemical capacitors
Introduction With the emergence of the Internet of Things (IoT), over 50 billion connected devices are expected by 2020 [1, 2]. New types of devices are being invented continuously, each with their own unique power requirements. Many of these devices are not connected to the power grid: wireless sensors, health monitors, wearables, etc., and require integrated energy storage and/or energy harvesting capability. The typical power profile for these types of devices is very low power during standby and data collection with a significantly higher peak power needed for data transmission. The low power modes can be supported by an energy-harvesting device; however, for the high power modes, an electrochemical (EC) capacitor is an ideal candidate. EC capacitors outperform batteries for these types of devices since they can capture energy at high rates and at lower voltages than batteries as well as provide higher peak power. Although the energy density for EC capacitors is significantly less (~20×) than batteries, when paired with an energy harvester, the important figure of merit is lifetime energy density (energy density × cycle lifetime). Unlike batteries, EC capacitors are electrostatic devices and do not rely on chemical reactions to store energy. This enables them to achieve higher cycle lifetimes of many thousands of times, easily compensating for their lower energy density. This is especially true for the billions of off-power-grid IoT devices where it is not possible to regularly replace the batteries. Silicon is already the material of choice for the integrated circuits found in every IoT device. Fig. 1. Charge-discharge measurement While there are numerous research efforts to integrate energy harvesting devices on-chip, the of a stack of P-Si such as in Fig. 1.
Fig. 2. Tapered porous silicon nanostructure created by changing the current density during etching. The tapered profile (in blue) can be optimized for desired device performance (e.g. faster speed or higher capacitance).
effort to integrate EC capacitors on a silicon die has to date been limited. Typically EC electrodes are comprised of high surface area carbon micro-particles, but due to possible contamination and electrical shorting when processing with conductive particles, a particle based electrode is not a good candidate for an integrated solution. A potentially better choice is high-surface area porous silicon nanostructures as the electrode material (see Figs. 1 and 2). Silicon nanostructures have already been used extensively as battery anodes in the form of nanowires [3], nanotubes [4], nanoporous particles [5, 6], and (macro-, meso-, nano-) porous silicon (P-Si) films [7-9]. Also, hybrid EC capacitors using carbon-coated Si/SiO2 particles as an anode have been demonstrated [10]. However, the few publications regarding porous silicon as an electrode material for EC capacitors have either required high temperature processes incompatible with on-chip integration or macroporous silicon (pores diameters larger than 50 nm) which limits the surface area and therefore the overall achievable performance. This paper presents EC capacitors based on P-Si nanostructures with highly branched pores coated with atomic layer deposited (ALD) films (see Fig. 3). The main pore diameter is tapered from 100 to 20 nm; the majority of the surface area comes from the branching structure along the pore walls consisting of nanopores in the 5 to 15 nm range. P-Si has poor conductivity as well as poor chemical and mechanical stability because the silicon surface can easily oxidize. Consequently, the energy density of P-Si coated with a conductive passivation film is significantly higher. Measurements of coated P-Si capacitors reveal that an areal capacitance of 3 to 6 mF/cm2 can be achieved using 2 m deep pores and the capacitance scaled approximately linearly with depth with 28 mF/cm2 measured for 12 m deep pores [11-14]. These results are one to two orders of magnitude higher than the other studies utilizing P-Si [15-18]. These devices were fabricated using silicon process methods with the potential for on-chip integration. The pores can be formed in localized regions on the front side or on the backside, utilizing the bulk Si, of a silicon die containing integrated circuits and a kinetic or solar energy harvesting device such as a silicon solar cell [19]. The EC capacitors can be integrated into silicon chips and used as a micro-supercapacitor for energy storage in several different ways. Pores can be patterned into localized regions of silicon and then a coating can be applied to form the second electrode or pores can be formed in a side-by-side planar design. In addition, pores can be formed on the backsides of two silicon die and stacked to form an EC, optionally pores can be formed on both sides of silicon die creating a double-sided substrate and then inserted into the stack creating the configuration shown in Fig. 1. The porous volume and space between P-Si electrodes is filled with a liquid or preferably solid electrolyte [20]. Solid-state electrolyte alternatives include gel-polymer electrolytes [21, 22] and ionic-liquid based gelled electrolytes called ionogels [22, 23]. The series resistance can be minimized by using thin highly-doped silicon substrates. The stacked P-Si structure has the advantage of being a thin form factor with minimal impact on the area available for circuits. Additionally, it is relatively easy to manufacture, building off of die stacking technologies already developed for 3D integrated circuits. The measurements from a stack of silicon dies in Fig. 2 shows a charge-discharge cycle to 5 volts. In this configuration, there are two EC capacitors in series resulting in a doubling of the operating voltage and areal energy (volumetric energy remains the same). This can provide localized low-energy storage such as that needed for integrated sensors. Experimental
Fig. 5. Cross sectional images of carbonized P-Si created at 500 °C through reaction with acetylene followed by a second ramp up to 720 °C (see [8, 10] for details).
Fig. 4. SEM images of top of porous region (left) before and (right) after stop-flow ALD TiN deposition. The pore walls become thicker but the overall pore structure does not change.
To maximize the performance of P-Si electrochemical capacitors, it is important to optimize the pore structure and surface properties. The pore structure can be characterized with five interdependent parameters: pore size, surface area, porosity, depth, and morphology; likewise, the surface properties can be characterized by chemical stability, conductivity and wettability. A. Porous-Silicon Nanostructure The following properties control the performance of the electrochemical capacitor: capacitance, operating voltage, cycle lifetime, and operating frequency. The total surface area needs to be high to obtain large capacitance which requires small pore diameters and deep etch depths that create high-aspect-ratio features. The high-aspect ratios can lead to high effective series resistance (ESR) because of the long path that ionic charge carriers have to traverse. Contrariwise for high operating frequency, large pore diameters are preferred for fast ion transport. For optimal performance, a pore structure with an open central channel (fast transport) and many smaller pores branching out along the sidewall (high surface area) is desired. The need for the central open channel diminishes the closer one gets to the bottom of the porous layer favoring smaller highly-branched pores. In an effort to create this optimal structure, a tapered-pore nanostructure with main channel sizes tapering from 100 nm to 20 nm and with the degree of branching increasing with depth (see Fig. 3) was developed to deliver extremely high surface-to-volume ratios. Electrochemical etching using hydrofluoric acid and isopropyl alcohol (2:1 HF:IPA) was employed [24] to etch the P-Si nanostructures with depths of up to 250 m and a porosity of ~75%. IPA was added to reduce the hydrogen gas generation and improve the homogeneity of P-Si [25, 26]. The etching apparatus is a double tank electrochemical cell for 4 inch Si wafers developed by AMMT [27]. The electrical symmetry of this cell with front side and backside contact via the HF:IPA etchant, allows for double sided P-Si fabrication by simply reversing the current direction. Highly doped (100) p-type silicon (0.01 to 0.001 -cm) was chosen because it provides good electrode conductivity. Depending on the current density used, wide smoother-walled pores or narrow highly-branched pores can be achieved. Silicon with less dopant can be used, but process parameters (current density, HF concentration, temperature, etc.) need to be adjusted appropriately to obtain similar structures [25, 26]. As part of the etching procedure, a sacrificial layer process is used to ensure fully open pores; it consists of a high current density etch followed by a KOH strip before the P-Si etch process. This proved to be essential for ALD coating penetration and for device operation at higher power densities. After etching, native silicon oxide 0.1 nm to 0.2 nm thick can form in air within 1 hour on the freshly etched silicon surfaces [28, 29]. This would result in a significant capacitance drop, so samples were stored in a nitrogen ambient soon after etching. It should be noted that although the anodization process is a simple method for synthesizing P-Si, dry etching processes (such as: deep reactive-ion etching) could
Fig. 3. Pore size distribution from BET adsorption analysis of three different etching current densities demonstrating the inverse relationship between pore diameter and surface-area density.
Fig. 6. SEM cross sectional image with an EDS depth profile of Ti and N concentrations superimposed on Si pores showing Ti and N concentration as a function of depth.
also be used. The unetched portions of the silicon substrate served as the current collectors for the two-electrode symmetric cells. Some of the dopants become deactivated in the P-Si due to defect states such as surface dangling bonds, so the P-Si has a lower conductivity compared to the unetched Si. Redoping of P-Si is a potential method to further improve its conductivity, but in this paper, conductive surface coatings were explored. Surface-area measurements using Brunauer–Emmett–Teller (BET) adsorption analysis shows an inverse relationship between pore diameter and surface-area density (see Fig. 4). A non-local density functional theory (NLDFT) model applicable for nitrogen adsorption at 77 °K in porous silica with a cylindrical-branched pore geometry [30, 31] was used. This model is valid for the pore sizes (0.35 to 100 nm) and type H1 sorption hysteresis observed. B. Surface Coatings This P-Si nanostructure was combined with an ionic liquid to create an electrochemical capacitor. Wafers etched with pores were diced into square electrodes with an area of 1 cm2. A conventional cell with a two- or three-electrode configuration was used for electrochemical characterization. Bare silicon is not stable over a long period of time due to unwanted reactions with the electrolyte [32], resulting in decreasing capacitance with cycling [13, 33]. Conductive, passivating and/or electrochemically active surface coatings such as ALD titanium nitride (TiN) (see Fig. 5) [12, 13, 34], pseudo-capacitive materials (e.g. VN, RuO2), SiC [35, 36], or carbon (see Fig. 6) [12, 37-39] were found necessary for long-term stability. Recent work by one of our coauthors [17] has since confirmed that coating P-Si with a graphene-like carbon deposited at high temperatures (over 650 °C) can reduce these unwanted reactions. The present study demonstrates that stability is also achievable at reduced deposition temperatures with ALD TiN enabling on-chip integration. Carbon and TiN coated samples were prepared using the same P-Si nanostructure enabling direct comparison of the coating materials. Double layer charge storage occurs at the surface of the TiN or carbon with the accessible surface area for the electrolyte still largely dependent on the P-Si acting as scaffolding. Carbonization of the P-Si was achieved using a two-step deposition process with a mixture of nitrogen and acetylene gas (1:1 N2 to C2H2) in a CVD furnace [37, 38]. The first step is based on the adsorption of acetylene into the hydrogen-terminated, oxide-free P-Si crystal matrix and uses a continuous acetylene flow while ramping to 500 °C. The hydrogen termination desorbs and is replaced by acetylene fragments forming a highly-stable thermally hydrocarbonized P-Si (THCPSi) that is hydrophobic. It effectively locks the structure and prevents the pores from rearranging. Graphitization of the acetylene occurs at temperatures above 650 °C, so after the material is brought back to room temperature, acetylene gas is discontinued and then the sample is ramped up to 720 °C in pure nitrogen gas (see [37-39] for details). Finally, the sample is allowed to cool back to room temperature under N2 gas flow and the surface becomes hydrophilic because the hydrocarbon termination gradually converts into silicon carbide [40]. Thermally carbonized P-Si (TCPSi) (see Fig. 6) with a high chemical stability even in basic solutions is obtained [37]. The hydrophilic nature of TCPSi is due to a thin oxide crust covering the outer surface on top of a nonstoichiometric SiC layer because carbon in SiC cannot itself terminate the surface. The pores are expected to be uniformly coated because acetylene is initially inserted at room temperature instead of at high temperature, so graphitization cannot block the pores and prevent uniform carbonization of the surfaces.
Fig. 8. XPS depth profile of ALD TiN deposited on a planar surface.
Fig. 7. TEM and TEM-EDS images of porous Si coated with ALD TiN. (a) TiN coatings can be seen on P-Si. Box shows region where EDS was taken. (b) HRTEM of TiN and Si. (c) TEM-EDS of Ti-K show TiN coatings.
The second technique for coating P-Si was stop-flow ALD of TiN. ALD of films in ultrahigh aspect ratio features (AR over 100:1) presents unique challenges. To obtain uniform coatings, efficient surface reactions are needed between high volatility, low molecular weight, small molecular diameter precursors without chemical vapor deposition side reactions [41, 42]. TiCl4 is among the best candidates because in addition to its high vapor pressure and moderately small molecular weight, it can be used to form conductive TiN without side reactions that might oxidize the silicon surface. In recent work on ALD TiN/Al 2O3/TiN metal-insulator-metal (MIM) capacitors in 30:1 AR trenches [43], a plasma-enhanced ALD TiN process was used. In the case of our higher aspect ratio P-Si substrates with torturous channels, the penetration of plasma-based coreactants would be very challenging dictating the use of purely thermal processing. In this work, the TiCl4 + NH3 ALD TiN process met these criteria and resulted in passivating conductive films. The SEM images in Fig. 5 show the top of the porous silicon before and after coating with ALD TiN. Unlike some ALD processes, this coating process did not seal closed the porous silicon. ALD reactor design also plays a critical role. Whereas the majority of ALD is in a continuous viscous flow reactor, a pseudo stop-flow ALD reactor was used to obtain uniform coatings to a 12 μm pore depth (see Fig. 7). To minimize native silicon oxide formation, samples were stored in a N2 atmosphere and then loaded directly into the vacuum system of the ALD reactor. The substrate was allowed higher-pressure extended precursor soak times with intervening pump-purge cycles to remove excess precursor along with reaction byproducts. The large open central regions needed in the pore structure for ion transport also aids in the coating process by enhancing precursor diffusion down the pores. A typical process consisted of TiCl 4 precursor soak for 5 seconds followed by N2 purge for 10 seconds and then NH3 soak for 5 seconds and a second purge for 10 seconds. Table I. Porous Si surface area reduction from TiN coating.
Coating Before ALD 2.5nm TiN 5 nm TiN 10 nm TiN
Surface area m2/cm3 241 210 168 113
Percent reduction — –13% –30% –53%
Fig. 9. Cyclic voltammetry using a three-terminal cell at 50 mV/s of uncoated porous silicon. The uncoated silicon is not stable after 100 cycles. Fig. 10. Three-terminal CV measurements at 10 mV/s of 5 m deep by ~50 nm wide pores (100:1 aspect ratio). The positive voltage is starting to show a slight degradation at +1.2 V whereas the negative voltage is stable. The electrochemical window is limited by the cathode to approximately 2.4 volts for a symmetrical device, but can be extended in the negative direction by creating an asymmetric device.
Materials Characterization Key characteristics of the bare and coated P-Si nanostructures (surface area, pore volume, and pore size distribution) and the effectiveness of the surface coatings were studied. SEM images were used to ensure fully open pores and to measure the tapered pore structures. ALD TiN films were first characterized on planar surfaces for conductivity, wettability, purity, and electrochemical stability. Penetration depth and chemical composition of the coatings were measured with energy-dispersive Xray spectroscopy (EDS). EDS depth profiling superimposed onto the SEM image shows that the Ti and N penetrate equally to the bottom of the 12 m deep pores (see Fig. 7). Surface area measurements of the optimized P-Si nanostructure using BET analysis showed that smaller pores etched at lower current densities resulted in larger surface areas (see Fig. 4). Larger pores with a smaller total surface area were obtained at higher current densities. Tapered pores fabricated by varying the current density during etching show higher surface areas than devices with large pores and lower surface area than devices with only small pores. Measurements of TiN coated samples showed that the surface area is reduced with increasing TiN thickness (see Table I). The reduction of surface area is due to the reduction of the pore diameter and the blockage/filling of pores with initial diameters less than twice the coating thickness. The thickness of the TiN after 300 ALD cycles in the pores is difficult to determine, but can be estimated using TiN mass and pore volume measurements. Calculations show it to be as low as an average of 2 nm for a 5 nm thickness on a planar surface. This lower deposition rate is likely due to limited precursor access of the high aspect ratio structures. Transmission electron microscopy (TEM) cross-sectional images of the porous silicon after ALD TiN shows evidence that the pore walls are coated with TiN (see Fig. 8). High-resolution TEM analysis within the pores (see Fig. 8b) show both crystalline TiN (200) with a lattice spacing of 2.25 Å and Si (311) with a larger lattice spacing of 3.15 Å. TEM-EDS measurements show the location of the Ti-K emission (see Fig. 8c) confirming that TiN is coating the pore walls.
Fig. 12. Comparison of CV measurements of two different TiN-coating thicknesses on porous silicon after electrically cycling 50 times at a rate of 10 mV/s. When only 200 ALD cycles are used, the structure is unstable.
X-ray photoelectron spectroscopy (XPS) was used to study the chemical composition of the TiN (see Fig. 9) on planar surfaces. The XPS depth profiling shows that the thick TiN films are nitrogen rich which is less reactive than titanium-rich TiN. Also the oxygen level was below 2 atomic percent and carbon was below 1 atomic percent in the bulk of this 30 nm film. The chlorine content was below the 0.5 atomic percent XPS detection limit. The surface energy of ionic liquid was also examined using liquid droplets to enhance electrolyte penetration and it was found that the best wettability was obtained on TiN [13]. Coating quality was characterized by measuring the electrochemical window of fabricated EC capacitors. Performance P-Si electrodes with and without TiN or carbon coatings were tested using cyclic voltammetry and impedance spectroscopy in a three-terminal measurement setup. The working electrode was one of the aforementioned P-Si electrodes, the reference electrode was platinum wire, and the counter electrode was either a platinum mesh or active carbon, which served as a current sink. Different ionic liquids were studied to determine the ionic liquid best suited to TiN coated porous Si including TEABF4/AN, EMI-BF4, EMI-Tf, and a 3 M EMI-BF4/propylene carbonate (PC) mixture. The highest capacitance density and energy density was obtained using EMI-BF4 and EMI-Tf [44]. In this study, all electrodes were immersed in EMI-BF4 electrolyte in a N2-filled glove box. To improve electrolyte penetration into the porous electrodes, the electrodes immersed in electrolyte were treated using a vacuum to remove air trapped in the pores.
a)
b)
Fig. 13. SEM images of ALD TiN coated porous silicon: a) 300 ALD cycles ALD that results in 5 nm of TiN on a flat silicon surface and b) 200 ALD cycles of TiN.
Fig. 11. Energy-dispersive X-ray spectroscopy of titanium K-line normalized to silicon K-line versus depth for 7 m deep pores with ~50 nm pore diameters (140:1 aspect ratios). Two different ALD TiN thicknesses were used to coat the P-Si. 300 ALD cycles result in 5 nm TiN on a flat silicon surface.
Fig. 14. CV measurements at 1 mV/s (slower than typically done) shows that (a) the larger 5 m deep by approximately 50 nm wide pores (100:1 aspect ratio) are stable after 50 cycles. b) An average 30 nm wide pores (166:1 aspect ratio) using the same ALD TiN process shows some degradation at 1 mV/s at the positive potential which is not seen at higher 10 mV/s rates.
As shown in Fig. 10, the cyclic voltammetry of an uncoated P-Si electrode in three different voltage ranges indicates irreversible redox reactions, in which case charges cannot be effectively stored on the electrode. The capacitance is quite low at lower voltages because of the formation of silicon dioxide. In contrast, the device coated with TiN or carbon can be stably cycled (with repeated overlapping curves), as can be seen for 50 cycles in Fig. 11. TiN coated P-Si electrode with 5 µm deep pores were cycled at 10 mV/s at increasing voltage windows to determine the electrochemical window. The TiN coated device curves are relatively rectangular with the measurement not changing from cycle to cycle. This indicates capacitive behavior with minimal faradic reactions in the range of −1.2 V to +1.2 V. The electrochemical response of the ALD TiN coatings on P-Si was further studied by changing the TiN coating thickness.
Fig. 15. Charge-discharge curve at a constant current using two-electrode devices for an ALD TiN coated 12 m deep P-Si and an uncoated 254 m deep P-Si electrochemical capacitor.
a)
b)
Fig. 17. Nyquist plot of the impedance spectroscopy of TiN coated 10 m deep P-Si. Insert shows that large pores result in the lowest effective series resistance and vice versa with the tapered structure having an ESR just below the largest pores.
c)
Fig. 16. Charge-Discharge of porous silicon (a) without and (b) with TiN coating on the porous silicon surface. (c) The capacitance is stable after long term cycling at 50 mV/s to 0.8 V which is within the electrochemical window for all the devices.
EDS depth profile measurements in Fig. 12 show that the ALD TiN effectively penetrated to the bottom of the 7 m deep pores (140:1 aspect ratio). The EDS depth profile also shows that with fewer cycles, less TiN material is deposited into the pores. Cyclic voltammetry measurements of these samples in Fig. 13 shows that thinning the TiN coating by reducing the number of ALD cycles from 300 to 200 results in the onset of irreversible redox reactions. The thicker TiN can be seen in SEM crosssection images with 300 ALD cycles versus 200 ALD cycles in Fig. 14. Smaller pores can be formed to further increase the surface area. Samples were prepared with an average pore size of 30 nm (166:1 aspect ratio) and coated with ALD TiN and then characterized (see Fig. 15). Three-terminal cyclic voltammetry at 1 mV/s (slower than typically done) showed that the larger ~50 nm pores continue to be stable in the range of −1.0 V to +1.0 V, but that the smaller 30 nm pores with TiN are starting to degrade at a potential of +1.0 V because of increased difficulties of obtaining a conformal TiN coating. The capacitance hence is actually reduced as seen in Fig. 15. Furthermore, due to a less conformal TiN coating, the ESR for electrodes with smaller pores increases and the CV curves start to deviate from a rectangular shape. TiN coated P-Si electrodes were also made into two terminal symmetric cells and tested using galvanostatic charging and discharging (see Fig. 16). A deep 254 m uncoated P-Si sample was prepared to examine the limits of pore depth and it exhibited poor charging characteristics because of irreversible chemical reactions resulting in only 3.4 mF/cm2 of capacitance.
Fig. 18. Bode plot comparing 2 m P-Si with and without ALD TiN coatings. The impedance was tested at open circuit potential.
Fig. 19. Capacitance vs. frequency of 2 m deep P-Si. Real capacitance C' shows the storage capability whereas the imaginary capacitance C" corresponds to energy dissipation by an irreversible process.
An ALD coated 12 m deep sample (21× shallower) exhibited nearly linear charging and discharging versus time using a constant current and exhibited an areal capacitance density of 28 mF/cm2. Additional two-terminal devices were assembled using uncoated, carbon-coated, and TiN-coated P-Si. The devices were then cycled 1,000 times. The capacitance is C = Q/V, where Q is obtained by integrating the discharge current of the cyclic voltammetry curves and normalizing to the volume of the P-Si. Capacitance dropped quickly after the first few cycles of bare P-Si from reactions (see Fig. 17) while that of TiN coated PSi increases during the first hundreds of cycles, a phenomenon known as conditioning. The conditioning process could be from a combination of two factors. First, pseudo-redox reactions from the existence of functional groups on the TiN surface may have a positive effect on the electrochemical performance. The fixed amount of functional groups and the limited reversibility of such reactions may limit the increase in capacitance to only the initial cycles [45, 46]. Second, electrochemical activation processes from the intercalation of ions and solvent into the small pores during polarization may also cause a capacitance gain [47]. After stabilization, the TiN coated P-Si has an areal capacitance of 3.1 mF/cm2 for 2 m deep pores after 1,000 cycles, 10× higher than bare P-Si and 3× more than the carbonized P-Si (see Fig. 17). The increased capacitance could arise in part from the TiN being involved in faradaic redox reactions [46], but aqueous electrolytes are not being used and this was not evident in the measurements. The volumetric capacitance for the TiN coated samples presented in this paper range from 30~60 F cm˗ 3 for a half cell, which is inside the range of 12~160 F cm˗ 3 that has been reported for carbon in non-aqueous electrolytes [48]. We conclude that despite the surface area of the coated P-Si being 5-10 times less than carbon, the volumetric capacitance is within the range because a higher fraction of the P-Si surface area is active in the EC capacitor. Impedance spectroscopy was also used to characterize the TiN coated 10 m deep P-Si with different pore morphologies. The effective series resistance (ESR) was found to correlate with the pore size with lower ESR corresponding to larger pores and vice
versa (see insert in Fig. 18). The ESR of tapered pores was found to be between that of the larger pores and mid-size pores. The knee in the impedance spectrum occurs at 0.6 Hz for these 10 m deep pores. The improvement from coatings can also be seen in the Bode plot showing impedance versus frequency (see Fig. 19). The impedance is lower for TiN-coated P-Si because of the conductive TiN layer. The time constant of the TiN coated 2 m deep PSi EC capacitor is 17.6 ms. Uncoated P-Si initially is faster, but it soon becomes too lossy after cycling to be measured. This time constant is shorter than the 1.3 second time constant associated with the impedance spectroscopy measurements for the deeper 10 m deep pores in Fig. 18 because the conductive path is longer and therefore more resistive in the deeper pores. The | | and the imaginary capacitance C"=Z' real capacitance C' | | are calculated and plotted in Fig. 20 where Z' and Z" represent the real and imaginary part of the electrochemical impedance respectively and represents the frequency. At lower frequencies, the capacitance of TiN/P-Si is 3~6 mF/cm2 for the 2 m deep pores, similar to that from CV measurements, whereas bare P-Si before cycling is only 0.4 mF/cm2 and degrades after cycling. A Ragone chart depicting the performance characteristics of the P-Si EC capacitors by plotting energy density (storage capacity) vs. power density (speed of charge and discharge) is shown in Fig. 21. The values are calculated by integrating the galvanostatic discharge curves for each device at various current densities and normalizing to the volume of the P-Si. Also included are the energy versus power densities of electrolytic capacitors and Li-ion batteries including thin film Li-batteries [49] although Li-ion batteries can only be recharged a few hundred times before having to be replaced. Using TiN coatings, volumetric energy densities of up to 9×10−3 Wh/cm3 were obtained which is over 800× higher than bare P-Si at 1 V and comparable to commercial carbon-based EC capacitors. This converts to a specific energy of 6 Wh/kg using the P-Si and electrolyte masses (not accounting for surface coatings and packaging). The energy density of TiN coated P-Si is less than bulk Li-ion batteries and is comparable to thin-film Li batteries, but with much higher power densities. Also, the energy density of TiN-coated P-Si is better than electrolytic capacitors. At power densities between 1 and 10 W/cm3, the TiN-coated P-Si electrochemical capacitors in Fig. 21 have two to three orders of magnitude more energy density than 3 V electrolytic capacitors making them suitable for applications such as solar or vibrational energy harvesting. In addition, they do not have the disadvantage of requiring frequent replacement as would be the case with Li-ion batteries. Conclusion Tapered P-Si nanostructures were characterized, optimized, passivated with TiN or carbon, and used with an ionic liquid electrolyte to form an electrochemical capacitor. Pseudo stop-flow ALD TiN was successfully used to coat the high aspect ratio structures. The energy density is increased by coating the P-Si with ALD TiN or carbon with ALD TiN producing the larger increase in energy density. The P-Si EC capacitors with carbon or TiN coatings both exhibited stable capacitance for over 1,000 cycles. Impedance testing showed that devices exhibited capacitive behavior (C' C") up to 60 Hz. The energy density of TiNcoated P-Si is one to three orders of magnitude higher than electrolytic capacitors and comparable to carbon-based EC capacitors. P-Si based EC capacitors are thus shown to have the potential to provide integrated on-chip energy storage.
Fig. 21. Ragone plot for performance comparison of volumetric power density versus energy density of TiN coated P-Si, carbonized P-Si (C P-Si), and bare P-Si as compared to Li-ion batteries and electrolytic capacitors. The values for P-Si are after 100 cycles at the indicated test voltage.
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Highlights
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Porous silicon provides high surface areas suitable for electrochemical capacitors.
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Stacked Si die with coated porous Si layers enable integrated energy storage.
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The nanopore morphology and coatings are optimized for maximizing energy density.
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Coating the silicon improves conductivity, stability, and capacitance.
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Stop-flow ALD TiN is effective at coating high-aspect-ratio nanostructures (>100:1).
Graphical abstract