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Integrating systolic arrays into a supersystem
Microprocessors An advanced DSP systolic-array architecture S B LEELAND (Motorola Inc., Chandler, AZ, USA) Computer (USA), vol. 20, no. 7, pp. 95-96 (July 1987) An advanced digital signal processing systolic-array architecture currently under development is described. Aspects of the architecture that give improved performance are examined. Architecture simulations have reconfirmed that the design performs best on algorithms with strong locality of signal flow. (4 refs.)
The systolic/cellular system for signal processing J G N A S H , K W PRYZTULA, S HANSEN (Hughes Res. Labs., Malibu, CA, USA) Computer (USA), vol. 20, no. 7, pp. 96-97 (July 1987) A description is given of a systolic/cellular system for large classes of linear algebraic and cellular operations. It consists of a host and a programmable coprocessor. The latter includes an array of 16 • 16 mesh-connected processors, dual-port array memory, and a controller with a separate program memory. The input data and the programs for the coprocessor are loaded from the host into the array memory and the program memory, respectively. The system can operate into two modes: cellular and systolic. Maximum system performance as in the neighbourhood of 450 million operations per second. (4 refs.)
P-NAC: a systolic array for comparing nucleic acid sequences D P LOPRESTI (Dept. ofComput. Sci., Brown Univ., Providence, RI, USA) Computer (USA), vol. 20, no. 7, pp. 98-99 (July 1987) A description is given of the Princeton Nucleic Acid Comparator (P-NAC), a linear systolic array for comparing DNA sequences. The architecture is a parallel realisation of a standard dynamic programming algorithm. Benchmark timings of a NMOS VLSI implementation confirm that for its dedicated application, P-NAC is two orders of magnitude faster than current microcomputers. Experience with the prototype is shaping the design of a second-generation device, to be known as the Brown Nucleic Acid Comparator (B-NAC), that will be algorithmically flexible and more tolerant of fabrication faults. (2 refs.)
Integrating systolic arrays into a supersystem W LIN, S CHIN, C HO (General Electric Co., Schenectady, NY, USA) Computer (USA), vol. 20, no. 7, pp. 100-101 (July 1987) A reconfigurable two-dimensional processor array is proposed that is a tradeoff between large-grain vector machines and small-grain, pure systolic arrays. The advantages are fourfold. The advantages of this approach are outlined, and the architecture is described. (2 refs.)
The concept and implementation of data-driven processor arrays I KOREN (Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA), I PELED Computer (USA), vol. 20, no. 7, pp. 102-103 (July 1987) The architecture and principles of a flexible VLSI array that would allow the generation of new computation fronts and their cancellation at a later time are described. The order in which instructions are executed is data-dependent, so each processing element is truly data-driven. It is shown that it is feasible to map an arbitrary algorithm onto such an array. (5 refs.) Application ofa convolver chip to anti-aliasing computergenerated images T W ROWLEY (Hirts Res. Centre, GEC Res., Wembley, England) Disp. Technol. &Appl. (GB), vol. 8, no. 3, pp. 147-150 (July 1987) Aliasing artefact may be reduced or removed from computer-generated images by using convolution filtering. The causes of aliasing artefacts are examined, the use of convolution filters for their removal or reduction is proposed and the application of the MA7180 convolver chip for this purpose is explored. Examples of particular filter configurations are used to illustrate possible applications to computer-generated image data streams. Functional self test in microprocessor systems G C BACCOLINI, C OFFELLI (Inst. of Electrotech. & Electron., Padova Univ., Italy) Conference Proceedings, IEEE Instrumentation and Measurement Technology ~ Conference (Cat. No. 87CH2405-9), Boston, MA, USA, 27-29 April 1987 (New York, USA: IEEE 1987), pp. 321-325 A high fault coverage self-test procedure used in microprocessor systems is described. It is based on a bus test program, which works in such a way that a bus fault entraps it in a situation that can be either an infinite loop or a jump to a location different from the one ending the test in absence of faults. The method requires simple hardware, and the bus test program is only 25 bytes long. After the bus test has detected no faults, a control of single functional block is accomplished; multiple fault detections are possible. (5 refs.) A 15 MIPS 32 b microprocessor J YETI'ER, M FORSYTH, W JAFFE, D TANKSALVALA,J WHEELER (Hewlett Packard, Fort Collins, CO, USA) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25-27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 26-27, 325. In German. A 32-b VLSI CPU designed to implement a set of 140 instructions, using direct hardwired decoding and execution, is described. The circuit has been fabricated in 1.5 Ima NMOS technology utilising two levels of tungsten metallisation. 115,000 transistors are con53
The systolic/cellular system for signal processing J G N A S H , K W PRYZTULA, S HANSEN (Hughes Res. Labs., Malibu, CA, USA) Computer (USA), vol. 20, no. 7, pp. 96-97 (July 1987) A description is given of a systolic/cellular system for large classes of linear algebraic and cellular operations. It consists of a host and a programmable coprocessor. The latter includes an array of 16 • 16 mesh-connected processors, dual-port array memory, and a controller with a separate program memory. The input data and the programs for the coprocessor are loaded from the host into the array memory and the program memory, respectively. The system can operate into two modes: cellular and systolic. Maximum system performance as in the neighbourhood of 450 million operations per second. (4 refs.)
P-NAC: a systolic array for comparing nucleic acid sequences D P LOPRESTI (Dept. ofComput. Sci., Brown Univ., Providence, RI, USA) Computer (USA), vol. 20, no. 7, pp. 98-99 (July 1987) A description is given of the Princeton Nucleic Acid Comparator (P-NAC), a linear systolic array for comparing DNA sequences. The architecture is a parallel realisation of a standard dynamic programming algorithm. Benchmark timings of a NMOS VLSI implementation confirm that for its dedicated application, P-NAC is two orders of magnitude faster than current microcomputers. Experience with the prototype is shaping the design of a second-generation device, to be known as the Brown Nucleic Acid Comparator (B-NAC), that will be algorithmically flexible and more tolerant of fabrication faults. (2 refs.)
Integrating systolic arrays into a supersystem W LIN, S CHIN, C HO (General Electric Co., Schenectady, NY, USA) Computer (USA), vol. 20, no. 7, pp. 100-101 (July 1987) A reconfigurable two-dimensional processor array is proposed that is a tradeoff between large-grain vector machines and small-grain, pure systolic arrays. The advantages are fourfold. The advantages of this approach are outlined, and the architecture is described. (2 refs.)
The concept and implementation of data-driven processor arrays I KOREN (Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA), I PELED Computer (USA), vol. 20, no. 7, pp. 102-103 (July 1987) The architecture and principles of a flexible VLSI array that would allow the generation of new computation fronts and their cancellation at a later time are described. The order in which instructions are executed is data-dependent, so each processing element is truly data-driven. It is shown that it is feasible to map an arbitrary algorithm onto such an array. (5 refs.) Application ofa convolver chip to anti-aliasing computergenerated images T W ROWLEY (Hirts Res. Centre, GEC Res., Wembley, England) Disp. Technol. &Appl. (GB), vol. 8, no. 3, pp. 147-150 (July 1987) Aliasing artefact may be reduced or removed from computer-generated images by using convolution filtering. The causes of aliasing artefacts are examined, the use of convolution filters for their removal or reduction is proposed and the application of the MA7180 convolver chip for this purpose is explored. Examples of particular filter configurations are used to illustrate possible applications to computer-generated image data streams. Functional self test in microprocessor systems G C BACCOLINI, C OFFELLI (Inst. of Electrotech. & Electron., Padova Univ., Italy) Conference Proceedings, IEEE Instrumentation and Measurement Technology ~ Conference (Cat. No. 87CH2405-9), Boston, MA, USA, 27-29 April 1987 (New York, USA: IEEE 1987), pp. 321-325 A high fault coverage self-test procedure used in microprocessor systems is described. It is based on a bus test program, which works in such a way that a bus fault entraps it in a situation that can be either an infinite loop or a jump to a location different from the one ending the test in absence of faults. The method requires simple hardware, and the bus test program is only 25 bytes long. After the bus test has detected no faults, a control of single functional block is accomplished; multiple fault detections are possible. (5 refs.) A 15 MIPS 32 b microprocessor J YETI'ER, M FORSYTH, W JAFFE, D TANKSALVALA,J WHEELER (Hewlett Packard, Fort Collins, CO, USA) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25-27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 26-27, 325. In German. A 32-b VLSI CPU designed to implement a set of 140 instructions, using direct hardwired decoding and execution, is described. The circuit has been fabricated in 1.5 Ima NMOS technology utilising two levels of tungsten metallisation. 115,000 transistors are con53