Intel flash EPROM for in-system reprogrammable nonvolatile storage

Application note Intel flash EPROM for in-system reprogrammable nonvolatile storage Flash memory has reprogrammability advantages over EPROM and is not limited in capacity like EEPROM. Saul Zales and Dale Elbert describe Intel's flash EPROM technology and its use in a microcomputer application

For years engineers have suffered frustration at the hands of the EPROM. EPROMs provide a cost-effective way of storing large amounts of firmware in a digital system, but are inconvenient to program and reprogram. They have to be taken out of a system, erased in a UV enclosure and then reprogrammed in a dedicated EPROM programmer. Engineers can now use the flash EPROM to store firmware. This is a modified EPROM that can be erased electronically. Consequently, it is possible to build a flash EPROM into a system and erase and reprogram it without removing it from the system. Flash EPROMs offer the same capacity as the conventional EPROM and are not limited to small capacities like the EEPROM. This application note introduces the flash EPROM and describes its operating principles. Since it requires an accurate Vpp supply for programming, the application note descr/bes several ways of generating an on-board Vpp. The final part demonstrates how flash EPROM can be used in a simple microcomputer based on the 80C186. A.C. microsystems

memory

flash EPROM

Intel's ETOX (EPROM tunnel oxide) flash memories combine electrical chip-erasure and reprogramming with EPROM nonvolatility and ease of use. Advances in tunnel oxides have made it possible to develop doublepolysilicon single-transistor electricallyerasable programmable memories. ETOX flash memories electrically erase all bits in the array matrix via electron tunnelling. The EPROM programming mechanism of hot electron injection is employed for electrical byte programming. A command port interface, internal margin voltage generation, and address and data latches augment standard EPROM circuitry to make the 28F256 a high-density memory optimized for microprocessorcontrolled reprogramming. The dense one-transistor cell structure, coupled with high array efficiency, yields a 256kbit die measuring 181 x 203 mils.

Intel Corporation,3065 BowersAvenue,Santa Clara,CA 95051,USA

TECHNOLOGY OVERVIEW ETOX flash memory technology is derived from Intel's standard CMOS EPROM process base. Using advanced CMOS 1.5 pm technology, the 32 768 x 8-bit flash memories employ a 6pm x 6pm singletransistor cell, affording array density comparable to EPROM technology. The flash memory cell structure is identical to the EPROM structure except for the thinner gate (tunnel) oxide (see Figure 1). An update of the featured 28F256 device, the 28F256A, is now available. Its ETOX-II technology affords 10 Ms/byte programming and 1Ok cycles reprogramming potential.) High quality tunnel oxide under the single floating polysilicon gate allows electrical erasure. All cells in the array are simultaneously erased via Fowler-Nordheim tunnelling. Applying 12V on the source junctions and grounding the select gates typically erases the entire array

in 200 ms. Programming is accomplished with the standard EPROM mechanism of hot electron injection from the cell drain junction to the floating gate. Programming is initiated by bringing both the select gate and the cell drain to high voltage. Programming occurs at a rate of 1O0 p s/byte. DEVICE ARCHITECTURE Figure 2 shows the block diagram for the 28F256. The feature which differentiates Intel's 256kbit flash memory is its command port architecture. The command port simplifies microprocessor control of the erase, erase verify, program, program verify, and read operations, without the need for additional control pins or

Cell +VG FIRSTLEVEL T i~/POLYSILICON(FLOATING)

EPROM SECOND LEVEL

POLYSILICON ~

+VD v~ I I 325~ "l ~Tm GATEOXIDE ""

I

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P-SUBSTRATE

Cell +VG FIRSTLEVEL POLYSILICON T I/(FLOATING)

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P-SUBSTRATE

Figure 1. Comparison of EPROM and flash memory cells

0141-9331/90/08543-07 © 1990 ButtenNorth-Heinemann Ltd Vol 14 No 8 October 1990

543

Application note

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.

.

.

.

.

.

.

DQo-DQ7 Vcc

~,

Vss Vpp

p, J ERASEVOLTAGE I

~ 7

, COM lAND REG ;TER

I

INPUT/OUTPUT BUFFERS

SWITCH I

/

I TO'RR,Y

I SOURCE

DEC DER ST TE LA CH

PGM VOLTAGE I SWITCH

I

CHiP ENABLE OUTPUTENABLE LOGIC

DATA LATCH

Y-DECODER ~

Y-GATING

Ao-A14

[

X-DECODER

I:l

262,144 BIT CELL MATRIX

Figure 2. 28F256 block diagram the multiplexing of high voltage with control functions. On-chip address and data latches minimize system interface logic and free the system bus during erase and program operations. High voltage (12 V) on the Vpp pin enables the command port. In the absence of this high voltage, the device only performs the read operation, inhibiting erasure or programming of the device. (Figure 3 shows 28F256 pin configurations.) The command port consists of a command register, command decoder and state latch, the data-in latch, and the address latch. The command decoder output directs

the operation of the erase voltage switch, program voltage switch, and the erase/program verify voltage generator. Functions are selected via the command port in a microprocessor write cycle controlled by the chipenable and write-enable pins. Contents of the address latch are updated on the falling edge of writeenable. The rising edge of writeenable latches the command and data registers and initiates operations. Erasure is achieved through a twostep write sequence. The erase setup code is written to the command register in the first cycle. The erase

k.j Vpp C 1 NCI- 2

32 "1 VCC 31 " I ~

NCr" 3

30 "1NC

A12C 4

29 "1A14

A7 C 5

28 "1A13

AS C 6

27 "1 AB

nnnnnnn / 4 A7C 5 A6C 6

A5 C 7

26 "1 A9

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25 "1All

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24 "IO-E

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23 "lAID

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22 "1~'~

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AOC 12

21 "ID07

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20 "1 DO6

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17 "ID03

Figure 3. 28F256 pin configurations 544

3

2

1 32 31 30 G 29 "1 A14 28 "m A13

28F256 32-LEADPLCC 0.450" X 0.550"

10

TOP VIEW

1

27 "I A8 '-lAg 26 25 "~A11 24 "10E 23 O A I O 22 21 "1 DO7

14 15 16 17 18 19 20

UUUUUUU

.

.

.

confirmation code is written in the second cycle. The rising edge of this second write-enable pulse initiates the erase operation. The command decoder triggers the erase voltage switch, connectingthe 12 V supply to the source of all bits in the array, while all wordlines are grounded. FowlerNordheim tunnelling results in the simultaneous erasure of all bits. Writing the erase verify code into the command register terminates erasure, latches the address of the byte to verify, and sets the internally generated erase margin voltage. The microprocessor then accesses the output from the addressed byte using standard read timings. The verify procedure repeats for all addresses. Should a byte require more time to reach the erased state, another erase operation is applied. The erase and verify operations continue until the entire array is erased. Programming follows a similar flow. The program set-up command is written to the command register on the first cycle. The second cycle loads the address and data latches. The rising edge of the second writeenable pulse initiates programming by applying high voltage to the gates and drains of the bits to be programmed. Writing the program verify command to the register terminates the programming operation and applies the program verify voltage to the newly programmed byte. Again, the addressed byte can be read using standard microprocessor read timings. Should the addressed byte require more time to reach the programmed state, the programming operation and verification are repeated until the byte is programmed. Erase and program verification ensure the data retention of the newly altered memory bits. The cell margining performed in the QuickPulse Programming and Quick-Erase algorithms is more reliable than historical overpulsing schemes, as margining tests the amount of charge stored on the floating gate. Intel's flash memories employ a unique circuit to generate the erase and program verify voltages internally. This consists of a high voltage switch and the verify voltage

Microprocessors and Microsystems

Application note Down Conversion Vpp

-E

(From 16.00V-26 OOV to 12.00V)

Vpp

Vpp

v,.~--~,.

T

LM-317

°'± '

M2

L1,,

g

-

-]

;

---t

_ vo=

T

k~__~_ !.=_S~.!R~!RL*...gj

-----

COMPONENTS

COST*

LM-317 R1 = 124, 1% R2 = 1070, 1% C1 = 0.1 t..cF C2 = 100 v F

0.40 0.045 0.045 0.02 0.15

VERIFY

R2

VOLTAGE

I R3

ENABLE

_

...........X............................,iT

R1

M4

°= I

$0.66

Figure 6. Vpp generation circuit: regulation from a higher voltage

r

VERIFY GENERATOR

HIGH VOLTAGE SWITCH

Down Conversion

Figure 4.

generator. Transistors M1 -M4 constitute the high-voltage switch which disconnects Vpp from the resistor when the device is not in the verify mode. The verify voltage generator includes a resistor divider and a buffer. Internal margin voltage generation maintains microprocessor compatibility by eliminatingthe need for external reference voltages. Figure 4 shows a simplified version of the circuit.

Vpp

(From 16.0V-40.0V to 12.00V)

Erase/program verify generator

SPECIFICATIONS

Flash memories, like EPROMs, require a 12 V extemally generated power supply for reprogramming. Intel's 28F256 offers two Vpp specifications: 12.0 V + 0.6 V (5%) and 12.75 V +0.25 £ (2%). ( V p p generation techniques are discussed below and Figures 5-9 show different circuit alternatives.) Since the 27F256 is for EPROM OBP replacement, it uses the EPROM-compatible 12.75 V Vp.p.(only). Both devices guarantee a minimum of 100 reprogramming cycles, sufficient for most version update applications. The 5% Vpp devices are compatible with most off-the-shelf (or available in-system) power supplies. The EPROM-compatible 12.75 V devices offer a performance advantage over the 12 V versions. Typical 32 kbyte 12.75 V programming

Vol 74 No 8 October 1990

Vln

takes less than four seconds - - a 510 times improvement over the 12.0 V part. This saving, multiplied by all the devices in the remote system, and by the number of remote systems to be updated, can be significant. However, this improvement factor is based on hot temperature programming data. Room temperature results will be more comparable. It is essential to use the specified Vpp when reprogramming either the 12 V or 12.75 V device. Once the command to erase, program, or verify is issued, the device generates the required voltages internally from the Vpp supply. The command register controls selection of internal reference circuitry tapped from V p p . An improper Vpp level causes the DownConversion (From 14.0V-26.0V to 12.00V

:

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= i........ - - . .................. 1) i ............................

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,

COMPONENTS

COST'

LT- 1085 R1 = 124, 1% R2 = 1070, 1% C1 = 10 v F C2 = 1OFF

2.50 0.045 0.045 0.10 0.10 $2.79

Figure 7.

Vpp generation circuit:

regulation from a higher voltage references to be wrong, degrading performance. When programming UV EPROMs, Vcc is raised to 6.5V. On flash memories, the V p p reference circuitry and command register architecture provide the same function while keeping Vcc and V p p a t static levels. An incorrect Vcc level during UV EPROM programming poses similar hazards to improper Vpp levels on flash memories.

Vpp

GENERATION

COMPONENTS

COST*

LM2391CT R1 = 2OK, 1% R2 = 180K, 1% R3 = 10 Kfl C1 = 0.1 .u,F C2 = IO0~F

$0.75 0.045 0.045 0.02 0.02 0.15

A static Vpp is needed to reprogram flash memories. The Vpp voltage can be generated by

$1.03

• regulating it down from a higher voltage; • pumping it up from a lower voltage

Figure 5. Vpp generation circuit: regulation from a higher voltage

545

Application note Down Conversion Circuit (From 50V to 12.0V) L1 11

6

~ut

~ vcc TL-497AC c I T.3 T Wn = 5.Ov ~ I s.ec~l,gvo~.g, I <~ I I

Regulator Coral S 1%

= 12.~

1o [

c, ~ L~, ,~;-6;~Em~"1 1 ±c=±c3 ,0~T 31 21, 3 ,l 1 ~ -],°FT,~F [ c1_ i I [ R=~ ~ I

COMPONENTS

COST

TL-497AC R1 R2 R3 C1 C2 C3 L1 Ct

1.15 0.02 0.045 0,045 0.15 0.15 0.02 1.00 0.02 $2.600

Figure 8. Vpp generation circuit: 512V pump (i.e. charge converter, etc.); • designing or system's 12V required ISW specifications.

pump, DC/DC or specifying the supply with the tolerances and

Reprogramming current should be considered when selecting a V p p generation option. Parallel reprogramming for flash memory in 16-bit or 32-bit systems will require additional current capability. R e g u l a t i n g from h i g h e r v o l t a g e Vpn is obtained from a higher voyage by using a regulator. If using the 12.0V flash memory then standard three-terminal 12 V +1%, +2% +4% nonadjustable regulators are also available. To achieve the 0.25 V tolerance for the 12.75V specification, precision resistors are required. Some regulators have on/ off control built-in (see Figure 5). All regulators require a minimum input voltage greater than the output voltage (see Figures 6 and 7).

Raising 5 V to 1 2 V

be obtained by pumpingVcc and regulating it to the proper voltage. A voltage charge-pump can be designed and built using discrete components, by using a chargepump integrated circuit and some Vpp c an

546

discrete components (see Figure 8), or by using a monolithic DC/DC converter (see Figure 9). When using adjustable circuits containing discrete components, output voltage should fall within the Vpp specifications for all corners of the components' skew (i.e. Vcc + 10%; Rx + I%, Ry _+ I%, etc.). The resistors' temperature coefficients should be included in the calculation matrix. Note that each of the various components can add error to the V pp supply. The monolithic DC/DC converter shown in Figure 9 fits into a 24-pin socket. It offers the advantages of close temperature tracking and ease of implementation. It has been characterized at temperatures and meets all the Vpp specifications. Most DC/DC converters are only 50-60% efficient, so heat dissipation may be a concern. In all Vpp generation methods, a capacitor on the input voltage terminals reduces the output noise voltage. Some power supplies (see Figures 7 and 8) specify a large-valued capacitor to decrease the effective series resistance (ESR). Place a 0.1 p F capacitor within 0.25 in of each flash memory's Vpp input (in addition the one on the V p p generator's input). The ESR is inversely proportional to the capacitance value and the rated working voltage. To lower the ESR choose a capacitor with a large capacitance and a high working voltage (i.e. greater than 100 V).

Data p r o t e c t i o n

With V p p below Vcc + 2 V, internal circuitry disables the command register and eliminates the possibility of inadvertent erasure or programming. Switching the Vpp supply off provides the secondary benefits of improved power and thermal management. There are two ways to switch V p p on and off: • directly switch the Vpp generator's output, or • switch the input voltage supplying the regulation circuit. Any switching circuit will cause a

Up Conversion Circuit

(From5.0Vto 12,75V)

5v s . o o v ~1 +÷s,

cl ~~

v~ e.,~.>

I

Valor PM7022

~ G N DGND

: .... i o:: oi__~ B,,,,..A COMPONENTS

COST*

PM7022 C1 - 0.1 ,u.F

$6.25 0.05

Buzl 1A

2.59

$8.89

Figure 9. Monolithic converter

DC/DC

voltage drop, so choose a switch with this drop in mind. Controlling the input voltage of a DC/DC convertor with a MOSPOWER FET is a straightforward approach. (See Figure 9). The FET switch should be chosen carefully. It should have a low on-resistance to minimize the voltage divider effect of the converter and FET switch. If the voltage across the FET switch is too high, the converter input voltage will not meet its specifications. The switching circuit must always be designed with sufficient margin to maximum V p p and Vcc load currents. WRITES AND READS DURING Vpp T R A N S I T I O N S

After switching Vpp off, the CPU can read from the flash memory without waiting for the capacitors on Vpp to bleed off. To do this, the read memory command should be written prior to issuing the Vpp_OFF instruction. Alternatively, the device resets automatically to read mode when V pp drops below Vcc + 2 V. Raising Vpp tO 12 V enables the command register. It is necessary to wait 100 ns after Vpp achieves its steady state value before writing to the command register. Remember that the steady state Vpp settling time depends on both the power supply slew rate and the capacitive load on the Vpp bus. Also note that Vcc and chip enable must go hiljh before Vp during powerup, and remain higl~

Microprocessors and Microsystems

Application note Vpp Pin c ~ . - . i ~ - - ~ " ~ - o Vcc C .~_ I R = 10kaovpp

after Vpp powers down. This power sequencing protects against inadvertent writes.

OTHER V~,CONSIDERATIONS The Vpp pin is a MOS input which can be damaged by electrostatic discharge (ESD). In OBP applications, an external power source supplies Vpp and is then removed. Electrostatic charge can build up on the floating Vpp pin. This problem may be solved by tying the pin to Vcc through a diode and pull-up resistor (Figure 10a) or through a resistor to ground (Figure 10b). With either approach a 10 kN resistor should be used to minimize V p p power consumption. Typically EPROMs require Vpp to be within one diode drop of Vcc for optimal standby power consumption. Either approach can be used with flash memory. ISW (in-system writing) applications do not require this ESD protection, as most regulators and charge pumps contain a voltage divider on the output stage. A divider provides a resistive path to ground even with the supply tumed off. (It is important to check the schematics of the chosen Vpp supply.) However, if the Vpp supply is switched directly, the resistor should be added to ground; the switch isolates the Vpp pin and allows charge to build up.

a

Vpp Pin ~

Vpp

b Figure 10. a, Vpp tied to Vcc; b, Vpp tied to ground

Vcc Vo¢ TIB SRDY ARDY

BHE

• Keep all high current loops lengths to a minimum using copper connections that are as wide as possible. (This will decrease the inductive impedance which otherwise causes noise spikes.) • Place the voltage regulator as close to the flash memory as practical to avoid an output ground loop. Excessive lead length results in an error voltage across the distributed line resistance. • Separate the input capacitor return from the regulator load return line.

,9 D7 8 1:)6 7D5

Q7 12 Q4B 13 ~ 14

1

3

W--~HIGH

6D4 O4ts s03{2]O~ Is

A19/S( A18JS~ A17/$4 A16/S~

4 D2 3 01

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A D l l la AD10 12

AD9 14 ADS 16

6 ~ LOW

GNC ~ L I

VSS VSS

AD15 1 AD14 3 AD13 57

4 ~'~'~

A18 A17 A16 A15 A14 A13 A12 All A10

7 05 Q5 =o, '~ 03 131 4 02 3 O1

2oo 11LE

02 17 Q1 1R

~:~19 GND

A7 A6

I~pyg/RCUITRY AND TRACE D15 D14 D13 D12 Dll D10 D9 08

80C18(

[1]

Vppcircuitry and traces should be laid out for high frequency operation, since programming power characteristics exhibit an AC current component. The following design rules should be employed. • Keep leads as shortas possible and use a single ground point or ground plane (a ground plane eliminates problems). • Locate the resistor network (or a regulator) as close as possible to the adjustment pin to minimize noise pick-up in the feedback loop. The resistor divider network should also be as short as possible to minimize line loss.

Vol 74 No 8 O c t o b e r 7990

r I:~E~ET

D7

D6 D5

I34 [33 D2 D1

DO

12:5

.........~

4~ INT0

INT 1

INT 2 INT 3

12:10 19:6

I Figure 11.

CPU and address and data buffers

547

Application note

.

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.

.

.

.

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.

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.

.

.

.

This eliminates an input ground loop, which could result in excessive output ripple.

20 v~ Vp¢

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A12 AIO =

22

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SYSTEM DESIGN EXAMPLE: INCORPORATING THE 2 8 F 2 5 6 IN A N 8 0 C 1 8 6 DESIGN

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VR~ WE HIGH WE LOW

22 Vcc

30 A17 L'~ A16 AI5 A14

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-

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10

~.

11 AI 12 ~0

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010 011 012 013 014 D15

Figure 12.

EPROM and flash memory

HIGH LOW R~

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20

~J~ 2

A14 A13 !At2

~

27

A13 A12 A11

Vcc d 27 ~'~22

M0 ~ ~

2 ~8 ~7

fO. [10H1 GND ~ m

02 03 O4 I)5 O6 D7 Oe 00

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Figure 13.

548

Static memory

...... 1

e~,6

A general-purpose controller and/or data acquisition system was built to demonstrate 86-based ISW. The 80C186 CPU drives the system, which contains 16 kbyte of EPROM (two 27C64's), 64kbyte of flash memory (two 28F256s), 64 kbyte of SRAM (two g2k X 8-bit) three 8-bit ports (82C55A), one serial port (82510), and a 5 V-12.75 V DC/DC converter. Three 74HC573s demultiplex the address/data bus and latch the byte-high enable line (BHE) and the status lines (if needed). Two 74HC245 data transceivers simulate the worst case data path for a system requiring added drive capability. If the transceivers are not needed they can be replaced with wired headers. See Figures 11-15. The 80C186 reset (output) drives the reset input on the 82510, 82C55A, and the OE\ inputs on the address latches and data transceivers. The reset line goes inactive five clock cycles before the first code fetch. Also, the CPU's write signal is split into byte-write-high and byte-write-low to allow for byte or word writes. The 80C186 has on-chip memory and peripheral chip selects. Two of the memory chip selects are dedicated--the upper chip select (UCS, dedicated for the boot area) and the lower chip select (LCS, for the interrupt vector table area). See the memory map in Figure 16. The permanent code was placed in an EPROM in the UCS memory segment; this code includes routines for hardware initialization, communications, data uploading and downloading, erasure and programming algorithms, I/O drivers, ASCII to binary conversion tables, etc. For greater flexibility, these memory devices could be 27F64 flash memories configured for OBP. This would be useful for systems reconfigured for different communi-

Microprocessors and Microsystems

Application note :rESET

RESET

PA7 PA6 PA5 PA4 I PA3 1 PA2 2 PAl 4 P~

1:27 O-E 3

WR LOW

M AO

4:17 A2 4:18 A1

27 37

D7 [36 D5 [34 133 D2 D1 DO

82C55A [15]

UCS

22 21 20

MCSO

PC7 10 PC6 11 PC5 12

Vcc

~ND

LCS

Figure 16.

PC3 PC2 16 PC1 15 PC0 14

"2"

Version update code, Data Accumulation storage, etc. 40000H

RAM

19 PBO 18

~26

Initialize H/W, Comm, flash memory @go's, etc. FC000H

Application

PB7 25 PB5 P~ PBa PB2 PBI

31 )3 ~2 D1

Boot

Vector table, Stack, Buffers, etc. 0000

80C186 memory map

Serial interface

cation protocols as the last step prior to shipment. Code and constants that might change are placed in the 32 kbyte of flash memory. The RAM is used for the interrupt table, stack, variable data storage, and buffers. The three 8-bit ports on the 82C55A peripheral controller can be used for control and/or data acquisition. The device powers-up with all port pins high. Similarly, all port pins go high after warm resets as well. Because the pins are high after a power-up/reset, an open collector inverter was used to control the MOSPOWER switch which in tum controls Vpp. The FET switch must be driven to one rail or the other to guarantee its low on-resistance. Vpp is turned off during power-up or reset as a hardware write protection solution. The DC/DC converter supplies Vpp. The 82510 is a flexible singlechannel CHMOS UART offering high integration. The device offloads the system and CPU of many tasks associated with asynchronous serial communications. It can be used as a basic serial port for the host serial link, or can be configured to support highspeed modem applications. Software was written to download code and data parameters (code updates) from a PC to the demo board through the PC's COM1 port (serial port). The system can also upload data (remote data acquisition) to the PC via the same link. Once the download code and data has been programmed it can not be lost, even if power should fail. This is because ETOX flash memory is based on EPROM technology and needs no power to retain data.

Vol 14 No 8 O c t o b e r 1990

549'

....

1 %

24

Vcc Vcc Vpp

14

½

10

F

+V

'IR2

+V DC/OC 5/12,75 + - 2% V [16] GND '2 GND 13

-V

4

F1

5 --_,B

Figure 14.

Parallel interface + 12v

2

3

J1:2 J1:20 J14

12v

1 Vcc X2 RESET

XtTxD 6

ET 3

WE LOWA3

14

I~W-R

b-~ TO 11

1 4

10 13

J1:3 J1:5 J1:22 J1:6

3

~

§

4

J1:8

8 11

01 25130

DI

26

DO

5 INT GND

1:4.5

--

Figure 15.

GND J1:7 . "-z J_

--

1

82510 Illl