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Interface characteristics between tungsten silicide electrodes and thin dielectrics
Microelectronic Engineering 55 (2001) 197–203 www.elsevier.nl / locate / mee
Interface characteristics between tungsten silicide electrodes and thin dielectrics a ¨ B. Sell a , *, J. Willer a , K. Pomplun a , A. Sanger , D. Schumann a , W. Krautschneider b a
¨ ¨ Str. 180, D-01099 Dresden, Germany Infineon Technologies, Memory Products, Konigsbrucker TU Hamburg-Harburg, Techn. Electronics, Eissendorfer Str. 38, D-21071 Hamburg, Germany
b
Abstract In today’s ULSI technology there is an increasing demand in metal electrodes for storage capacitors and transistors. In this publication we present an investigation of MOS capacitor structures with CVD tungsten silicide (WSix ) as metal electrode in conjunction with silicon dioxide (SiO 2 ) and oxidized nitride (NO). Bulk silicon and poly silicon were used as second electrode, respectively. Tungsten silicide has been used both as gate electrode and as bottom electrode. For both cases thermal stability up to 7808C with low leakage current has been shown. Band discontinuities between SiO 2 and WSix were estimated from current–voltage measurements. 2001 Elsevier Science B.V. All rights reserved. Keywords: Tungsten silicide; Metal gate; SiO 2 ; NO; Band discontinuity
1. Introduction For ULSI DRAMs it has been recognized, that a storage capacitance with a fixed, non-scalable value is needed for fast and reliable readout of the information. This ground rule independent capacitor value requires for future technology generations that the reduced cell area has to be compensated by higher storage nodes and a higher specific capacitance. The latter is realized by reducing the thickness of the node dielectric but is limited by the onset of direct tunneling. Therefore, new materials not only for dielectrics but also for electrodes are desirable. Metal electrodes lack a depletion region and exhibit the advantage of a small resistivity. This can help to reduce series resistance of high aspect ratio capacitor geometries. However, thermal budget of integrated processes requires high metallurgical stability in addition to process compatibility so that the choice of a suitable metal is crucial. For the introduction of new electrode materials it is therefore indispensable to understand the physics of metal–dielectric interface of appropriate candidates. The use of tungsten silicide (WSi x ) as bottom-electrode has been investigated in conjunction with the high-k dielectric tantalum pentoxide (Ta 2 O 5 ) [1]. It has been reported that this dielectric displays *Corresponding author. Tel.: 1 49-351-886-7758; fax: 1 49-351-886-7752. E-mail address: [email protected] (B. Sell). 0167-9317 / 01 / $ – see front matter PII: S0167-9317( 00 )00448-2
2001 Elsevier Science B.V. All rights reserved.
B. Sell et al. / Microelectronic Engineering 55 (2001) 197 – 203
198
some degradation in direct contact to WSi x when heated above 3008C. In that report [1] the specific capacitance decreased by 30% when raising the annealing temperature from 300 to 4008C while the leakage current was reduced at the same time. This was explained by a thin oxide which was grown on the WSi x . In this work the interface properties between CVD-WSi x electrodes with different stoichiometries and oxide or oxidized nitride (NO) as dielectric have been investigated.
2. Experimental In a first experiment (A) planar capacitor structures with WSi x bottom electrodes were fabricated on 80 wafers. Fig. 1a shows the schematic of the process flow. After oxidation of the substrate 60-nm CVD-tungsten silicide were deposited in a hexagonal phase. Two different thermal treatments were now applied to transform the WSi x in the final tetragonal phase. We compared an RTP-anneal at around 10008C in oxidizing atmosphere with the same anneal in pure nitrogen. In the following the latter process will be referred to as passivation. After an HF-dip, oxidized nitride (NO) and poly-silicon were deposited, annealed at 7808C and patterned as shown in Fig. 1a. In a second experiment (B) planar capacitors with WSi x top electrodes were fabricated as demonstrated in Fig. 1b. Substrates were highly As doped and a nominal 8-nm thermal oxide was grown on top. CVD-WSi x with different stoichiometries was deposited in a hexagonal structured layer and was subsequently transformed to the tetragonal phase at 7808C. As a reference, poly-Si was deposited instead of WSi x on some wafers. LPCVD nitride as hard mask was deposited prior to gate
Fig. 1. Process flow and schematic of test structures of experiment A (a) and experiment B (b).
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patterning. Finally, the nitride hard mask was removed with phosphoric acid to reveal the top electrodes for electrical characterization as shown in Fig. 1b.
3. Results TEM images of the NO / WSi x interface of experiment A are shown in Fig. 2. When the recrystallization of WSi x was done in oxidizing atmosphere, we observed an enhanced growth of oxide at the grain boundaries which could not be removed by an HF-dip (Fig. 2a). This leads to a parasitic oxide capacitance in series to the NO capacitance and thus to a reduced overall capacitance as schematically shown in the figure. A capacitance value of 660 nF / cm 2 ; was measured in accumulation at 2 3 V as shown in Fig. 3. However, when recrystallization was performed in pure nitrogen, no oxide residuals were observed (Fig. 2b) and capacitance increased from 660 nF / cm 2 to more than 800 nF / cm 2 (Fig. 3). Accordingly, the equivalent oxide thickness has been reduced from 5.2 to 4.3 nm for stoichiometries x 5 2.3 and x 5 2.7 and down to 4.1 nm x 5 2.1. At the same time, the leakage current has been reduced by up to two orders of magnitude as shown in Fig. 4. Values for stoichiometries were determined by RBS measurements. Fig. 5 shows a TEM image of the WSi x / oxide / Si interface of experiment B. The observed oxide thickness of 9.2 nm is in good agreement with the 9.0 nm extracted from CV measurements (Fig. 6) for WSi x stoichiometries of 2.3 and 2.7. For tungsten-rich WSi x , however, we determined a somewhat smaller equivalent thickness of 8.4 nm while at the same time the leakage current was reduced by four orders of magnitude (Fig. 7). Naturally, this reduction is only for electron injection from the gate, that means for negative gate voltage. For positive gate voltages we have electron injection from the substrate which should depend only weekly on the gate material. To simulate the tunnel current for positive gate bias, we used the standard Fowler-Nordheim expression [2] and the well known value for the SiO 2 / Si band discontinuity f of 3.15 eV and an oxide thickness of 9.0 nm. Si-depletion has
Fig. 2. TEM images of the NO / WSi x interface of experiment A. A process without surface passivation (a) is compared to a nitrogen passivation process (b). Residual oxide in (a) leads to a parasitic series capacitance which reduces the overall capacitance. Clean interfaces as observed in (b) help to avoid any parasitic capacitance.
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Fig. 3. Capacitance–voltage curves for the samples of experiment A for different stoichiometries x. For x 5 2.1 a slight increase in capacitance is observed. Compared to simulation (not shown) we observe a broadening of the CV profile, which is most likely due to interface states.
been included in the calculations. The result is in excellent agreement with the measured data. Curves for negative gate bias were then fitted using an oxide thickness of 9.0 nm and adjusting the parameter for the band discontinuity between the WSi x and the NO. The extrapolated data is summarized in Table 1.
4. Discussion During the execution of experiment A it was crucial to fabricate a well passivated oxygen-free WSix surface before deposition of NO. It has been reported by Lee et al. [3] that there is an enhanced oxide growth at the grain boundaries during the oxidation of WSi x . In addition, metal oxides form at these sites, which cannot be removed with an HF-dip. If in contrast the grain boundaries are stuffed with nitrogen, a uniform dielectric can be deposited yielding a lower leakage current and increased capacitance. Comparing the measured capacitance to a simulation (not shown) shows a broadening of the CV curve and an increase in the minimum capacitance. This is most likely attributed to a large density of interface states [4] which is expected since state densities of a dielectric / poly-Si interface rather than of a dielectric / bulk-Si interface influence these CV measurements. The values for the band discontinuity extracted in experiment B are subject to some experimental
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Fig. 4. IV curves for samples of experiment A. Nitrogen passivation reduces the leakage current by more than one order of magnitude which is almost independent of WSi x stoichiometry. The insets show the band diagram for positive and negative gate voltage, respectively.
Fig. 5. Capacitance–voltage curves for samples of experiment B. An oxide thickness of about 9.0 nm is observed for stoichiometries x 5 2.3 and x 5 2.7. For x 5 1.9, however, the equivalent oxide thickness is reduced to 8.4 nm.
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Fig. 6. TEM image of wafer 3 of experiment B. After exposing the wafer to a 8508C anneal the oxide is still uniform and exhibits a thickness of around 9.2 nm.
uncertainties since the thickness of the oxide has a strong influence on the result. An experiment for a more accurate extraction of the band discontinuities is in preparation. Nonetheless it can be said, that there is a strong influence of the WSi x stoichiometry on band discontinuity. Taking into account the smaller value for the equivalent oxide thickness of the samples with x 5 1.9, the band discontinuity even changes from 3.0 eV for x 5 2.3 to 3.9 eV for x 5 1.9. This is very close to the value for pure tungsten. All samples with WSi x electrodes exhibit a smaller leakage current than those with poly-Si electrodes.
5. Summary In conclusion, MOS capacitor structures with WSi x bottom and top electrodes, respectively, were fabricated exhibiting thermal stability up to 7808C with low leakage currents. A nitrogen passivation for WSi x bottom electrodes was developed, yielding a 20% increase in capacitance while lowering the leakage current by more than one order of magnitude. In a second experiment WSix top electrodes were deposited directly on oxide showing a smooth interface and good electrical characteristics even after processing at 7808C. Band discontinuities between WSi x and oxide were estimated as a function of stoichiometry from IV measurements.
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Fig. 7. IV characteristics for samples of experiment B for different stoichiometries of WSix and for poly-Si as reference. The black lines are simulated IV curves using the estimated values for the band discontinuities. The insets show the band diagrams for positive and negative gate voltage, respectively.
Table 1 Extracted values for the band discontinuity f between oxide and WSi x as a function of WSi x stoichiometry as described in experiment B a Wafer no. Electrode material Stoichiometry (x) t eq (CV measurements) (nm) Estimated band discontinuity f (eV) a
20 WSi x 1.9 8.4 3.5
3 WSi x 2.3 9.0 3.0
5 WSi x 2.7 9.0 3.0
13 Poly – 9.0 2.8
Values for the stoichiometry were observed by RBS and equivalent oxide thickness t eq determined by CV measurements.
References [1] [2] [3] [4]
S. Kamiyama et al., IEDM Tech. Dig. (1993) 49–52. D. Roy, Quantum Mechanical Tunneling And Its Applications, World Scientific Publication, 1986. J.-G. Lee et al., Jpn. J. Appl. Phys. 36 (1997) 7140–7145. E.H. Nicollian, J.R. Brews, MOS Physics and Technology, Wiley, New York, 1982.
Interface characteristics between tungsten silicide electrodes and thin dielectrics a ¨ B. Sell a , *, J. Willer a , K. Pomplun a , A. Sanger , D. Schumann a , W. Krautschneider b a
¨ ¨ Str. 180, D-01099 Dresden, Germany Infineon Technologies, Memory Products, Konigsbrucker TU Hamburg-Harburg, Techn. Electronics, Eissendorfer Str. 38, D-21071 Hamburg, Germany
b
Abstract In today’s ULSI technology there is an increasing demand in metal electrodes for storage capacitors and transistors. In this publication we present an investigation of MOS capacitor structures with CVD tungsten silicide (WSix ) as metal electrode in conjunction with silicon dioxide (SiO 2 ) and oxidized nitride (NO). Bulk silicon and poly silicon were used as second electrode, respectively. Tungsten silicide has been used both as gate electrode and as bottom electrode. For both cases thermal stability up to 7808C with low leakage current has been shown. Band discontinuities between SiO 2 and WSix were estimated from current–voltage measurements. 2001 Elsevier Science B.V. All rights reserved. Keywords: Tungsten silicide; Metal gate; SiO 2 ; NO; Band discontinuity
1. Introduction For ULSI DRAMs it has been recognized, that a storage capacitance with a fixed, non-scalable value is needed for fast and reliable readout of the information. This ground rule independent capacitor value requires for future technology generations that the reduced cell area has to be compensated by higher storage nodes and a higher specific capacitance. The latter is realized by reducing the thickness of the node dielectric but is limited by the onset of direct tunneling. Therefore, new materials not only for dielectrics but also for electrodes are desirable. Metal electrodes lack a depletion region and exhibit the advantage of a small resistivity. This can help to reduce series resistance of high aspect ratio capacitor geometries. However, thermal budget of integrated processes requires high metallurgical stability in addition to process compatibility so that the choice of a suitable metal is crucial. For the introduction of new electrode materials it is therefore indispensable to understand the physics of metal–dielectric interface of appropriate candidates. The use of tungsten silicide (WSi x ) as bottom-electrode has been investigated in conjunction with the high-k dielectric tantalum pentoxide (Ta 2 O 5 ) [1]. It has been reported that this dielectric displays *Corresponding author. Tel.: 1 49-351-886-7758; fax: 1 49-351-886-7752. E-mail address: [email protected] (B. Sell). 0167-9317 / 01 / $ – see front matter PII: S0167-9317( 00 )00448-2
2001 Elsevier Science B.V. All rights reserved.
B. Sell et al. / Microelectronic Engineering 55 (2001) 197 – 203
198
some degradation in direct contact to WSi x when heated above 3008C. In that report [1] the specific capacitance decreased by 30% when raising the annealing temperature from 300 to 4008C while the leakage current was reduced at the same time. This was explained by a thin oxide which was grown on the WSi x . In this work the interface properties between CVD-WSi x electrodes with different stoichiometries and oxide or oxidized nitride (NO) as dielectric have been investigated.
2. Experimental In a first experiment (A) planar capacitor structures with WSi x bottom electrodes were fabricated on 80 wafers. Fig. 1a shows the schematic of the process flow. After oxidation of the substrate 60-nm CVD-tungsten silicide were deposited in a hexagonal phase. Two different thermal treatments were now applied to transform the WSi x in the final tetragonal phase. We compared an RTP-anneal at around 10008C in oxidizing atmosphere with the same anneal in pure nitrogen. In the following the latter process will be referred to as passivation. After an HF-dip, oxidized nitride (NO) and poly-silicon were deposited, annealed at 7808C and patterned as shown in Fig. 1a. In a second experiment (B) planar capacitors with WSi x top electrodes were fabricated as demonstrated in Fig. 1b. Substrates were highly As doped and a nominal 8-nm thermal oxide was grown on top. CVD-WSi x with different stoichiometries was deposited in a hexagonal structured layer and was subsequently transformed to the tetragonal phase at 7808C. As a reference, poly-Si was deposited instead of WSi x on some wafers. LPCVD nitride as hard mask was deposited prior to gate
Fig. 1. Process flow and schematic of test structures of experiment A (a) and experiment B (b).
B. Sell et al. / Microelectronic Engineering 55 (2001) 197 – 203
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patterning. Finally, the nitride hard mask was removed with phosphoric acid to reveal the top electrodes for electrical characterization as shown in Fig. 1b.
3. Results TEM images of the NO / WSi x interface of experiment A are shown in Fig. 2. When the recrystallization of WSi x was done in oxidizing atmosphere, we observed an enhanced growth of oxide at the grain boundaries which could not be removed by an HF-dip (Fig. 2a). This leads to a parasitic oxide capacitance in series to the NO capacitance and thus to a reduced overall capacitance as schematically shown in the figure. A capacitance value of 660 nF / cm 2 ; was measured in accumulation at 2 3 V as shown in Fig. 3. However, when recrystallization was performed in pure nitrogen, no oxide residuals were observed (Fig. 2b) and capacitance increased from 660 nF / cm 2 to more than 800 nF / cm 2 (Fig. 3). Accordingly, the equivalent oxide thickness has been reduced from 5.2 to 4.3 nm for stoichiometries x 5 2.3 and x 5 2.7 and down to 4.1 nm x 5 2.1. At the same time, the leakage current has been reduced by up to two orders of magnitude as shown in Fig. 4. Values for stoichiometries were determined by RBS measurements. Fig. 5 shows a TEM image of the WSi x / oxide / Si interface of experiment B. The observed oxide thickness of 9.2 nm is in good agreement with the 9.0 nm extracted from CV measurements (Fig. 6) for WSi x stoichiometries of 2.3 and 2.7. For tungsten-rich WSi x , however, we determined a somewhat smaller equivalent thickness of 8.4 nm while at the same time the leakage current was reduced by four orders of magnitude (Fig. 7). Naturally, this reduction is only for electron injection from the gate, that means for negative gate voltage. For positive gate voltages we have electron injection from the substrate which should depend only weekly on the gate material. To simulate the tunnel current for positive gate bias, we used the standard Fowler-Nordheim expression [2] and the well known value for the SiO 2 / Si band discontinuity f of 3.15 eV and an oxide thickness of 9.0 nm. Si-depletion has
Fig. 2. TEM images of the NO / WSi x interface of experiment A. A process without surface passivation (a) is compared to a nitrogen passivation process (b). Residual oxide in (a) leads to a parasitic series capacitance which reduces the overall capacitance. Clean interfaces as observed in (b) help to avoid any parasitic capacitance.
200
B. Sell et al. / Microelectronic Engineering 55 (2001) 197 – 203
Fig. 3. Capacitance–voltage curves for the samples of experiment A for different stoichiometries x. For x 5 2.1 a slight increase in capacitance is observed. Compared to simulation (not shown) we observe a broadening of the CV profile, which is most likely due to interface states.
been included in the calculations. The result is in excellent agreement with the measured data. Curves for negative gate bias were then fitted using an oxide thickness of 9.0 nm and adjusting the parameter for the band discontinuity between the WSi x and the NO. The extrapolated data is summarized in Table 1.
4. Discussion During the execution of experiment A it was crucial to fabricate a well passivated oxygen-free WSix surface before deposition of NO. It has been reported by Lee et al. [3] that there is an enhanced oxide growth at the grain boundaries during the oxidation of WSi x . In addition, metal oxides form at these sites, which cannot be removed with an HF-dip. If in contrast the grain boundaries are stuffed with nitrogen, a uniform dielectric can be deposited yielding a lower leakage current and increased capacitance. Comparing the measured capacitance to a simulation (not shown) shows a broadening of the CV curve and an increase in the minimum capacitance. This is most likely attributed to a large density of interface states [4] which is expected since state densities of a dielectric / poly-Si interface rather than of a dielectric / bulk-Si interface influence these CV measurements. The values for the band discontinuity extracted in experiment B are subject to some experimental
B. Sell et al. / Microelectronic Engineering 55 (2001) 197 – 203
201
Fig. 4. IV curves for samples of experiment A. Nitrogen passivation reduces the leakage current by more than one order of magnitude which is almost independent of WSi x stoichiometry. The insets show the band diagram for positive and negative gate voltage, respectively.
Fig. 5. Capacitance–voltage curves for samples of experiment B. An oxide thickness of about 9.0 nm is observed for stoichiometries x 5 2.3 and x 5 2.7. For x 5 1.9, however, the equivalent oxide thickness is reduced to 8.4 nm.
202
B. Sell et al. / Microelectronic Engineering 55 (2001) 197 – 203
Fig. 6. TEM image of wafer 3 of experiment B. After exposing the wafer to a 8508C anneal the oxide is still uniform and exhibits a thickness of around 9.2 nm.
uncertainties since the thickness of the oxide has a strong influence on the result. An experiment for a more accurate extraction of the band discontinuities is in preparation. Nonetheless it can be said, that there is a strong influence of the WSi x stoichiometry on band discontinuity. Taking into account the smaller value for the equivalent oxide thickness of the samples with x 5 1.9, the band discontinuity even changes from 3.0 eV for x 5 2.3 to 3.9 eV for x 5 1.9. This is very close to the value for pure tungsten. All samples with WSi x electrodes exhibit a smaller leakage current than those with poly-Si electrodes.
5. Summary In conclusion, MOS capacitor structures with WSi x bottom and top electrodes, respectively, were fabricated exhibiting thermal stability up to 7808C with low leakage currents. A nitrogen passivation for WSi x bottom electrodes was developed, yielding a 20% increase in capacitance while lowering the leakage current by more than one order of magnitude. In a second experiment WSix top electrodes were deposited directly on oxide showing a smooth interface and good electrical characteristics even after processing at 7808C. Band discontinuities between WSi x and oxide were estimated as a function of stoichiometry from IV measurements.
B. Sell et al. / Microelectronic Engineering 55 (2001) 197 – 203
203
Fig. 7. IV characteristics for samples of experiment B for different stoichiometries of WSix and for poly-Si as reference. The black lines are simulated IV curves using the estimated values for the band discontinuities. The insets show the band diagrams for positive and negative gate voltage, respectively.
Table 1 Extracted values for the band discontinuity f between oxide and WSi x as a function of WSi x stoichiometry as described in experiment B a Wafer no. Electrode material Stoichiometry (x) t eq (CV measurements) (nm) Estimated band discontinuity f (eV) a
20 WSi x 1.9 8.4 3.5
3 WSi x 2.3 9.0 3.0
5 WSi x 2.7 9.0 3.0
13 Poly – 9.0 2.8
Values for the stoichiometry were observed by RBS and equivalent oxide thickness t eq determined by CV measurements.
References [1] [2] [3] [4]
S. Kamiyama et al., IEDM Tech. Dig. (1993) 49–52. D. Roy, Quantum Mechanical Tunneling And Its Applications, World Scientific Publication, 1986. J.-G. Lee et al., Jpn. J. Appl. Phys. 36 (1997) 7140–7145. E.H. Nicollian, J.R. Brews, MOS Physics and Technology, Wiley, New York, 1982.