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gate insulator interface in organic field effect transistors
Thin Solid Films 499 (2006) 95 – 103 www.elsevier.com/locate/tsf
Interfacial charge phenomena at the semiconductor/gate insulator interface in organic field effect transistors Eiji Itoh *, Keiichi Miyairi Department of Electrical and Electronic Engineering, Shinshu University, 4-17-1, Wakasato, Nagano 380-8553, Japan Available online 8 August 2005
Abstract We have investigated the electrical characteristics of metal-insulator-semiconductor (MIS) capacitors consisting of p-type semiconductor layer, either regio-regular poly(3-hexylthiophene) (P3HT) or copper-phthalocyanine (CuPc) prepared on tantalum oxide, with a high dielectric constant (¨ 20), or double layered structure consisting of tantalum oxide and polyimide thin films. These results are combined with field effect transistor (FET) properties and conventional surface potential measurements and discussed in terms of the interfacial capacitance and charge exchange phenomena at the semiconductor/insulator interface. It was found that the use of Ta2O5 as a gate insulator is not only an effective way to reduce operating voltage of FET but also a useful way to investigate the interfacial capacitance which exists within a few nanometers at the semiconductor/gate insulator interface. The interfacial trap density, which is deeply associated with FET properties, was also discussed, taking into account the conventional capacitance measurement and the threshold voltage in FET properties. D 2005 Elsevier B.V. All rights reserved. Keywords: Organic field effect transistor; Polyimide; Tantalum oxide; Poly(3-hexylthiophene); Phthalocyanine; Charge-exchange phenomena
1. Introduction Thin-film organic field-effect transistors (OFET) are attractive devices for low-cost, low-performance and large area applications, such as active matrix organic displays and flexible integrated circuits, etc. [1 –5]. The solution-processable polymers are preferred to fabricate low-cost devices, and one promising class of materials for OFET applications is regioregular poly(3-hexylthiophene) (P3HT) [5– 8], while the low molecular organic semiconductors are also very important because they give higher mobility and reproducivility of the sample preparation [9– 14]. Since the reliability and the performance of OFETs are intimately related to their surface conditions, an understanding of the interfacial phenomena is of great importance to discuss the device operations. Since the measured capacitance varies as a function of the applied voltage and the trapped charges in the bulk semiconductor and at the insulator/semiconductor interface, the capacitance (or impedance) measurement with * Corresponding author. E-mail address: [email protected] (E. Itoh). 0040-6090/$ - see front matter D 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2005.07.028
the help of metal-insulator-semiconductor (MIS) diodes is intrinsically useful technique to investigate the charge phenomena in FETs. However, the capacitance change related to the interfacial traps, that is the interfacial capacitance, is usually difficult to observe because the thickness of interfacial layer become less than a few nanometers whereas the typical thickness of the gate insulator for OFETs is thicker than a few hundred nanometers resulting in a very small change in the capacitance value compared to gate capacitance. Moreover, since the cutoff frequencies due to the deeply trapped charge exchange observed at the semiconducor/insulator interface is normally below 100 Hz, sometimes below 1 Hz, the current signal in the capacitance measurement become sometimes below noise level [15]. On the other hand, the use of high dielectric constant (high K) materials and/or thinner films for the gate insulator are useful technique to reduce the operating voltage of OFETs [16 –18], however the effect is still controversial because a decrease in the field effect mobility with increasing the dielectric constant have been published in single crystal FETs [19]. Although not immediately obvious, the choice of high K gate dielectrics is also useful to investigate the interfacial
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charge phenomena because a reduction in equivalent thickness of the gate insulator enables to increase the signal from the interfacial capacitance as well as measured capacitance. Although many different insulators and semiconductors have been used for OFETs, few reports of a systematic study into the interactions between the insulator and the semiconductor have been published [20 –22]. In this study, we have investigated the electrical characteristics of metal-insulator semiconductor (MIS) capacitors consisting of typical p-type semiconductor layer, either P3HT [5 –8] or CuPc [9,10], and gate insulators. Since the thickness of interface region to be discussed here is very thin compared to gate insulator, we have employed the tantalum oxide (Ta2O5), with a high K dielectric constant (¨ 20), prepared by RF sputtering technique or double layered structure consisting of tantalum oxide and very thin polyimide layer to reduce the equivalent thickness of gate insulator. And then we have analyzed the capacitance to estimate the acceptor density profiles in semiconductor layer and the interfacial capacitance associated with the interfacial traps. These results have also been combined with FET properties and conventional surface potential measurements and then discussed in terms of the interfacial capacitance and charge exchange phenomena at the semiconductor/insulator interface.
2. Experimental details The process of fabricating the OFETs is as follows. Firstly, the gate electrodes consisting of a stack of Cr and Au (or Al) were deposited through a metal shadow mask by thermal evaporation. About 200-nm-thick Ta2O5 gate insulator was then deposited by rf magnetron sputtering from Ta target in argon atmosphere with a O2 fractions in the total gas (Ar + O2) of 30%. The substrate temperature was maintained at 100 -C and the sputtering gas was kept constant at 10 mTorr. The discharge power, the diameter of the target and the sputtering rate were 100 W, 4 in., and 100 nm/h. The second gate insulator, a 30-nm-thick Kapton type polyimide (PI), was then prepared by spin coating from the solutions of the polyimide precursor dissolved in N-methyl2-pyrrolidone (1.5 wt.%). The films were then cured at 300 -C for 2 h in a conventional oven under a nitrogen atmosphere. A 0.5 wt.% toluene solution of purified regioregular P3HT (MERCK) was then spun onto the insulator for P3HT based FET. The thickness of the P3HT was about 50 nm. For CuPc based FET, on the other hand, CuPc layer was evaporated in a vacuum. The pressure during evaporation was of the order of 10 6 Torr, and the evaporation rate was ¨ 0.1 nm/s. Several pairs of 2-mmwide, collinear gold stripes were then deposited by evaporation through a shadow mask onto the P3HT layer as source and drain electrodes. These electrodes were aligned perpendicular to the gate electrode. The resulting channel length L was 20 Am and the channel width W was 2
mm. Finally, the semiconductor layer was cut along the top gold stripes to prevent the lateral leakage current between the adjacent two samples. The large area of overlap of 4 mm2 between (source + drain) electrodes and the gate in this arrangement allowed capacitance –voltage measurements to be made on the same sample. A circular gold contact, with a diameter of 1.8 mm, surrounded by a concentric guard ring separated 75 Am was also prepared by conventional Flift off_ technique for comparison, that is, 20-nm-thick gold was evaporated onto a 400-nm-thick patterned photoresist layer prepared on P3HT layer or directly onto P3HT layer followed by the removal of photoresist/Au double layer in acetone. All measurements were carried out under vacuum and in the dark at 30 -C after heating at 100 -C for 1 h in order to remove residual solvent and/or adventitious dopants such as water and oxygen. The current– voltage (I – V) characteristics of the FET devices were measured using an electrometer (Keithley, Model 6517A) and a stabilized power supply. Capacitance –voltage (C –V) measurements were made with a conventional LCR meter (Agilent model 4284A). The surface potential built across the electrode/ insulator and electrode/semiconductor interfaces was measured under vacuum using a vibrating probe voltmeter (TREK model 320B). For surface potential measurements, films were deposited over one-half of a clean gold (Au) or ITO electrode, thus enabling the surface potential of structures to be measured with reference to the uncoated section of the electrodes.
3. Results and discussions 3.1. P3HT-based FETs Fig. 1 shows the output characteristics (I DS –V DS) of the P3HT-based FET with a 25-Am-long channel prepared on 350- nm-thick PI layer. Significant drain currents were
Fig. 1. Output characteristics (I DS – V DS) of P3HT-FET prepared on a 350nm-thick PI with channel width, W, of 1.6 mm and channel length, L, of 25 Am.
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observed even for positive V G, although these became negligible for V GS > +40 V. The drain currents in the PIFETs do not fully saturate for large negative voltage. From the transfer characteristics (I DS – V GS) of P3HT-PI FET, we deduced that V T = 25 V, which varies from + 20 V to + 30 V between the samples, and l P3HT = 6.1 10 3 cm2/V s (not shown here) [22]. Fig. 2 shows the output characteristics of the P3HT-based FET with a 20-Am-long channel prepared on the double layered insulator consisting of 200-nm-thickTa2O5 and 30-nm-thick PI layers. Of interest in Fig. 2 is much lower operation voltage compared to Fig. 1 and shows good saturation behavior for V GS > 3 V. Fig. 3 shows the transfer characteristics (I DS1/2 vs. V GS) of this device, after correcting for the small leakage current through the gate insulator. The curves superimpose for V DS = 4, 6 and 8 in the voltage range 2 < V GS < 2 V reflecting the good saturation seen in Fig. 2. The field effect mobility, l P3HT, and the threshold voltage, V T, are deduced to be 3.8 10 3 cm2/V s and + 2 V, respectively. It should be noted here that l P3HT and V T were deduced to be 2– 3 10 3 cm2/V s and 1.8 V, respectively, in P3HT-based FET prepared on 200nm-thick Ta2O5 gate insulator (not shown). A negative value of threshold voltage in P3HT on Ta2O5 single layer probably suggests the existence of relatively high density of interfacial trap in the forbidden states at the P3HT/Ta2O5 interface. The work-function difference of ¨ 0.3 eV between P3HT [22] and the gate electrode should be also taken into account to discuss the threshold voltage shift, though it is much smaller than measured threshold voltage of 1.8 V. On the other hand, a large positive threshold voltage shift of about DV T ¨ + 4 V in P3HT-based FET on Ta2O5/PI gate insulator compared to that of Ta2O5 gate is presumably due to the interfacial trapped charges at the P3HT/insulator interface. In our previous study, it was reported that such a positively voltage shift in P3HT-based FET prepared on PI was ascribed to the charge exchange phenomena at the
Fig. 2. Output characteristics (I DS – V DS) of the P3HT-FET prepared on the double layered insulator consisting of 200 nm-thick Ta2O5 and 30-nm-thick PI with channel width, W, of 2 mm and channel length, L, of 20 Am.
97
Fig. 3. Transfer characteristics (I DS – V GS) of the 20-Am-long channel P3HT-FET prepared on the double layered insulator consisting of 200-nmthick Ta2O5 and 30-nm-thick PI.
electron accepting PI and electron donating P3HT layers [21,22]. Since the surface potential measurement revealed that the surface potential of PI and P3HT thin film with respect to ITO reference electrode is 0.28 V and + 0.33 V, respectively, there is a fixed negative charges in PI interfacial layer and hence a positive charges in P3HT due to the displacement of electron from P3HT into PI layers. The difference in above mentioned DV T and V T value (¨ 25 V) in P3HT on 350 nm-thick PI may be ascribed to reduction of equivalent thickness of insulator from 350 nm to 60 nm in P3HT FET on Ta2O5/PI gate, which is calculated as ( 0( PIA/C. Here ( 0 is the permittivity in vacuum, ( PI ¨ 3 is the relative dielectric constant, A is the electrode area, and C is the measured insulator capacitance. Fig. 4 compares the frequency dependence of capacitance as a function of gate voltage in (a) sample A: 350-nmthick PI/50-nm-thick P3HT MIS capacitor, and (b) sample B: 200-nm-thick Ta2O5/30-nm-thick PI/50 nm-thick-P3HT MIS capacitor. Here, the electrode area of sample B is 4 mm2 and the shape of semiconductor layer is patterned by cutting the semiconductor along the top gold stripes, whereas the electrode area of sample A is about 1.2 mm2 and it was not defined. In sample B, drain and source electrodes were connected together to reduce the effect of lateral leakage current between source and drain electrodes. It is apparent from Fig. 4 that the capacitance value of sample B is about 15 times larger than that of sample A at the frequency range between 102 and 104 Hz due to the increase in gate insulator capacitance. In each sample, the capacitance decreases with frequency and gate voltage V G, and it falls quickly the frequency around 104 Hz due to the Maxwell-Wagner dispersion (also known as ‘‘interfacial polarization’’ or ‘‘space charge polarization’’) of two different dielectric materials [23,24]. These results are easily explained using the equivalent circuit in Fig. 5(a) in accumulation, that is at the voltages V G < V T. Here C I is the insulator capacitance, C B and R B are the capacitance and
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Fig. 6. The capacitance – voltage characteristics of Au/200-nm-thick Ta2O5/ 50-nm-thick P3HT MIS capacitor as a function of measured frequency.
Fig. 4. Voltage and frequency dependences of capacitance C measured at 30 -C in (a) ITO/350-nm-thick PI/50-nm-thick P3HT MIS capacitor and in (b) Au/200-nm-thick Ta2O5/50-nm-thick P3HT MIS capacitor.
resistance of the bulk P3HT, and R S is a small series resistance associated with the electrodes. The relaxation frequency of the circuit, f R, is given by [21] fR ¼
1 : 2pRB ðC1 þ CB Þ
ð1Þ
For frequencies f b f R, the measured capacitance converges to C I ¨ 1.8 nF in sample B, on the other hand, the measured capacitance increases with decreasing frequency unlimitedly in sample A and it exceeds C I ¨ 110 pF. It is simply due to a spreading out of accumulated holes along P3HT/insulator interface on top of the gate electrode in sample A. Such an abnormal capacitance increase can be suppressed successfully by patterning the semiconductor layer with the help of shadow mask or just cutting the
semiconductor into desired shape before use, or the use of circular gold contact surrounded by a concentric guard ring connected to the ground. We have therefore adopted the patterned electrodes in all other samples will be discussed below. Fig. 6 shows the capacitance –voltage characteristics of sample B as a function of measured frequency. The capacitance remains almost constant in accumulation and it decreases steeply at the voltage region between + 2 and + 6 V. The capacitance becomes constant above + 6 V and it is almost independent of frequency. The capacitance value corresponds well with the series capacitance of the insulator and the P3HT depletion layer capacitance supporting that the film thickness of P3HT is 40 nm and the relative dielectric constant of Ta2O5, PI and P3HT as 20, 3, and 3.2 [20]. Of interest in Fig. 5 is that the capacitance starts to decrease at around V T ¨ 2 V deduced in Fig. 3, that is, the P3HT layer starts to deplete above V T ¨ + 2 V and it is completely depleted at +6 V. Moreover, it should be pointed out that the capacitance change at 1 kHz, for example, by V GS change is about 800 pF, and it is about 60 times larger
Fig. 5. Equivalent circuits for the device (a) in accumulation, (b) partially depleted, (c) incorporating interfacial states at the lower frequency lower than the relaxation frequency f R, and (d) the equivalent circuit of Fig. 5(c) converted into a frequency dependent capacitance C P in parallel with a frequency-dependent conductance G P.
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believe that bulk space charge contributes little in Eq. (2) and that the main contributor to the large values of V T observed in sample B comes from fixed negative charges in PI interfacial layer and partially from work-function difference. The net trapped charge density is estimated to be ¨ 5 1011 cm 2 from Fig. 5 and Eq. (2), and it becomes ¨ 1012 cm 2 if the total DV T with reference to V T in the P3HT-based FET prepared on single layer of Ta2O5 is taken into account. It is therefore suggested here that the capacitance measurement associated with FET properties is powerful method to investigate the electrical properties of P3HT-based FET, which is fabricated on Ta2O5 or double layered insulator. 3.2. CuPc-based FETs
Fig. 7. (a) Output characteristics (I DS – V DS) of the CuPc-FET prepared on 200-nm-thick Ta2O5 with channel width, W, of 2 mm and channel length, L, of 20 Am, where CuPc is evaporated only on the overlapping area of gate and the Au top stripes for drain and source electrodes by shadow mask. (b) Output characteristics (I DS – V DS) of CuPc-FET with ring electrode prepared on 200-nm-thick Ta2O5. The top Au electrodes with width, W, of 5.65 mm and channel length, L, of 75 Am were patterned by lift-off technique.
than that of sample A of ¨13 pF. The use of Ta2O5 layer or double layered insulator is thus a very effective way to investigate the electrical properties of MIS capacitor. Several possible factors can cause the shift DV T in the threshold voltage for P3HT-based FETs, for example, the work function difference, / MS, between gate electrode and semiconductor, a space charge in the bulk region of the insulator, and charges trapped in states at the insulator/ semiconductor interface. Their contributions to DV T are described by [15] Z dI / 1 Qit ð/s Þ DVT ¼ M S xqð xÞdx ; ð2Þ eS e0 0 CI q where q(x) is the space charge density in the insulator and C i is the insulator capacitance per unit area. Q it(/ S) is the net charge per unit area trapped in interface states and is a function of the degree of band bending at the interface and hence the potential / S of the semiconductor surface. The work function difference between gate Au electrode and P3HT is only ¨ 0.3 eV from the conventional surface potential measurement and therefore, makes a small contribution of / MS/q to the large DV T observed. Space charges can arise in the insulator from mobile ionic species and from trapped electronic charges. According to the previous studies, the excess charges or trapped charges in the bulk insulator is likely to be small enough since the excess charges in bulk insulator was removed during the heattreatment even in a 350-nm-thick PI and showed little change in V T at room temperature [21,22]. Therefore, we
Fig. 7(a) shows the output characteristics (I DS – V DS) of the 50 nm-thick-CuPc based FET with a 20-Am-long channel prepared on 200-nm-thick Ta2O5 gate insulator. Here, CuPc layer is evaporated only on the overlapping area of gate electrode and the Au top stripe evaporated for source and gate electrodes by shadow-mask to prevent the lateral leakage current between the adjacent devices. Fig. 7(a) shows good saturation behavior and a good ON/OFF ratio 1/2 of about 105. Fig. 8(a) shows the transfer characteristics (I DS vs. V GS) of the device used in Fig. 7(a). The field effect mobility, l CuPc, and the threshold voltage, V T, are deduced to be 4.0 10 3 cm2/V s and 1.5 V, respectively. The l CuPc obtained here is in the high-end of the reported values as CuPc [9,10]. Fig. 7(b) shows the output characteristics (I DS –V DS) of the 40-nm-thick CuPc based FET with a 75-Am-long concentric type channel prepared by Flift off_ technique on
Fig. 8. Transfer characteristics of the CuPc-FET patterned by (a) shadow mask and (b) lift-off technique.
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Fig. 9. The capacitance – voltage characteristics of Al/200-nm-thick Ta2O5/ 50-nm-thick CuPc MIS capacitor patterned by shadow mask as a function of measured frequency.
200-nm-thick Ta2O5 gate insulator. Here, the channel length L and the channel width W are 75 Am and 5650 Am, respectively. Here, the inner circular electrode was connected to source and the outer guard electrode was connected to drain electrodes, respectively. The drain current decreases about 1 order of magnitude compared to the device patterned by shadow-mask even though the W/L ratio decreases only by 25%. Fig. 8(b) shows the transfer 1/2 characteristics (I DS vs. V GS) of this device, after correcting for the small leakage current through the gate insulator. The field effect mobility, l CuPc, and the threshold voltage, V T, are deduced to be 5.6 10 4 cm 2/Vs and + 1.5 V, respectively. Of interest in Fig. 8(b) is the large subthreshold current for V GS > V T. That is, the CuPc-based FET prepared by conventional lift-off technique is not only damage the interface but also deteriorates the device stability. Figs. 9 and 10 show the voltage dependence of the capacitance and the loss, which is defined as the measured conductance G divided by angular frequency x, G/x, as a function of frequency. Here, the ratio of the measured capacitance to loss coincides with the ratio of real part to imaginary part of dielectric constant. The capacitance decreases with the gate voltage and then becomes constant for large positive V GS in both Figs. 9 and 10. Capacitance values also decreased with frequency, and an additional increase in the capacitance is observed at low frequency in the accumulation mode. It should be noted here that the calculated value of the Ta2O5 gate insulator is estimated to be ¨ 3150 pF for the CuPc-FET patterned by shadow mask in Fig. 9, whereas it becomes ¨ 2300 pF for the device patterned by lift-off in Fig. 10. That is, the measured capacitance coincides with the gate capacitance at only very low frequency region under accumulation. The capacitance
remains constant below the threshold voltage V T deduced from Fig. 8, and then decreases quickly above V T. A marked loss peak is also observed in this region. It is noted here that the deference in peak-voltage between Figs. 9 and 10 corresponds well with the threshold voltage difference in these devices. In Fig. 10, CuPc layer is fully depleted at + 7 V and the capacitance value becomes the series capacitance of C I and C d = ( 0( SA/d. Here, the ( S is the relative dielectric constant of CuPc ¨ 3 and d is the thickness of CuPc layer. Of interest is that this voltage coincides well with the voltage when the CuPc-based FET prepared by Flift-off_ technique becomes Foff state_ completely. The subthreshold current in Fig. 8(b) is therefore considered to be the JFET effect, that is, the current flows in the undepleted bulk [25] presumably due to the additional impurity formed during the photolithography process. It is therefore concluded that the use of C – V measurement with either patterned semiconductor or patterned ring electrode is suitable to discuss the electrical properties of OFETs, however, Flift-off_ techniques may damage the semiconductor even a stable semiconductor such as CuPc seriously. Fig. 11 shows the frequency dependence of the capacitance and the loss at V G = 6 V and V G = 0 V at the temperatures of 30, 50 and 70 -C in the device patterned by lift-off technique. It is clearly shown that there are two steps in the dispersion of capacitance and thus there are two remarkable peaks in the loss curve, and their frequency increases with temperature. It is interestingly to note that each capacitance value converges to the same value, the capacitance of the capacitance of the gate oxide ¨ 2300 pF, at low frequency. Similar behaviors were also observed in CuPc-FET patterned by shadow mask,
Fig. 10. The capacitance – voltage characteristics of Al/200-nm-thick Ta2O5/40-nm-thick CuPc MIS capacitor patterned by lift-off technique as a function of measured frequency.
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dependent capacitance C P in parallel with a frequencydependent conductance G P, as shown in Fig. 5(d). The values of C P and G P are described as [15,26], CP ¼ CD þ
CS ; 1 þ x 2 s2
ð3Þ
and GP CS xs ¼ : 1 þ x 2 s2 x
Fig. 11. The frequency dependences of capacitance C measured at 30, 50 and 70 -C Al/200-nm-thick Ta2O5/40-nm-thick CuPc MIS capacitor patterned by lift-off technique at V G = 6 V and 0 V.
however, the peak frequencies became higher than those of Fig. 11. The higher frequency peak in Fig. 11 is ascribed to the Maxwell-Wagner polarization discussed in Section 3.1, whereas the dispersion at low frequency region is considered in terms of the interfacial traps. If the influence of interfacial capacitance related to the interfacial trapped charge is negligibly small, the equivalent circuit of MIS capacitor will be described as Fig. 5(b) at the voltage larger than V T. And thus the measured capacitance C changes as a function of the gate voltage between C I and the series capacitance of C I and C d. The basic equivalent circuit incorporating the interface trap effect is shown in Fig. 5(c) for f b f R in Eq. (1) assuming the impedance of the parallel branch of the bulk capacitance and resistance is negligibly small. Here C it and R it are the capacitance and resistance associated with the interface traps, and are the functions of build-up potential at the interface. The product C SR S is the interface-trap lifetime. The low frequency peak in Fig. 11 is thus a strong evidence of interfacial capacitance [15,26]. From surface analysis of Ta2O5 by AFM (SHIMADZU SPM-9500J), the surface image of Ta2O5 is displaying a rather coarse, granular structure and the rootmean-square (rms) roughness of 2.1 nm was observed over a 1 Am 1 Am area (not shown). Such a structural disorder at the Ta2O5 surface may produce the deep, high density of interfacial traps. Further investigation should be investigated in the near future related to the interfacial roughness. 3.3. Analysis of capacitance curves The parallel branch of the equivalent circuit of equivalent circuit in Fig. 5(c) will be converted to a frequency-
ð4Þ
Here, s is the interface-trap lifetime C SR S. Since Eq. (4) does not contain C D and depends only on the interfacial trap branch of the equivalent circuit in Fig. 5(d). A plot of G P/x at the maximum is C S/2. And once C S is known, the interfacial-trap density is obtained by using the relation D it = C S/qA. After subtracting the reactance of the insulator capacitance from measured impedance and converted back into the admittance, the value of G P is estimated. The interface-trap density D it is thus calculated from the C – V and the loss curve G/x (loss) – V curves using the following relation [26,27]: #1 " 2 Gmax Gmax 2 Cmax 2 Dit ¼ þ 1 ; ð5Þ qA x xCI CI where q is the electronic charge, G max/x is the peak value of the loss and C max is the capacitance corresponding to G max. From C–V and the loss –V curves in Figs 9 and 10, the D it values is estimated as 8.2 1011 eV 1 cm 2 for CuPc-FET patterned by lift-off, whereas it is estimated as 2.8 1011 eV 1 cm 2 for CuPc-FET patterned by shadow mask, respectively. The larger value of D it estimated here in the device patterned by lift-off may thus cause the smaller value of the field effect mobility in Fig. 8. Generally, the C – V characteristics depends on the density and the depth profile of the acceptors in p-type semiconductors, such as CuPc and P3HT. According to the Mott-Schottky analysis, the capacitance at a certain gate bias corresponds to the depletion depth, d depl, in the semiconductor layer by: ddepl ¼ e0 es A=ð1=C 1=CI Þ:
ð6Þ
Eq. (6) may hold when the contribution of the interfacial capacitance and minority carriers can be disregarded or they are incorporated to the depletion layer capacitance C D. The acceptor density, N A, at the depletion edge x at the given voltage determined using the Mott-Schottky relation [15,26]: NA ¼
2 qe0 eS A2
1 2 BCHF BVGS
;
ð7Þ
where C HF is the MIS high-frequency capacitance below the Maxwell-Wagner relaxation frequency f R discussed in Eq. (1). When the interface states (or traps) are present they affect the slope of the 1/C 2HF vs. V curves, that is, the
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interfacial capacitance or depletion layer capacitance which is difficult to cancel out, and it is estimated as 19 nF for P3HT FET prepared on Ta2O5/PI double layer and 30 nF for CuPc FET prepared by shadow mask. By substituting these values into (C depl + C it ) in conventional equation of subthreshold swing S [15,26]: Cdepl þ Cit BVGS kT ln10 1 þ Su , ; BðlogIDS Þ q CI
Fig. 12. The corrected doing profiles obtained from Eq. (8) for CuPc- and P3HT-MIS capacitors calculated from the capacitance curves at 100 Hz and 3 kHz, respectively, from Figs. 6, 9 and 10). Only C LC of CuPc-MIS capacitor patterned by lift-off was calculated from C – V curve at 30 Hz.
ð10Þ
S values are estimated as 1.0 V/dec for P3HT FET and 0.64 V/dec for CuPc FET, corresponds well to the experimental values of 0.93 V/dec and 0.82 V/dec from transfer characteristics, respectively. It is therefore predicted here that S value will be improved more using smooth, clean high K gate dielectric thin film as an gate insulator and decreasing the interfacial capacitance.
4. Conclusion interfacial states causes the Fstretch-out_ of C – V curves. According to Brews [28], this stretch-out effect can be easily corrected by using following equation whether or not interface states are present: !1 2 1 CLF =CI dð1=CHF Þ2 NAV ¼ ; ð8Þ qe0 eS A2 1 CHF =CI dV where C LF is the quasi-static low-frequency capacitance obtained by C – V measurement corresponding to C HF. In Eq. (8), the range of distance for which the doping profile can be determined to within 5% accuracy is x > 3L D, where L D is the bulk (extrinsic) Debye length [15]: 1=2 LD ¼ kT e0 eS =q2 NAV :
ð9Þ
Fig. 12 shows the corrected doing profiles obtained from Eq. (8) for CuPc- and P3HT-MIS capacitors calculated from the capacitance curves at 100 Hz and 3 kHz, respectively, from Figs. 6, 9 and 10. Only C LC of CuPc-MIS capacitor patterned by lift-off was calculated from C–V curve at 30 Hz because it gives the low frequency dispersion at the frequency around 100 Hz. A very high density of acceptor states is calculated in the vicinity of the insulator/semiconductor interface and it decreases steeply within 10 nm from the interface in Fig. 12. Here the bulk acceptor densities are estimated as approximately 3 1023 m 3 for CuPc and 1 1023 m 3 for P3HT from the rough average of N A between x = 15 and 30 nm, and thus L D are roughly estimated as 6.2 nm for P3HT and 3.8 nm for CuPc, respectively. Therefore, this fast decrease in N A may be ascribed to the stretching-out of carriers at the interface. The distribution of interface states should also be taken into account since N A decreases too fast and it is still decreasing at the distance larger than 3L D. From the minimum values of d depl in Eq. (6) and Fig. 12, one can estimate the very large
We have investigated the electrical characteristics of metal-insulator semiconductor (MIS) capacitors consisting of p-type semiconductor layer, either regio-regular poly(3hexylthiophene) (P3HT) or copper-phthalocyanine (CuPc) prepared on the tantalum oxide, with a high dielectric constant (¨ 20), or double layered structure consisting of tantalum oxide and very thin polyimide. These results are combined with FET properties and conventional surface potential measurements and discussed in terms of the interfacial capacitance and charge exchange phenomena at the semiconductor/insulator interface. The use of Ta2O5 layer as an insulator is not only an effective way to reduce operating voltage of field effect transistor but also a useful way to investigate the capacitance change ascribed to the interfacial capacitance or the interfacial electronic states at the interface. From capacitance measurement, the voltage when the capacitance starts to decrease coincides well with the threshold voltage of FET, V T, and the CuPc FET patterned by lift-off technique can be completely turn-off only when the MIS capacitor is fully depleted due to the large JFET current. The positive shift of threshold voltage in P3HT FET prepared on PI is discussed in terms of the interfacial fixed charges due to the charge exchange between the electron accepting PI and electron donating P3HT. And such a voltage shift and the loss peak in the loss – V curves were explained in terms of interfacial trap density. Finally, the acceptor-profile in semiconductors was also calculated. It was found that very high density of states exists at the insulator/semiconductor interface and it decreases very quickly suggesting the large density of interfacial traps exist and it produces the large interfacial capacitance. The large interfacial capacitance may cause the large subthreshold swing and it can be reduced by using high K gate dielectric thin film and reducing the interfacial capacitance.
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Acknowledgements The authors acknowledge useful discussions with D.M. Taylor, I. Torres, T. Murayama, and T. Highchi. This work was supported by the CLUSTER of the Ministry of Education, Culture, Sports, Science and Technology, Japan.
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[10] S. Hoshino, T. Kamata, K. Yase, J. Appl. Phys. 92 (2002) 6028. [11] S.F. Nelson, Y.-Y. Lin, D.J. Gundlach, T.N. Jackson, Appl. Phys. Lett. 72 (1998) 1854. [12] C.D. Dimitrakopoulos, P.R.L. Malenfant, Adv. Mater. 14 (2000) 99. [13] V. Podzorov, S.E. Sysoev, E. Loginova, V.M. Pudalov, M.E. Gershenson, Appl. Phys. Lett. 83 (2003) 3504. [14] V.C. Sundar, J. Zaumseil, V. Podzorov, E. Menard, R.L. Willett, T. Someya, M.E. Gershenson, J.A. Rogers, Science 303 (2004) 1644. [15] S.M. Sze, Physics of Semiconductor Devices, 2nd edR, Wiley, 1981. [16] J. Tate, J.A. Rogers, C.D.W. Jones, B. Vyas, D.W. Murphy, W.J. Li, Z. Bao, R.E. Slusher, A. Dodabalapur, H.E. Katz, Langmuir 16 (2000) 6054. [17] Y. Iino, Y. Inoue, Y. Fujisaki, H. Fujikake, H. Sato, M. Kawakita, S. Tokito, H. Kikuchi, Jpn. J. Appl. Phys. 42 (2003) 299. [18] G. Wang, D. Moses, A.J. Heeger, H.M. Zhang, M. Narasimhan, R.E. Demaray, J. Appl. Phys. 95 (2004) 316. [19] A.F. Stassen, R.W.I. de Boer, N.N. Iosad, A.F. Morpurgo, Appl. Phys. Lett. 85 (2004) 3899. [20] S. Scheinert, W. Schliefke, Synth. Met. 139 (2003) 501. [21] I. Torres, D.M. Taylor, E. Itoh, Appl. Phys. Lett. 85 (2004) 314. [22] E. Itoh, I. Torres, D.M. Taylor, Jpn. J. Appl. Phys. 44 (2005) 641. [23] A. von Hippel, Dielectric and Waves, Wiley, New York, 1954. [24] K. Miyairi, Jpn. J. Appl. Phys., Part 1 37 (1998) 4900. [25] E.J. Meijer, C. Deteheverry, P.J. Baesjou, E. van Veenendaal, D.M. de Leeuw, T.M. Klapwijk, J. Appl. Phys. 93 (2003) 4831. [26] E.H. Nicollian, J.R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology, Wiley, NewYork, 1982. [27] W.A. Hill, C.C. Coleman, Solid-State Electron. 23 (1980) 987. [28] J.R. Brews, J. Appl. Phys. 44 (1973) 3228.
Interfacial charge phenomena at the semiconductor/gate insulator interface in organic field effect transistors Eiji Itoh *, Keiichi Miyairi Department of Electrical and Electronic Engineering, Shinshu University, 4-17-1, Wakasato, Nagano 380-8553, Japan Available online 8 August 2005
Abstract We have investigated the electrical characteristics of metal-insulator-semiconductor (MIS) capacitors consisting of p-type semiconductor layer, either regio-regular poly(3-hexylthiophene) (P3HT) or copper-phthalocyanine (CuPc) prepared on tantalum oxide, with a high dielectric constant (¨ 20), or double layered structure consisting of tantalum oxide and polyimide thin films. These results are combined with field effect transistor (FET) properties and conventional surface potential measurements and discussed in terms of the interfacial capacitance and charge exchange phenomena at the semiconductor/insulator interface. It was found that the use of Ta2O5 as a gate insulator is not only an effective way to reduce operating voltage of FET but also a useful way to investigate the interfacial capacitance which exists within a few nanometers at the semiconductor/gate insulator interface. The interfacial trap density, which is deeply associated with FET properties, was also discussed, taking into account the conventional capacitance measurement and the threshold voltage in FET properties. D 2005 Elsevier B.V. All rights reserved. Keywords: Organic field effect transistor; Polyimide; Tantalum oxide; Poly(3-hexylthiophene); Phthalocyanine; Charge-exchange phenomena
1. Introduction Thin-film organic field-effect transistors (OFET) are attractive devices for low-cost, low-performance and large area applications, such as active matrix organic displays and flexible integrated circuits, etc. [1 –5]. The solution-processable polymers are preferred to fabricate low-cost devices, and one promising class of materials for OFET applications is regioregular poly(3-hexylthiophene) (P3HT) [5– 8], while the low molecular organic semiconductors are also very important because they give higher mobility and reproducivility of the sample preparation [9– 14]. Since the reliability and the performance of OFETs are intimately related to their surface conditions, an understanding of the interfacial phenomena is of great importance to discuss the device operations. Since the measured capacitance varies as a function of the applied voltage and the trapped charges in the bulk semiconductor and at the insulator/semiconductor interface, the capacitance (or impedance) measurement with * Corresponding author. E-mail address: [email protected] (E. Itoh). 0040-6090/$ - see front matter D 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2005.07.028
the help of metal-insulator-semiconductor (MIS) diodes is intrinsically useful technique to investigate the charge phenomena in FETs. However, the capacitance change related to the interfacial traps, that is the interfacial capacitance, is usually difficult to observe because the thickness of interfacial layer become less than a few nanometers whereas the typical thickness of the gate insulator for OFETs is thicker than a few hundred nanometers resulting in a very small change in the capacitance value compared to gate capacitance. Moreover, since the cutoff frequencies due to the deeply trapped charge exchange observed at the semiconducor/insulator interface is normally below 100 Hz, sometimes below 1 Hz, the current signal in the capacitance measurement become sometimes below noise level [15]. On the other hand, the use of high dielectric constant (high K) materials and/or thinner films for the gate insulator are useful technique to reduce the operating voltage of OFETs [16 –18], however the effect is still controversial because a decrease in the field effect mobility with increasing the dielectric constant have been published in single crystal FETs [19]. Although not immediately obvious, the choice of high K gate dielectrics is also useful to investigate the interfacial
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charge phenomena because a reduction in equivalent thickness of the gate insulator enables to increase the signal from the interfacial capacitance as well as measured capacitance. Although many different insulators and semiconductors have been used for OFETs, few reports of a systematic study into the interactions between the insulator and the semiconductor have been published [20 –22]. In this study, we have investigated the electrical characteristics of metal-insulator semiconductor (MIS) capacitors consisting of typical p-type semiconductor layer, either P3HT [5 –8] or CuPc [9,10], and gate insulators. Since the thickness of interface region to be discussed here is very thin compared to gate insulator, we have employed the tantalum oxide (Ta2O5), with a high K dielectric constant (¨ 20), prepared by RF sputtering technique or double layered structure consisting of tantalum oxide and very thin polyimide layer to reduce the equivalent thickness of gate insulator. And then we have analyzed the capacitance to estimate the acceptor density profiles in semiconductor layer and the interfacial capacitance associated with the interfacial traps. These results have also been combined with FET properties and conventional surface potential measurements and then discussed in terms of the interfacial capacitance and charge exchange phenomena at the semiconductor/insulator interface.
2. Experimental details The process of fabricating the OFETs is as follows. Firstly, the gate electrodes consisting of a stack of Cr and Au (or Al) were deposited through a metal shadow mask by thermal evaporation. About 200-nm-thick Ta2O5 gate insulator was then deposited by rf magnetron sputtering from Ta target in argon atmosphere with a O2 fractions in the total gas (Ar + O2) of 30%. The substrate temperature was maintained at 100 -C and the sputtering gas was kept constant at 10 mTorr. The discharge power, the diameter of the target and the sputtering rate were 100 W, 4 in., and 100 nm/h. The second gate insulator, a 30-nm-thick Kapton type polyimide (PI), was then prepared by spin coating from the solutions of the polyimide precursor dissolved in N-methyl2-pyrrolidone (1.5 wt.%). The films were then cured at 300 -C for 2 h in a conventional oven under a nitrogen atmosphere. A 0.5 wt.% toluene solution of purified regioregular P3HT (MERCK) was then spun onto the insulator for P3HT based FET. The thickness of the P3HT was about 50 nm. For CuPc based FET, on the other hand, CuPc layer was evaporated in a vacuum. The pressure during evaporation was of the order of 10 6 Torr, and the evaporation rate was ¨ 0.1 nm/s. Several pairs of 2-mmwide, collinear gold stripes were then deposited by evaporation through a shadow mask onto the P3HT layer as source and drain electrodes. These electrodes were aligned perpendicular to the gate electrode. The resulting channel length L was 20 Am and the channel width W was 2
mm. Finally, the semiconductor layer was cut along the top gold stripes to prevent the lateral leakage current between the adjacent two samples. The large area of overlap of 4 mm2 between (source + drain) electrodes and the gate in this arrangement allowed capacitance –voltage measurements to be made on the same sample. A circular gold contact, with a diameter of 1.8 mm, surrounded by a concentric guard ring separated 75 Am was also prepared by conventional Flift off_ technique for comparison, that is, 20-nm-thick gold was evaporated onto a 400-nm-thick patterned photoresist layer prepared on P3HT layer or directly onto P3HT layer followed by the removal of photoresist/Au double layer in acetone. All measurements were carried out under vacuum and in the dark at 30 -C after heating at 100 -C for 1 h in order to remove residual solvent and/or adventitious dopants such as water and oxygen. The current– voltage (I – V) characteristics of the FET devices were measured using an electrometer (Keithley, Model 6517A) and a stabilized power supply. Capacitance –voltage (C –V) measurements were made with a conventional LCR meter (Agilent model 4284A). The surface potential built across the electrode/ insulator and electrode/semiconductor interfaces was measured under vacuum using a vibrating probe voltmeter (TREK model 320B). For surface potential measurements, films were deposited over one-half of a clean gold (Au) or ITO electrode, thus enabling the surface potential of structures to be measured with reference to the uncoated section of the electrodes.
3. Results and discussions 3.1. P3HT-based FETs Fig. 1 shows the output characteristics (I DS –V DS) of the P3HT-based FET with a 25-Am-long channel prepared on 350- nm-thick PI layer. Significant drain currents were
Fig. 1. Output characteristics (I DS – V DS) of P3HT-FET prepared on a 350nm-thick PI with channel width, W, of 1.6 mm and channel length, L, of 25 Am.
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observed even for positive V G, although these became negligible for V GS > +40 V. The drain currents in the PIFETs do not fully saturate for large negative voltage. From the transfer characteristics (I DS – V GS) of P3HT-PI FET, we deduced that V T = 25 V, which varies from + 20 V to + 30 V between the samples, and l P3HT = 6.1 10 3 cm2/V s (not shown here) [22]. Fig. 2 shows the output characteristics of the P3HT-based FET with a 20-Am-long channel prepared on the double layered insulator consisting of 200-nm-thickTa2O5 and 30-nm-thick PI layers. Of interest in Fig. 2 is much lower operation voltage compared to Fig. 1 and shows good saturation behavior for V GS > 3 V. Fig. 3 shows the transfer characteristics (I DS1/2 vs. V GS) of this device, after correcting for the small leakage current through the gate insulator. The curves superimpose for V DS = 4, 6 and 8 in the voltage range 2 < V GS < 2 V reflecting the good saturation seen in Fig. 2. The field effect mobility, l P3HT, and the threshold voltage, V T, are deduced to be 3.8 10 3 cm2/V s and + 2 V, respectively. It should be noted here that l P3HT and V T were deduced to be 2– 3 10 3 cm2/V s and 1.8 V, respectively, in P3HT-based FET prepared on 200nm-thick Ta2O5 gate insulator (not shown). A negative value of threshold voltage in P3HT on Ta2O5 single layer probably suggests the existence of relatively high density of interfacial trap in the forbidden states at the P3HT/Ta2O5 interface. The work-function difference of ¨ 0.3 eV between P3HT [22] and the gate electrode should be also taken into account to discuss the threshold voltage shift, though it is much smaller than measured threshold voltage of 1.8 V. On the other hand, a large positive threshold voltage shift of about DV T ¨ + 4 V in P3HT-based FET on Ta2O5/PI gate insulator compared to that of Ta2O5 gate is presumably due to the interfacial trapped charges at the P3HT/insulator interface. In our previous study, it was reported that such a positively voltage shift in P3HT-based FET prepared on PI was ascribed to the charge exchange phenomena at the
Fig. 2. Output characteristics (I DS – V DS) of the P3HT-FET prepared on the double layered insulator consisting of 200 nm-thick Ta2O5 and 30-nm-thick PI with channel width, W, of 2 mm and channel length, L, of 20 Am.
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Fig. 3. Transfer characteristics (I DS – V GS) of the 20-Am-long channel P3HT-FET prepared on the double layered insulator consisting of 200-nmthick Ta2O5 and 30-nm-thick PI.
electron accepting PI and electron donating P3HT layers [21,22]. Since the surface potential measurement revealed that the surface potential of PI and P3HT thin film with respect to ITO reference electrode is 0.28 V and + 0.33 V, respectively, there is a fixed negative charges in PI interfacial layer and hence a positive charges in P3HT due to the displacement of electron from P3HT into PI layers. The difference in above mentioned DV T and V T value (¨ 25 V) in P3HT on 350 nm-thick PI may be ascribed to reduction of equivalent thickness of insulator from 350 nm to 60 nm in P3HT FET on Ta2O5/PI gate, which is calculated as ( 0( PIA/C. Here ( 0 is the permittivity in vacuum, ( PI ¨ 3 is the relative dielectric constant, A is the electrode area, and C is the measured insulator capacitance. Fig. 4 compares the frequency dependence of capacitance as a function of gate voltage in (a) sample A: 350-nmthick PI/50-nm-thick P3HT MIS capacitor, and (b) sample B: 200-nm-thick Ta2O5/30-nm-thick PI/50 nm-thick-P3HT MIS capacitor. Here, the electrode area of sample B is 4 mm2 and the shape of semiconductor layer is patterned by cutting the semiconductor along the top gold stripes, whereas the electrode area of sample A is about 1.2 mm2 and it was not defined. In sample B, drain and source electrodes were connected together to reduce the effect of lateral leakage current between source and drain electrodes. It is apparent from Fig. 4 that the capacitance value of sample B is about 15 times larger than that of sample A at the frequency range between 102 and 104 Hz due to the increase in gate insulator capacitance. In each sample, the capacitance decreases with frequency and gate voltage V G, and it falls quickly the frequency around 104 Hz due to the Maxwell-Wagner dispersion (also known as ‘‘interfacial polarization’’ or ‘‘space charge polarization’’) of two different dielectric materials [23,24]. These results are easily explained using the equivalent circuit in Fig. 5(a) in accumulation, that is at the voltages V G < V T. Here C I is the insulator capacitance, C B and R B are the capacitance and
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Fig. 6. The capacitance – voltage characteristics of Au/200-nm-thick Ta2O5/ 50-nm-thick P3HT MIS capacitor as a function of measured frequency.
Fig. 4. Voltage and frequency dependences of capacitance C measured at 30 -C in (a) ITO/350-nm-thick PI/50-nm-thick P3HT MIS capacitor and in (b) Au/200-nm-thick Ta2O5/50-nm-thick P3HT MIS capacitor.
resistance of the bulk P3HT, and R S is a small series resistance associated with the electrodes. The relaxation frequency of the circuit, f R, is given by [21] fR ¼
1 : 2pRB ðC1 þ CB Þ
ð1Þ
For frequencies f b f R, the measured capacitance converges to C I ¨ 1.8 nF in sample B, on the other hand, the measured capacitance increases with decreasing frequency unlimitedly in sample A and it exceeds C I ¨ 110 pF. It is simply due to a spreading out of accumulated holes along P3HT/insulator interface on top of the gate electrode in sample A. Such an abnormal capacitance increase can be suppressed successfully by patterning the semiconductor layer with the help of shadow mask or just cutting the
semiconductor into desired shape before use, or the use of circular gold contact surrounded by a concentric guard ring connected to the ground. We have therefore adopted the patterned electrodes in all other samples will be discussed below. Fig. 6 shows the capacitance –voltage characteristics of sample B as a function of measured frequency. The capacitance remains almost constant in accumulation and it decreases steeply at the voltage region between + 2 and + 6 V. The capacitance becomes constant above + 6 V and it is almost independent of frequency. The capacitance value corresponds well with the series capacitance of the insulator and the P3HT depletion layer capacitance supporting that the film thickness of P3HT is 40 nm and the relative dielectric constant of Ta2O5, PI and P3HT as 20, 3, and 3.2 [20]. Of interest in Fig. 5 is that the capacitance starts to decrease at around V T ¨ 2 V deduced in Fig. 3, that is, the P3HT layer starts to deplete above V T ¨ + 2 V and it is completely depleted at +6 V. Moreover, it should be pointed out that the capacitance change at 1 kHz, for example, by V GS change is about 800 pF, and it is about 60 times larger
Fig. 5. Equivalent circuits for the device (a) in accumulation, (b) partially depleted, (c) incorporating interfacial states at the lower frequency lower than the relaxation frequency f R, and (d) the equivalent circuit of Fig. 5(c) converted into a frequency dependent capacitance C P in parallel with a frequency-dependent conductance G P.
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believe that bulk space charge contributes little in Eq. (2) and that the main contributor to the large values of V T observed in sample B comes from fixed negative charges in PI interfacial layer and partially from work-function difference. The net trapped charge density is estimated to be ¨ 5 1011 cm 2 from Fig. 5 and Eq. (2), and it becomes ¨ 1012 cm 2 if the total DV T with reference to V T in the P3HT-based FET prepared on single layer of Ta2O5 is taken into account. It is therefore suggested here that the capacitance measurement associated with FET properties is powerful method to investigate the electrical properties of P3HT-based FET, which is fabricated on Ta2O5 or double layered insulator. 3.2. CuPc-based FETs
Fig. 7. (a) Output characteristics (I DS – V DS) of the CuPc-FET prepared on 200-nm-thick Ta2O5 with channel width, W, of 2 mm and channel length, L, of 20 Am, where CuPc is evaporated only on the overlapping area of gate and the Au top stripes for drain and source electrodes by shadow mask. (b) Output characteristics (I DS – V DS) of CuPc-FET with ring electrode prepared on 200-nm-thick Ta2O5. The top Au electrodes with width, W, of 5.65 mm and channel length, L, of 75 Am were patterned by lift-off technique.
than that of sample A of ¨13 pF. The use of Ta2O5 layer or double layered insulator is thus a very effective way to investigate the electrical properties of MIS capacitor. Several possible factors can cause the shift DV T in the threshold voltage for P3HT-based FETs, for example, the work function difference, / MS, between gate electrode and semiconductor, a space charge in the bulk region of the insulator, and charges trapped in states at the insulator/ semiconductor interface. Their contributions to DV T are described by [15] Z dI / 1 Qit ð/s Þ DVT ¼ M S xqð xÞdx ; ð2Þ eS e0 0 CI q where q(x) is the space charge density in the insulator and C i is the insulator capacitance per unit area. Q it(/ S) is the net charge per unit area trapped in interface states and is a function of the degree of band bending at the interface and hence the potential / S of the semiconductor surface. The work function difference between gate Au electrode and P3HT is only ¨ 0.3 eV from the conventional surface potential measurement and therefore, makes a small contribution of / MS/q to the large DV T observed. Space charges can arise in the insulator from mobile ionic species and from trapped electronic charges. According to the previous studies, the excess charges or trapped charges in the bulk insulator is likely to be small enough since the excess charges in bulk insulator was removed during the heattreatment even in a 350-nm-thick PI and showed little change in V T at room temperature [21,22]. Therefore, we
Fig. 7(a) shows the output characteristics (I DS – V DS) of the 50 nm-thick-CuPc based FET with a 20-Am-long channel prepared on 200-nm-thick Ta2O5 gate insulator. Here, CuPc layer is evaporated only on the overlapping area of gate electrode and the Au top stripe evaporated for source and gate electrodes by shadow-mask to prevent the lateral leakage current between the adjacent devices. Fig. 7(a) shows good saturation behavior and a good ON/OFF ratio 1/2 of about 105. Fig. 8(a) shows the transfer characteristics (I DS vs. V GS) of the device used in Fig. 7(a). The field effect mobility, l CuPc, and the threshold voltage, V T, are deduced to be 4.0 10 3 cm2/V s and 1.5 V, respectively. The l CuPc obtained here is in the high-end of the reported values as CuPc [9,10]. Fig. 7(b) shows the output characteristics (I DS –V DS) of the 40-nm-thick CuPc based FET with a 75-Am-long concentric type channel prepared by Flift off_ technique on
Fig. 8. Transfer characteristics of the CuPc-FET patterned by (a) shadow mask and (b) lift-off technique.
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Fig. 9. The capacitance – voltage characteristics of Al/200-nm-thick Ta2O5/ 50-nm-thick CuPc MIS capacitor patterned by shadow mask as a function of measured frequency.
200-nm-thick Ta2O5 gate insulator. Here, the channel length L and the channel width W are 75 Am and 5650 Am, respectively. Here, the inner circular electrode was connected to source and the outer guard electrode was connected to drain electrodes, respectively. The drain current decreases about 1 order of magnitude compared to the device patterned by shadow-mask even though the W/L ratio decreases only by 25%. Fig. 8(b) shows the transfer 1/2 characteristics (I DS vs. V GS) of this device, after correcting for the small leakage current through the gate insulator. The field effect mobility, l CuPc, and the threshold voltage, V T, are deduced to be 5.6 10 4 cm 2/Vs and + 1.5 V, respectively. Of interest in Fig. 8(b) is the large subthreshold current for V GS > V T. That is, the CuPc-based FET prepared by conventional lift-off technique is not only damage the interface but also deteriorates the device stability. Figs. 9 and 10 show the voltage dependence of the capacitance and the loss, which is defined as the measured conductance G divided by angular frequency x, G/x, as a function of frequency. Here, the ratio of the measured capacitance to loss coincides with the ratio of real part to imaginary part of dielectric constant. The capacitance decreases with the gate voltage and then becomes constant for large positive V GS in both Figs. 9 and 10. Capacitance values also decreased with frequency, and an additional increase in the capacitance is observed at low frequency in the accumulation mode. It should be noted here that the calculated value of the Ta2O5 gate insulator is estimated to be ¨ 3150 pF for the CuPc-FET patterned by shadow mask in Fig. 9, whereas it becomes ¨ 2300 pF for the device patterned by lift-off in Fig. 10. That is, the measured capacitance coincides with the gate capacitance at only very low frequency region under accumulation. The capacitance
remains constant below the threshold voltage V T deduced from Fig. 8, and then decreases quickly above V T. A marked loss peak is also observed in this region. It is noted here that the deference in peak-voltage between Figs. 9 and 10 corresponds well with the threshold voltage difference in these devices. In Fig. 10, CuPc layer is fully depleted at + 7 V and the capacitance value becomes the series capacitance of C I and C d = ( 0( SA/d. Here, the ( S is the relative dielectric constant of CuPc ¨ 3 and d is the thickness of CuPc layer. Of interest is that this voltage coincides well with the voltage when the CuPc-based FET prepared by Flift-off_ technique becomes Foff state_ completely. The subthreshold current in Fig. 8(b) is therefore considered to be the JFET effect, that is, the current flows in the undepleted bulk [25] presumably due to the additional impurity formed during the photolithography process. It is therefore concluded that the use of C – V measurement with either patterned semiconductor or patterned ring electrode is suitable to discuss the electrical properties of OFETs, however, Flift-off_ techniques may damage the semiconductor even a stable semiconductor such as CuPc seriously. Fig. 11 shows the frequency dependence of the capacitance and the loss at V G = 6 V and V G = 0 V at the temperatures of 30, 50 and 70 -C in the device patterned by lift-off technique. It is clearly shown that there are two steps in the dispersion of capacitance and thus there are two remarkable peaks in the loss curve, and their frequency increases with temperature. It is interestingly to note that each capacitance value converges to the same value, the capacitance of the capacitance of the gate oxide ¨ 2300 pF, at low frequency. Similar behaviors were also observed in CuPc-FET patterned by shadow mask,
Fig. 10. The capacitance – voltage characteristics of Al/200-nm-thick Ta2O5/40-nm-thick CuPc MIS capacitor patterned by lift-off technique as a function of measured frequency.
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dependent capacitance C P in parallel with a frequencydependent conductance G P, as shown in Fig. 5(d). The values of C P and G P are described as [15,26], CP ¼ CD þ
CS ; 1 þ x 2 s2
ð3Þ
and GP CS xs ¼ : 1 þ x 2 s2 x
Fig. 11. The frequency dependences of capacitance C measured at 30, 50 and 70 -C Al/200-nm-thick Ta2O5/40-nm-thick CuPc MIS capacitor patterned by lift-off technique at V G = 6 V and 0 V.
however, the peak frequencies became higher than those of Fig. 11. The higher frequency peak in Fig. 11 is ascribed to the Maxwell-Wagner polarization discussed in Section 3.1, whereas the dispersion at low frequency region is considered in terms of the interfacial traps. If the influence of interfacial capacitance related to the interfacial trapped charge is negligibly small, the equivalent circuit of MIS capacitor will be described as Fig. 5(b) at the voltage larger than V T. And thus the measured capacitance C changes as a function of the gate voltage between C I and the series capacitance of C I and C d. The basic equivalent circuit incorporating the interface trap effect is shown in Fig. 5(c) for f b f R in Eq. (1) assuming the impedance of the parallel branch of the bulk capacitance and resistance is negligibly small. Here C it and R it are the capacitance and resistance associated with the interface traps, and are the functions of build-up potential at the interface. The product C SR S is the interface-trap lifetime. The low frequency peak in Fig. 11 is thus a strong evidence of interfacial capacitance [15,26]. From surface analysis of Ta2O5 by AFM (SHIMADZU SPM-9500J), the surface image of Ta2O5 is displaying a rather coarse, granular structure and the rootmean-square (rms) roughness of 2.1 nm was observed over a 1 Am 1 Am area (not shown). Such a structural disorder at the Ta2O5 surface may produce the deep, high density of interfacial traps. Further investigation should be investigated in the near future related to the interfacial roughness. 3.3. Analysis of capacitance curves The parallel branch of the equivalent circuit of equivalent circuit in Fig. 5(c) will be converted to a frequency-
ð4Þ
Here, s is the interface-trap lifetime C SR S. Since Eq. (4) does not contain C D and depends only on the interfacial trap branch of the equivalent circuit in Fig. 5(d). A plot of G P/x at the maximum is C S/2. And once C S is known, the interfacial-trap density is obtained by using the relation D it = C S/qA. After subtracting the reactance of the insulator capacitance from measured impedance and converted back into the admittance, the value of G P is estimated. The interface-trap density D it is thus calculated from the C – V and the loss curve G/x (loss) – V curves using the following relation [26,27]: #1 " 2 Gmax Gmax 2 Cmax 2 Dit ¼ þ 1 ; ð5Þ qA x xCI CI where q is the electronic charge, G max/x is the peak value of the loss and C max is the capacitance corresponding to G max. From C–V and the loss –V curves in Figs 9 and 10, the D it values is estimated as 8.2 1011 eV 1 cm 2 for CuPc-FET patterned by lift-off, whereas it is estimated as 2.8 1011 eV 1 cm 2 for CuPc-FET patterned by shadow mask, respectively. The larger value of D it estimated here in the device patterned by lift-off may thus cause the smaller value of the field effect mobility in Fig. 8. Generally, the C – V characteristics depends on the density and the depth profile of the acceptors in p-type semiconductors, such as CuPc and P3HT. According to the Mott-Schottky analysis, the capacitance at a certain gate bias corresponds to the depletion depth, d depl, in the semiconductor layer by: ddepl ¼ e0 es A=ð1=C 1=CI Þ:
ð6Þ
Eq. (6) may hold when the contribution of the interfacial capacitance and minority carriers can be disregarded or they are incorporated to the depletion layer capacitance C D. The acceptor density, N A, at the depletion edge x at the given voltage determined using the Mott-Schottky relation [15,26]: NA ¼
2 qe0 eS A2
1 2 BCHF BVGS
;
ð7Þ
where C HF is the MIS high-frequency capacitance below the Maxwell-Wagner relaxation frequency f R discussed in Eq. (1). When the interface states (or traps) are present they affect the slope of the 1/C 2HF vs. V curves, that is, the
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interfacial capacitance or depletion layer capacitance which is difficult to cancel out, and it is estimated as 19 nF for P3HT FET prepared on Ta2O5/PI double layer and 30 nF for CuPc FET prepared by shadow mask. By substituting these values into (C depl + C it ) in conventional equation of subthreshold swing S [15,26]: Cdepl þ Cit BVGS kT ln10 1 þ Su , ; BðlogIDS Þ q CI
Fig. 12. The corrected doing profiles obtained from Eq. (8) for CuPc- and P3HT-MIS capacitors calculated from the capacitance curves at 100 Hz and 3 kHz, respectively, from Figs. 6, 9 and 10). Only C LC of CuPc-MIS capacitor patterned by lift-off was calculated from C – V curve at 30 Hz.
ð10Þ
S values are estimated as 1.0 V/dec for P3HT FET and 0.64 V/dec for CuPc FET, corresponds well to the experimental values of 0.93 V/dec and 0.82 V/dec from transfer characteristics, respectively. It is therefore predicted here that S value will be improved more using smooth, clean high K gate dielectric thin film as an gate insulator and decreasing the interfacial capacitance.
4. Conclusion interfacial states causes the Fstretch-out_ of C – V curves. According to Brews [28], this stretch-out effect can be easily corrected by using following equation whether or not interface states are present: !1 2 1 CLF =CI dð1=CHF Þ2 NAV ¼ ; ð8Þ qe0 eS A2 1 CHF =CI dV where C LF is the quasi-static low-frequency capacitance obtained by C – V measurement corresponding to C HF. In Eq. (8), the range of distance for which the doping profile can be determined to within 5% accuracy is x > 3L D, where L D is the bulk (extrinsic) Debye length [15]: 1=2 LD ¼ kT e0 eS =q2 NAV :
ð9Þ
Fig. 12 shows the corrected doing profiles obtained from Eq. (8) for CuPc- and P3HT-MIS capacitors calculated from the capacitance curves at 100 Hz and 3 kHz, respectively, from Figs. 6, 9 and 10. Only C LC of CuPc-MIS capacitor patterned by lift-off was calculated from C–V curve at 30 Hz because it gives the low frequency dispersion at the frequency around 100 Hz. A very high density of acceptor states is calculated in the vicinity of the insulator/semiconductor interface and it decreases steeply within 10 nm from the interface in Fig. 12. Here the bulk acceptor densities are estimated as approximately 3 1023 m 3 for CuPc and 1 1023 m 3 for P3HT from the rough average of N A between x = 15 and 30 nm, and thus L D are roughly estimated as 6.2 nm for P3HT and 3.8 nm for CuPc, respectively. Therefore, this fast decrease in N A may be ascribed to the stretching-out of carriers at the interface. The distribution of interface states should also be taken into account since N A decreases too fast and it is still decreasing at the distance larger than 3L D. From the minimum values of d depl in Eq. (6) and Fig. 12, one can estimate the very large
We have investigated the electrical characteristics of metal-insulator semiconductor (MIS) capacitors consisting of p-type semiconductor layer, either regio-regular poly(3hexylthiophene) (P3HT) or copper-phthalocyanine (CuPc) prepared on the tantalum oxide, with a high dielectric constant (¨ 20), or double layered structure consisting of tantalum oxide and very thin polyimide. These results are combined with FET properties and conventional surface potential measurements and discussed in terms of the interfacial capacitance and charge exchange phenomena at the semiconductor/insulator interface. The use of Ta2O5 layer as an insulator is not only an effective way to reduce operating voltage of field effect transistor but also a useful way to investigate the capacitance change ascribed to the interfacial capacitance or the interfacial electronic states at the interface. From capacitance measurement, the voltage when the capacitance starts to decrease coincides well with the threshold voltage of FET, V T, and the CuPc FET patterned by lift-off technique can be completely turn-off only when the MIS capacitor is fully depleted due to the large JFET current. The positive shift of threshold voltage in P3HT FET prepared on PI is discussed in terms of the interfacial fixed charges due to the charge exchange between the electron accepting PI and electron donating P3HT. And such a voltage shift and the loss peak in the loss – V curves were explained in terms of interfacial trap density. Finally, the acceptor-profile in semiconductors was also calculated. It was found that very high density of states exists at the insulator/semiconductor interface and it decreases very quickly suggesting the large density of interfacial traps exist and it produces the large interfacial capacitance. The large interfacial capacitance may cause the large subthreshold swing and it can be reduced by using high K gate dielectric thin film and reducing the interfacial capacitance.
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Acknowledgements The authors acknowledge useful discussions with D.M. Taylor, I. Torres, T. Murayama, and T. Highchi. This work was supported by the CLUSTER of the Ministry of Education, Culture, Sports, Science and Technology, Japan.
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